drivers/i2c/busses/i2c-rcar.c

   1 /*
   2  *  drivers/i2c/busses/i2c-rcar.c
   3  *
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This file is based on the drivers/i2c/busses/i2c-sh7760.c
   8  * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
   9  *
  10  * This file used out-of-tree driver i2c-rcar.c
  11  * Copyright (C) 2011-2012 Renesas Electronics Corporation
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  25  */
  26 #include <linux/clk.h>
  27 #include <linux/delay.h>
  28 #include <linux/err.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/i2c.h>
  32 #include <linux/i2c/i2c-rcar.h>
  33 #include <linux/kernel.h>
  34 #include <linux/module.h>
  35 #include <linux/of_device.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38 #include <linux/slab.h>
  39 #include <linux/spinlock.h>
  40
  41 /* register offsets */
  42 #define ICSCR   0x00    /* slave ctrl */
  43 #define ICMCR   0x04    /* master ctrl */
  44 #define ICSSR   0x08    /* slave status */
  45 #define ICMSR   0x0C    /* master status */
  46 #define ICSIER  0x10    /* slave irq enable */
  47 #define ICMIER  0x14    /* master irq enable */
  48 #define ICCCR   0x18    /* clock dividers */
  49 #define ICSAR   0x1C    /* slave address */
  50 #define ICMAR   0x20    /* master address */
  51 #define ICRXTX  0x24    /* data port */
  52
  53 /* ICMCR */
  54 #define MDBS    (1 << 7)        /* non-fifo mode switch */
  55 #define FSCL    (1 << 6)        /* override SCL pin */
  56 #define FSDA    (1 << 5)        /* override SDA pin */
  57 #define OBPC    (1 << 4)        /* override pins */
  58 #define MIE     (1 << 3)        /* master if enable */
  59 #define TSBE    (1 << 2)
  60 #define FSB     (1 << 1)        /* force stop bit */
  61 #define ESG     (1 << 0)        /* en startbit gen */
  62
  63 /* ICMSR */
  64 #define MNR     (1 << 6)        /* nack received */
  65 #define MAL     (1 << 5)        /* arbitration lost */
  66 #define MST     (1 << 4)        /* sent a stop */
  67 #define MDE     (1 << 3)
  68 #define MDT     (1 << 2)
  69 #define MDR     (1 << 1)
  70 #define MAT     (1 << 0)        /* slave addr xfer done */
  71
  72 /* ICMIE */
  73 #define MNRE    (1 << 6)        /* nack irq en */
  74 #define MALE    (1 << 5)        /* arblos irq en */
  75 #define MSTE    (1 << 4)        /* stop irq en */
  76 #define MDEE    (1 << 3)
  77 #define MDTE    (1 << 2)
  78 #define MDRE    (1 << 1)
  79 #define MATE    (1 << 0)        /* address sent irq en */
  80
  81
  82 #define RCAR_BUS_PHASE_START    (MDBS | MIE | ESG)
  83 #define RCAR_BUS_PHASE_DATA     (MDBS | MIE)
  84 #define RCAR_BUS_PHASE_STOP     (MDBS | MIE | FSB)
  85
  86 #define RCAR_IRQ_SEND   (MNRE | MALE | MSTE | MATE | MDEE)
  87 #define RCAR_IRQ_RECV   (MNRE | MALE | MSTE | MATE | MDRE)
  88 #define RCAR_IRQ_STOP   (MSTE)
  89
  90 #define RCAR_IRQ_ACK_SEND       (~(MAT | MDE))
  91 #define RCAR_IRQ_ACK_RECV       (~(MAT | MDR))
  92
  93 /*
  94  * flags
  95  */
  96 #define ID_LAST_MSG     (1 << 0)
  97 #define ID_IOERROR      (1 << 1)
  98 #define ID_DONE         (1 << 2)
  99 #define ID_ARBLOST      (1 << 3)
 100 #define ID_NACK         (1 << 4)
 101
 102 enum rcar_i2c_type {
 103         I2C_RCAR_GEN1,
 104         I2C_RCAR_GEN2,
 105 };
 106
 107 struct rcar_i2c_priv {
 108         void __iomem *io;
 109         struct i2c_adapter adap;
 110         struct i2c_msg  *msg;
 111         struct clk *clk;
 112
 113         spinlock_t lock;
 114         wait_queue_head_t wait;
 115
 116         int pos;
 117         u32 icccr;
 118         u32 flags;
 119         enum rcar_i2c_type      devtype;
 120 };
 121
 122 #define rcar_i2c_priv_to_dev(p)         ((p)->adap.dev.parent)
 123 #define rcar_i2c_is_recv(p)             ((p)->msg->flags & I2C_M_RD)
 124
 125 #define rcar_i2c_flags_set(p, f)        ((p)->flags |= (f))
 126 #define rcar_i2c_flags_has(p, f)        ((p)->flags & (f))
 127
 128 #define LOOP_TIMEOUT    1024
 129
 130 /*
 131  *              basic functions
 132  */
 133 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
 134 {
 135         writel(val, priv->io + reg);
 136 }
 137
 138 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
 139 {
 140         return readl(priv->io + reg);
 141 }
 142
 143 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
 144 {
 145         /*
 146          * reset slave mode.
 147          * slave mode is not used on this driver
 148          */
 149         rcar_i2c_write(priv, ICSIER, 0);
 150         rcar_i2c_write(priv, ICSAR, 0);
 151         rcar_i2c_write(priv, ICSCR, 0);
 152         rcar_i2c_write(priv, ICSSR, 0);
 153
 154         /* reset master mode */
 155         rcar_i2c_write(priv, ICMIER, 0);
 156         rcar_i2c_write(priv, ICMCR, 0);
 157         rcar_i2c_write(priv, ICMSR, 0);
 158         rcar_i2c_write(priv, ICMAR, 0);
 159 }
 160
 161 /*
 162  *              bus control functions
 163  */
 164 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
 165 {
 166         int i;
 167
 168         for (i = 0; i < LOOP_TIMEOUT; i++) {
 169                 /* make sure that bus is not busy */
 170                 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
 171                         return 0;
 172                 udelay(1);
 173         }
 174
 175         return -EBUSY;
 176 }
 177
 178 /*
 179  *              clock function
 180  */
 181 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv,
 182                                     u32 bus_speed,
 183                                     struct device *dev)
 184 {
 185         u32 scgd, cdf;
 186         u32 round, ick;
 187         u32 scl;
 188         u32 cdf_width;
 189         unsigned long rate;
 190
 191         switch (priv->devtype) {
 192         case I2C_RCAR_GEN1:
 193                 cdf_width = 2;
 194                 break;
 195         case I2C_RCAR_GEN2:
 196                 cdf_width = 3;
 197                 break;
 198         default:
 199                 dev_err(dev, "device type error\n");
 200                 return -EIO;
 201         }
 202
 203         /*
 204          * calculate SCL clock
 205          * see
 206          *      ICCCR
 207          *
 208          * ick  = clkp / (1 + CDF)
 209          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 210          *
 211          * ick  : I2C internal clock < 20 MHz
 212          * ticf : I2C SCL falling time  =  35 ns here
 213          * tr   : I2C SCL rising  time  = 200 ns here
 214          * intd : LSI internal delay    =  50 ns here
 215          * clkp : peripheral_clk
 216          * F[]  : integer up-valuation
 217          */
 218         rate = clk_get_rate(priv->clk);
 219         cdf = rate / 20000000;
 220         if (cdf >= 1 << cdf_width) {
 221                 dev_err(dev, "Input clock %lu too high\n", rate);
 222                 return -EIO;
 223         }
 224         ick = rate / (cdf + 1);
 225
 226         /*
 227          * it is impossible to calculate large scale
 228          * number on u32. separate it
 229          *
 230          * F[(ticf + tr + intd) * ick]
 231          *  = F[(35 + 200 + 50)ns * ick]
 232          *  = F[285 * ick / 1000000000]
 233          *  = F[(ick / 1000000) * 285 / 1000]
 234          */
 235         round = (ick + 500000) / 1000000 * 285;
 236         round = (round + 500) / 1000;
 237
 238         /*
 239          * SCL  = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
 240          *
 241          * Calculation result (= SCL) should be less than
 242          * bus_speed for hardware safety
 243          *
 244          * We could use something along the lines of
 245          *      div = ick / (bus_speed + 1) + 1;
 246          *      scgd = (div - 20 - round + 7) / 8;
 247          *      scl = ick / (20 + (scgd * 8) + round);
 248          * (not fully verified) but that would get pretty involved
 249          */
 250         for (scgd = 0; scgd < 0x40; scgd++) {
 251                 scl = ick / (20 + (scgd * 8) + round);
 252                 if (scl <= bus_speed)
 253                         goto scgd_find;
 254         }
 255         dev_err(dev, "it is impossible to calculate best SCL\n");
 256         return -EIO;
 257
 258 scgd_find:
 259         dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
 260                 scl, bus_speed, clk_get_rate(priv->clk), round, cdf, scgd);
 261
 262         /*
 263          * keep icccr value
 264          */
 265         priv->icccr = scgd << cdf_width | cdf;
 266
 267         return 0;
 268 }
 269
 270 /*
 271  *              status functions
 272  */
 273
 274 static int rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
 275 {
 276         int read = !!rcar_i2c_is_recv(priv);
 277
 278         rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
 279         rcar_i2c_write(priv, ICMSR, 0);
 280         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
 281         rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
 282
 283         return 0;
 284 }
 285
 286 /*
 287  *              interrupt functions
 288  */
 289 static int rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
 290 {
 291         struct i2c_msg *msg = priv->msg;
 292
 293         /*
 294          * FIXME
 295          * sometimes, unknown interrupt happened.
 296          * Do nothing
 297          */
 298         if (!(msr & MDE))
 299                 return 0;
 300
 301         /*
 302          * If address transfer phase finished,
 303          * goto data phase.
 304          */
 305         if (msr & MAT)
 306                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
 307
 308         if (priv->pos < msg->len) {
 309                 /*
 310                  * Prepare next data to ICRXTX register.
 311                  * This data will go to _SHIFT_ register.
 312                  *
 313                  *    *
 314                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
 315                  */
 316                 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
 317                 priv->pos++;
 318
 319         } else {
 320                 /*
 321                  * The last data was pushed to ICRXTX on _PREV_ empty irq.
 322                  * It is on _SHIFT_ register, and will sent to I2C bus.
 323                  *
 324                  *                *
 325                  * [ICRXTX] -> [SHIFT] -> [I2C bus]
 326                  */
 327
 328                 if (priv->flags & ID_LAST_MSG)
 329                         /*
 330                          * If current msg is the _LAST_ msg,
 331                          * prepare stop condition here.
 332                          * ID_DONE will be set on STOP irq.
 333                          */
 334                         rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
 335                 else
 336                         /*
 337                          * If current msg is _NOT_ last msg,
 338                          * it doesn't call stop phase.
 339                          * thus, there is no STOP irq.
 340                          * return ID_DONE here.
 341                          */
 342                         return ID_DONE;
 343         }
 344
 345         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
 346
 347         return 0;
 348 }
 349
 350 static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
 351 {
 352         struct i2c_msg *msg = priv->msg;
 353
 354         /*
 355          * FIXME
 356          * sometimes, unknown interrupt happened.
 357          * Do nothing
 358          */
 359         if (!(msr & MDR))
 360                 return 0;
 361
 362         if (msr & MAT) {
 363                 /*
 364                  * Address transfer phase finished,
 365                  * but, there is no data at this point.
 366                  * Do nothing.
 367                  */
 368         } else if (priv->pos < msg->len) {
 369                 /*
 370                  * get received data
 371                  */
 372                 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
 373                 priv->pos++;
 374         }
 375
 376         /*
 377          * If next received data is the _LAST_,
 378          * go to STOP phase,
 379          * otherwise, go to DATA phase.
 380          */
 381         if (priv->pos + 1 >= msg->len)
 382                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
 383         else
 384                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_DATA);
 385
 386         rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
 387
 388         return 0;
 389 }
 390
 391 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
 392 {
 393         struct rcar_i2c_priv *priv = ptr;
 394         struct device *dev = rcar_i2c_priv_to_dev(priv);
 395         u32 msr;
 396
 397         /*-------------- spin lock -----------------*/
 398         spin_lock(&priv->lock);
 399
 400         msr = rcar_i2c_read(priv, ICMSR);
 401
 402         /*
 403          * Arbitration lost
 404          */
 405         if (msr & MAL) {
 406                 /*
 407                  * CAUTION
 408                  *
 409                  * When arbitration lost, device become _slave_ mode.
 410                  */
 411                 dev_dbg(dev, "Arbitration Lost\n");
 412                 rcar_i2c_flags_set(priv, (ID_DONE | ID_ARBLOST));
 413                 goto out;
 414         }
 415
 416         /*
 417          * Stop
 418          */
 419         if (msr & MST) {
 420                 dev_dbg(dev, "Stop\n");
 421                 rcar_i2c_flags_set(priv, ID_DONE);
 422                 goto out;
 423         }
 424
 425         /*
 426          * Nack
 427          */
 428         if (msr & MNR) {
 429                 dev_dbg(dev, "Nack\n");
 430
 431                 /* go to stop phase */
 432                 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
 433                 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
 434                 rcar_i2c_flags_set(priv, ID_NACK);
 435                 goto out;
 436         }
 437
 438         /*
 439          * recv/send
 440          */
 441         if (rcar_i2c_is_recv(priv))
 442                 rcar_i2c_flags_set(priv, rcar_i2c_irq_recv(priv, msr));
 443         else
 444                 rcar_i2c_flags_set(priv, rcar_i2c_irq_send(priv, msr));
 445
 446 out:
 447         if (rcar_i2c_flags_has(priv, ID_DONE)) {
 448                 rcar_i2c_write(priv, ICMIER, 0);
 449                 rcar_i2c_write(priv, ICMSR, 0);
 450                 wake_up(&priv->wait);
 451         }
 452
 453         spin_unlock(&priv->lock);
 454         /*-------------- spin unlock -----------------*/
 455
 456         return IRQ_HANDLED;
 457 }
 458
 459 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
 460                                 struct i2c_msg *msgs,
 461                                 int num)
 462 {
 463         struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
 464         struct device *dev = rcar_i2c_priv_to_dev(priv);
 465         unsigned long flags;
 466         int i, ret, timeout;
 467
 468         pm_runtime_get_sync(dev);
 469
 470         /*-------------- spin lock -----------------*/
 471         spin_lock_irqsave(&priv->lock, flags);
 472
 473         rcar_i2c_init(priv);
 474         /* start clock */
 475         rcar_i2c_write(priv, ICCCR, priv->icccr);
 476
 477         spin_unlock_irqrestore(&priv->lock, flags);
 478         /*-------------- spin unlock -----------------*/
 479
 480         ret = rcar_i2c_bus_barrier(priv);
 481         if (ret < 0)
 482                 goto out;
 483
 484         for (i = 0; i < num; i++) {
 485                 /* This HW can't send STOP after address phase */
 486                 if (msgs[i].len == 0) {
 487                         ret = -EOPNOTSUPP;
 488                         break;
 489                 }
 490
 491                 /*-------------- spin lock -----------------*/
 492                 spin_lock_irqsave(&priv->lock, flags);
 493
 494                 /* init each data */
 495                 priv->msg       = &msgs[i];
 496                 priv->pos       = 0;
 497                 priv->flags     = 0;
 498                 if (priv->msg == &msgs[num - 1])
 499                         rcar_i2c_flags_set(priv, ID_LAST_MSG);
 500
 501                 ret = rcar_i2c_prepare_msg(priv);
 502
 503                 spin_unlock_irqrestore(&priv->lock, flags);
 504                 /*-------------- spin unlock -----------------*/
 505
 506                 if (ret < 0)
 507                         break;
 508
 509                 /*
 510                  * wait result
 511                  */
 512                 timeout = wait_event_timeout(priv->wait,
 513                                              rcar_i2c_flags_has(priv, ID_DONE),
 514                                              5 * HZ);
 515                 if (!timeout) {
 516                         ret = -ETIMEDOUT;
 517                         break;
 518                 }
 519
 520                 /*
 521                  * error handling
 522                  */
 523                 if (rcar_i2c_flags_has(priv, ID_NACK)) {
 524                         ret = -ENXIO;
 525                         break;
 526                 }
 527
 528                 if (rcar_i2c_flags_has(priv, ID_ARBLOST)) {
 529                         ret = -EAGAIN;
 530                         break;
 531                 }
 532
 533                 if (rcar_i2c_flags_has(priv, ID_IOERROR)) {
 534                         ret = -EIO;
 535                         break;
 536                 }
 537
 538                 ret = i + 1; /* The number of transfer */
 539         }
 540 out:
 541         pm_runtime_put(dev);
 542
 543         if (ret < 0 && ret != -ENXIO)
 544                 dev_err(dev, "error %d : %x\n", ret, priv->flags);
 545
 546         return ret;
 547 }
 548
 549 static u32 rcar_i2c_func(struct i2c_adapter *adap)
 550 {
 551         /* This HW can't do SMBUS_QUICK and NOSTART */
 552         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 553 }
 554
 555 static const struct i2c_algorithm rcar_i2c_algo = {
 556         .master_xfer    = rcar_i2c_master_xfer,
 557         .functionality  = rcar_i2c_func,
 558 };
 559
 560 static const struct of_device_id rcar_i2c_dt_ids[] = {
 561         { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
 562         { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
 563         { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
 564         { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
 565         { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
 566         { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
 567         { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
 568         { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
 569         {},
 570 };
 571 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
 572
 573 static int rcar_i2c_probe(struct platform_device *pdev)
 574 {
 575         struct i2c_rcar_platform_data *pdata = dev_get_platdata(&pdev->dev);
 576         struct rcar_i2c_priv *priv;
 577         struct i2c_adapter *adap;
 578         struct resource *res;
 579         struct device *dev = &pdev->dev;
 580         u32 bus_speed;
 581         int irq, ret;
 582
 583         priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
 584         if (!priv) {
 585                 dev_err(dev, "no mem for private data\n");
 586                 return -ENOMEM;
 587         }
 588
 589         priv->clk = devm_clk_get(dev, NULL);
 590         if (IS_ERR(priv->clk)) {
 591                 dev_err(dev, "cannot get clock\n");
 592                 return PTR_ERR(priv->clk);
 593         }
 594
 595         bus_speed = 100000; /* default 100 kHz */
 596         ret = of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed);
 597         if (ret < 0 && pdata && pdata->bus_speed)
 598                 bus_speed = pdata->bus_speed;
 599
 600         if (pdev->dev.of_node)
 601                 priv->devtype = (long)of_match_device(rcar_i2c_dt_ids,
 602                                                       dev)->data;
 603         else
 604                 priv->devtype = platform_get_device_id(pdev)->driver_data;
 605
 606         ret = rcar_i2c_clock_calculate(priv, bus_speed, dev);
 607         if (ret < 0)
 608                 return ret;
 609
 610         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 611         priv->io = devm_ioremap_resource(dev, res);
 612         if (IS_ERR(priv->io))
 613                 return PTR_ERR(priv->io);
 614
 615         irq = platform_get_irq(pdev, 0);
 616         init_waitqueue_head(&priv->wait);
 617         spin_lock_init(&priv->lock);
 618
 619         adap                    = &priv->adap;
 620         adap->nr                = pdev->id;
 621         adap->algo              = &rcar_i2c_algo;
 622         adap->class             = I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED;
 623         adap->retries           = 3;
 624         adap->dev.parent        = dev;
 625         adap->dev.of_node       = dev->of_node;
 626         i2c_set_adapdata(adap, priv);
 627         strlcpy(adap->name, pdev->name, sizeof(adap->name));
 628
 629         ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0,
 630                                dev_name(dev), priv);
 631         if (ret < 0) {
 632                 dev_err(dev, "cannot get irq %d\n", irq);
 633                 return ret;
 634         }
 635
 636         ret = i2c_add_numbered_adapter(adap);
 637         if (ret < 0) {
 638                 dev_err(dev, "reg adap failed: %d\n", ret);
 639                 return ret;
 640         }
 641
 642         pm_runtime_enable(dev);
 643         platform_set_drvdata(pdev, priv);
 644
 645         dev_info(dev, "probed\n");
 646
 647         return 0;
 648 }
 649
 650 static int rcar_i2c_remove(struct platform_device *pdev)
 651 {
 652         struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
 653         struct device *dev = &pdev->dev;
 654
 655         i2c_del_adapter(&priv->adap);
 656         pm_runtime_disable(dev);
 657
 658         return 0;
 659 }
 660
 661 static struct platform_device_id rcar_i2c_id_table[] = {
 662         { "i2c-rcar",           I2C_RCAR_GEN1 },
 663         { "i2c-rcar_gen1",      I2C_RCAR_GEN1 },
 664         { "i2c-rcar_gen2",      I2C_RCAR_GEN2 },
 665         {},
 666 };
 667 MODULE_DEVICE_TABLE(platform, rcar_i2c_id_table);
 668
 669 static struct platform_driver rcar_i2c_driver = {
 670         .driver = {
 671                 .name   = "i2c-rcar",
 672                 .owner  = THIS_MODULE,
 673                 .of_match_table = rcar_i2c_dt_ids,
 674         },
 675         .probe          = rcar_i2c_probe,
 676         .remove         = rcar_i2c_remove,
 677         .id_table       = rcar_i2c_id_table,
 678 };
 679
 680 module_platform_driver(rcar_i2c_driver);
 681
 682 MODULE_LICENSE("GPL");
 683 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
 684 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");