2 * BRIEF MODULE DESCRIPTION
3 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
5 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option) any later
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
13 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
14 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
15 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
16 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
17 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
18 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
19 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
21 * POSSIBILITY OF SUCH DAMAGE.
23 * You should have received a copy of the GNU General Public License along with
24 * this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
28 * Interface and Linux Device Driver" Application Note.
30 #include <linux/types.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/ide.h>
37 #include <linux/scatterlist.h>
39 #include <asm/mach-au1x00/au1xxx.h>
40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
41 #include <asm/mach-au1x00/au1xxx_ide.h>
43 #define DRV_NAME "au1200-ide"
44 #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
46 /* enable the burstmode in the dbdma */
47 #define IDE_AU1XXX_BURSTMODE 1
49 static _auide_hwif auide_hwif
;
51 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
53 static inline void auide_insw(unsigned long port
, void *addr
, u32 count
)
55 _auide_hwif
*ahwif
= &auide_hwif
;
59 if(!put_dest_flags(ahwif
->rx_chan
, (void*)addr
, count
<< 1,
61 printk(KERN_ERR
"%s failed %d\n", __func__
, __LINE__
);
64 ctp
= *((chan_tab_t
**)ahwif
->rx_chan
);
66 while (dp
->dscr_cmd0
& DSCR_CMD0_V
)
68 ctp
->cur_ptr
= au1xxx_ddma_get_nextptr_virt(dp
);
71 static inline void auide_outsw(unsigned long port
, void *addr
, u32 count
)
73 _auide_hwif
*ahwif
= &auide_hwif
;
77 if(!put_source_flags(ahwif
->tx_chan
, (void*)addr
,
78 count
<< 1, DDMA_FLAGS_NOIE
)) {
79 printk(KERN_ERR
"%s failed %d\n", __func__
, __LINE__
);
82 ctp
= *((chan_tab_t
**)ahwif
->tx_chan
);
84 while (dp
->dscr_cmd0
& DSCR_CMD0_V
)
86 ctp
->cur_ptr
= au1xxx_ddma_get_nextptr_virt(dp
);
89 static void au1xxx_input_data(ide_drive_t
*drive
, struct ide_cmd
*cmd
,
90 void *buf
, unsigned int len
)
92 auide_insw(drive
->hwif
->io_ports
.data_addr
, buf
, (len
+ 1) / 2);
95 static void au1xxx_output_data(ide_drive_t
*drive
, struct ide_cmd
*cmd
,
96 void *buf
, unsigned int len
)
98 auide_outsw(drive
->hwif
->io_ports
.data_addr
, buf
, (len
+ 1) / 2);
102 static void au1xxx_set_pio_mode(ide_hwif_t
*hwif
, ide_drive_t
*drive
)
104 int mem_sttime
= 0, mem_stcfg
= au_readl(MEM_STCFG2
);
106 switch (drive
->pio_mode
- XFER_PIO_0
) {
108 mem_sttime
= SBC_IDE_TIMING(PIO0
);
110 /* set configuration for RCS2# */
111 mem_stcfg
|= TS_MASK
;
112 mem_stcfg
&= ~TCSOE_MASK
;
113 mem_stcfg
&= ~TOECS_MASK
;
114 mem_stcfg
|= SBC_IDE_PIO0_TCSOE
| SBC_IDE_PIO0_TOECS
;
118 mem_sttime
= SBC_IDE_TIMING(PIO1
);
120 /* set configuration for RCS2# */
121 mem_stcfg
|= TS_MASK
;
122 mem_stcfg
&= ~TCSOE_MASK
;
123 mem_stcfg
&= ~TOECS_MASK
;
124 mem_stcfg
|= SBC_IDE_PIO1_TCSOE
| SBC_IDE_PIO1_TOECS
;
128 mem_sttime
= SBC_IDE_TIMING(PIO2
);
130 /* set configuration for RCS2# */
131 mem_stcfg
&= ~TS_MASK
;
132 mem_stcfg
&= ~TCSOE_MASK
;
133 mem_stcfg
&= ~TOECS_MASK
;
134 mem_stcfg
|= SBC_IDE_PIO2_TCSOE
| SBC_IDE_PIO2_TOECS
;
138 mem_sttime
= SBC_IDE_TIMING(PIO3
);
140 /* set configuration for RCS2# */
141 mem_stcfg
&= ~TS_MASK
;
142 mem_stcfg
&= ~TCSOE_MASK
;
143 mem_stcfg
&= ~TOECS_MASK
;
144 mem_stcfg
|= SBC_IDE_PIO3_TCSOE
| SBC_IDE_PIO3_TOECS
;
149 mem_sttime
= SBC_IDE_TIMING(PIO4
);
151 /* set configuration for RCS2# */
152 mem_stcfg
&= ~TS_MASK
;
153 mem_stcfg
&= ~TCSOE_MASK
;
154 mem_stcfg
&= ~TOECS_MASK
;
155 mem_stcfg
|= SBC_IDE_PIO4_TCSOE
| SBC_IDE_PIO4_TOECS
;
159 au_writel(mem_sttime
,MEM_STTIME2
);
160 au_writel(mem_stcfg
,MEM_STCFG2
);
163 static void auide_set_dma_mode(ide_hwif_t
*hwif
, ide_drive_t
*drive
)
165 int mem_sttime
= 0, mem_stcfg
= au_readl(MEM_STCFG2
);
167 switch (drive
->dma_mode
) {
168 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
170 mem_sttime
= SBC_IDE_TIMING(MDMA2
);
172 /* set configuration for RCS2# */
173 mem_stcfg
&= ~TS_MASK
;
174 mem_stcfg
&= ~TCSOE_MASK
;
175 mem_stcfg
&= ~TOECS_MASK
;
176 mem_stcfg
|= SBC_IDE_MDMA2_TCSOE
| SBC_IDE_MDMA2_TOECS
;
180 mem_sttime
= SBC_IDE_TIMING(MDMA1
);
182 /* set configuration for RCS2# */
183 mem_stcfg
&= ~TS_MASK
;
184 mem_stcfg
&= ~TCSOE_MASK
;
185 mem_stcfg
&= ~TOECS_MASK
;
186 mem_stcfg
|= SBC_IDE_MDMA1_TCSOE
| SBC_IDE_MDMA1_TOECS
;
190 mem_sttime
= SBC_IDE_TIMING(MDMA0
);
192 /* set configuration for RCS2# */
193 mem_stcfg
|= TS_MASK
;
194 mem_stcfg
&= ~TCSOE_MASK
;
195 mem_stcfg
&= ~TOECS_MASK
;
196 mem_stcfg
|= SBC_IDE_MDMA0_TCSOE
| SBC_IDE_MDMA0_TOECS
;
202 au_writel(mem_sttime
,MEM_STTIME2
);
203 au_writel(mem_stcfg
,MEM_STCFG2
);
207 * Multi-Word DMA + DbDMA functions
210 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
211 static int auide_build_dmatable(ide_drive_t
*drive
, struct ide_cmd
*cmd
)
213 ide_hwif_t
*hwif
= drive
->hwif
;
214 _auide_hwif
*ahwif
= &auide_hwif
;
215 struct scatterlist
*sg
;
216 int i
= cmd
->sg_nents
, count
= 0;
217 int iswrite
= !!(cmd
->tf_flags
& IDE_TFLAG_WRITE
);
219 /* Save for interrupt context */
220 ahwif
->drive
= drive
;
222 /* fill the descriptors */
224 while (i
&& sg_dma_len(sg
)) {
228 cur_addr
= sg_dma_address(sg
);
229 cur_len
= sg_dma_len(sg
);
232 u32 flags
= DDMA_FLAGS_NOIE
;
233 unsigned int tc
= (cur_len
< 0xfe00)? cur_len
: 0xfe00;
235 if (++count
>= PRD_ENTRIES
) {
236 printk(KERN_WARNING
"%s: DMA table too small\n",
241 /* Lets enable intr for the last descriptor only */
243 flags
= DDMA_FLAGS_IE
;
245 flags
= DDMA_FLAGS_NOIE
;
248 if(!put_source_flags(ahwif
->tx_chan
,
251 printk(KERN_ERR
"%s failed %d\n",
256 if(!put_dest_flags(ahwif
->rx_chan
,
259 printk(KERN_ERR
"%s failed %d\n",
274 return 0; /* revert to PIO for this request */
277 static int auide_dma_end(ide_drive_t
*drive
)
282 static void auide_dma_start(ide_drive_t
*drive
)
287 static int auide_dma_setup(ide_drive_t
*drive
, struct ide_cmd
*cmd
)
289 if (auide_build_dmatable(drive
, cmd
) == 0)
295 static int auide_dma_test_irq(ide_drive_t
*drive
)
297 /* If dbdma didn't execute the STOP command yet, the
298 * active bit is still set
300 drive
->waiting_for_dma
++;
301 if (drive
->waiting_for_dma
>= DMA_WAIT_TIMEOUT
) {
302 printk(KERN_WARNING
"%s: timeout waiting for ddma to \
303 complete\n", drive
->name
);
310 static void auide_dma_host_set(ide_drive_t
*drive
, int on
)
314 static void auide_ddma_tx_callback(int irq
, void *param
)
318 static void auide_ddma_rx_callback(int irq
, void *param
)
321 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
323 static void auide_init_dbdma_dev(dbdev_tab_t
*dev
, u32 dev_id
, u32 tsize
, u32 devwidth
, u32 flags
)
325 dev
->dev_id
= dev_id
;
326 dev
->dev_physaddr
= (u32
)IDE_PHYS_ADDR
;
327 dev
->dev_intlevel
= 0;
328 dev
->dev_intpolarity
= 0;
329 dev
->dev_tsize
= tsize
;
330 dev
->dev_devwidth
= devwidth
;
331 dev
->dev_flags
= flags
;
334 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
335 static const struct ide_dma_ops au1xxx_dma_ops
= {
336 .dma_host_set
= auide_dma_host_set
,
337 .dma_setup
= auide_dma_setup
,
338 .dma_start
= auide_dma_start
,
339 .dma_end
= auide_dma_end
,
340 .dma_test_irq
= auide_dma_test_irq
,
341 .dma_lost_irq
= ide_dma_lost_irq
,
344 static int auide_ddma_init(ide_hwif_t
*hwif
, const struct ide_port_info
*d
)
346 _auide_hwif
*auide
= &auide_hwif
;
347 dbdev_tab_t source_dev_tab
, target_dev_tab
;
348 u32 dev_id
, tsize
, devwidth
, flags
;
350 dev_id
= IDE_DDMA_REQ
;
353 devwidth
= 32; /* 16 */
355 #ifdef IDE_AU1XXX_BURSTMODE
356 flags
= DEV_FLAGS_SYNC
| DEV_FLAGS_BURSTABLE
;
358 flags
= DEV_FLAGS_SYNC
;
361 /* setup dev_tab for tx channel */
362 auide_init_dbdma_dev( &source_dev_tab
,
364 tsize
, devwidth
, DEV_FLAGS_OUT
| flags
);
365 auide
->tx_dev_id
= au1xxx_ddma_add_device( &source_dev_tab
);
367 auide_init_dbdma_dev( &source_dev_tab
,
369 tsize
, devwidth
, DEV_FLAGS_IN
| flags
);
370 auide
->rx_dev_id
= au1xxx_ddma_add_device( &source_dev_tab
);
372 /* We also need to add a target device for the DMA */
373 auide_init_dbdma_dev( &target_dev_tab
,
374 (u32
)DSCR_CMD0_ALWAYS
,
375 tsize
, devwidth
, DEV_FLAGS_ANYUSE
);
376 auide
->target_dev_id
= au1xxx_ddma_add_device(&target_dev_tab
);
378 /* Get a channel for TX */
379 auide
->tx_chan
= au1xxx_dbdma_chan_alloc(auide
->target_dev_id
,
381 auide_ddma_tx_callback
,
384 /* Get a channel for RX */
385 auide
->rx_chan
= au1xxx_dbdma_chan_alloc(auide
->rx_dev_id
,
386 auide
->target_dev_id
,
387 auide_ddma_rx_callback
,
390 auide
->tx_desc_head
= (void*)au1xxx_dbdma_ring_alloc(auide
->tx_chan
,
392 auide
->rx_desc_head
= (void*)au1xxx_dbdma_ring_alloc(auide
->rx_chan
,
395 /* FIXME: check return value */
396 (void)ide_allocate_dma_engine(hwif
);
398 au1xxx_dbdma_start( auide
->tx_chan
);
399 au1xxx_dbdma_start( auide
->rx_chan
);
404 static int auide_ddma_init(ide_hwif_t
*hwif
, const struct ide_port_info
*d
)
406 _auide_hwif
*auide
= &auide_hwif
;
407 dbdev_tab_t source_dev_tab
;
410 #ifdef IDE_AU1XXX_BURSTMODE
411 flags
= DEV_FLAGS_SYNC
| DEV_FLAGS_BURSTABLE
;
413 flags
= DEV_FLAGS_SYNC
;
416 /* setup dev_tab for tx channel */
417 auide_init_dbdma_dev( &source_dev_tab
,
418 (u32
)DSCR_CMD0_ALWAYS
,
419 8, 32, DEV_FLAGS_OUT
| flags
);
420 auide
->tx_dev_id
= au1xxx_ddma_add_device( &source_dev_tab
);
422 auide_init_dbdma_dev( &source_dev_tab
,
423 (u32
)DSCR_CMD0_ALWAYS
,
424 8, 32, DEV_FLAGS_IN
| flags
);
425 auide
->rx_dev_id
= au1xxx_ddma_add_device( &source_dev_tab
);
427 /* Get a channel for TX */
428 auide
->tx_chan
= au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS
,
433 /* Get a channel for RX */
434 auide
->rx_chan
= au1xxx_dbdma_chan_alloc(auide
->rx_dev_id
,
439 auide
->tx_desc_head
= (void*)au1xxx_dbdma_ring_alloc(auide
->tx_chan
,
441 auide
->rx_desc_head
= (void*)au1xxx_dbdma_ring_alloc(auide
->rx_chan
,
444 au1xxx_dbdma_start( auide
->tx_chan
);
445 au1xxx_dbdma_start( auide
->rx_chan
);
451 static void auide_setup_ports(struct ide_hw
*hw
, _auide_hwif
*ahwif
)
454 unsigned long *ata_regs
= hw
->io_ports_array
;
457 for (i
= 0; i
< 8; i
++)
458 *ata_regs
++ = ahwif
->regbase
+ (i
<< IDE_REG_SHIFT
);
460 /* set the Alternative Status register */
461 *ata_regs
= ahwif
->regbase
+ (14 << IDE_REG_SHIFT
);
464 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
465 static const struct ide_tp_ops au1xxx_tp_ops
= {
466 .exec_command
= ide_exec_command
,
467 .read_status
= ide_read_status
,
468 .read_altstatus
= ide_read_altstatus
,
469 .write_devctl
= ide_write_devctl
,
471 .dev_select
= ide_dev_select
,
472 .tf_load
= ide_tf_load
,
473 .tf_read
= ide_tf_read
,
475 .input_data
= au1xxx_input_data
,
476 .output_data
= au1xxx_output_data
,
480 static const struct ide_port_ops au1xxx_port_ops
= {
481 .set_pio_mode
= au1xxx_set_pio_mode
,
482 .set_dma_mode
= auide_set_dma_mode
,
485 static const struct ide_port_info au1xxx_port_info
= {
486 .init_dma
= auide_ddma_init
,
487 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
488 .tp_ops
= &au1xxx_tp_ops
,
490 .port_ops
= &au1xxx_port_ops
,
491 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
492 .dma_ops
= &au1xxx_dma_ops
,
494 .host_flags
= IDE_HFLAG_POST_SET_MODE
|
495 IDE_HFLAG_NO_IO_32BIT
|
496 IDE_HFLAG_UNMASK_IRQS
,
497 .pio_mask
= ATA_PIO4
,
498 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
499 .mwdma_mask
= ATA_MWDMA2
,
501 .chipset
= ide_au1xxx
,
504 static int au_ide_probe(struct platform_device
*dev
)
506 _auide_hwif
*ahwif
= &auide_hwif
;
507 struct resource
*res
;
508 struct ide_host
*host
;
510 struct ide_hw hw
, *hws
[] = { &hw
};
512 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
513 char *mode
= "MWDMA2";
514 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
515 char *mode
= "PIO+DDMA(offload)";
518 memset(&auide_hwif
, 0, sizeof(_auide_hwif
));
519 ahwif
->irq
= platform_get_irq(dev
, 0);
521 res
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
524 pr_debug("%s %d: no base address\n", DRV_NAME
, dev
->id
);
528 if (ahwif
->irq
< 0) {
529 pr_debug("%s %d: no IRQ\n", DRV_NAME
, dev
->id
);
534 if (!request_mem_region(res
->start
, resource_size(res
), dev
->name
)) {
535 pr_debug("%s: request_mem_region failed\n", DRV_NAME
);
540 ahwif
->regbase
= (u32
)ioremap(res
->start
, resource_size(res
));
541 if (ahwif
->regbase
== 0) {
546 memset(&hw
, 0, sizeof(hw
));
547 auide_setup_ports(&hw
, ahwif
);
551 ret
= ide_host_add(&au1xxx_port_info
, hws
, 1, &host
);
555 auide_hwif
.hwif
= host
->ports
[0];
557 platform_set_drvdata(dev
, host
);
559 printk(KERN_INFO
"Au1xxx IDE(builtin) configured for %s\n", mode
);
565 static int au_ide_remove(struct platform_device
*dev
)
567 struct resource
*res
;
568 struct ide_host
*host
= platform_get_drvdata(dev
);
569 _auide_hwif
*ahwif
= &auide_hwif
;
571 ide_host_remove(host
);
573 iounmap((void *)ahwif
->regbase
);
575 res
= platform_get_resource(dev
, IORESOURCE_MEM
, 0);
576 release_mem_region(res
->start
, resource_size(res
));
581 static struct platform_driver au1200_ide_driver
= {
583 .name
= "au1200-ide",
584 .owner
= THIS_MODULE
,
586 .probe
= au_ide_probe
,
587 .remove
= au_ide_remove
,
590 static int __init
au_ide_init(void)
592 return platform_driver_register(&au1200_ide_driver
);
595 static void __exit
au_ide_exit(void)
597 platform_driver_unregister(&au1200_ide_driver
);
600 MODULE_LICENSE("GPL");
601 MODULE_DESCRIPTION("AU1200 IDE driver");
603 module_init(au_ide_init
);
604 module_exit(au_ide_exit
);