drivers/ide/mips/au1xxx-ide.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
   4  *
   5  * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
   6  *
   7  * This program is free software; you can redistribute it and/or modify it under
   8  * the terms of the GNU General Public License as published by the Free Software
   9  * Foundation; either version 2 of the License, or (at your option) any later
  10  * version.
  11  *
  12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
  13  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
  14  * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
  15  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  16  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  17  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  18  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  19  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  21  * POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  * You should have received a copy of the GNU General Public License along with
  24  * this program; if not, write to the Free Software Foundation, Inc.,
  25  * 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
  28  *       Interface and Linux Device Driver" Application Note.
  29  */
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/delay.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/init.h>
  36 #include <linux/ide.h>
  37 #include <linux/scatterlist.h>
  38
  39 #include <asm/mach-au1x00/au1xxx.h>
  40 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  41 #include <asm/mach-au1x00/au1xxx_ide.h>
  42
  43 #define DRV_NAME        "au1200-ide"
  44 #define DRV_AUTHOR      "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
  45
  46 /* enable the burstmode in the dbdma */
  47 #define IDE_AU1XXX_BURSTMODE    1
  48
  49 static _auide_hwif auide_hwif;
  50
  51 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
  52
  53 void auide_insw(unsigned long port, void *addr, u32 count)
  54 {
  55         _auide_hwif *ahwif = &auide_hwif;
  56         chan_tab_t *ctp;
  57         au1x_ddma_desc_t *dp;
  58
  59         if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
  60                            DDMA_FLAGS_NOIE)) {
  61                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
  62                 return;
  63         }
  64         ctp = *((chan_tab_t **)ahwif->rx_chan);
  65         dp = ctp->cur_ptr;
  66         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  67                 ;
  68         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  69 }
  70
  71 void auide_outsw(unsigned long port, void *addr, u32 count)
  72 {
  73         _auide_hwif *ahwif = &auide_hwif;
  74         chan_tab_t *ctp;
  75         au1x_ddma_desc_t *dp;
  76
  77         if(!put_source_flags(ahwif->tx_chan, (void*)addr,
  78                              count << 1, DDMA_FLAGS_NOIE)) {
  79                 printk(KERN_ERR "%s failed %d\n", __func__, __LINE__);
  80                 return;
  81         }
  82         ctp = *((chan_tab_t **)ahwif->tx_chan);
  83         dp = ctp->cur_ptr;
  84         while (dp->dscr_cmd0 & DSCR_CMD0_V)
  85                 ;
  86         ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
  87 }
  88
  89 static void au1xxx_input_data(ide_drive_t *drive, struct request *rq,
  90                               void *buf, unsigned int len)
  91 {
  92         auide_insw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
  93 }
  94
  95 static void au1xxx_output_data(ide_drive_t *drive, struct request *rq,
  96                                void *buf, unsigned int len)
  97 {
  98         auide_outsw(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
  99 }
 100 #endif
 101
 102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 103 {
 104         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 105
 106         /* set pio mode! */
 107         switch(pio) {
 108         case 0:
 109                 mem_sttime = SBC_IDE_TIMING(PIO0);
 110
 111                 /* set configuration for RCS2# */
 112                 mem_stcfg |= TS_MASK;
 113                 mem_stcfg &= ~TCSOE_MASK;
 114                 mem_stcfg &= ~TOECS_MASK;
 115                 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
 116                 break;
 117
 118         case 1:
 119                 mem_sttime = SBC_IDE_TIMING(PIO1);
 120
 121                 /* set configuration for RCS2# */
 122                 mem_stcfg |= TS_MASK;
 123                 mem_stcfg &= ~TCSOE_MASK;
 124                 mem_stcfg &= ~TOECS_MASK;
 125                 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
 126                 break;
 127
 128         case 2:
 129                 mem_sttime = SBC_IDE_TIMING(PIO2);
 130
 131                 /* set configuration for RCS2# */
 132                 mem_stcfg &= ~TS_MASK;
 133                 mem_stcfg &= ~TCSOE_MASK;
 134                 mem_stcfg &= ~TOECS_MASK;
 135                 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
 136                 break;
 137
 138         case 3:
 139                 mem_sttime = SBC_IDE_TIMING(PIO3);
 140
 141                 /* set configuration for RCS2# */
 142                 mem_stcfg &= ~TS_MASK;
 143                 mem_stcfg &= ~TCSOE_MASK;
 144                 mem_stcfg &= ~TOECS_MASK;
 145                 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
 146
 147                 break;
 148
 149         case 4:
 150                 mem_sttime = SBC_IDE_TIMING(PIO4);
 151
 152                 /* set configuration for RCS2# */
 153                 mem_stcfg &= ~TS_MASK;
 154                 mem_stcfg &= ~TCSOE_MASK;
 155                 mem_stcfg &= ~TOECS_MASK;
 156                 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
 157                 break;
 158         }
 159
 160         au_writel(mem_sttime,MEM_STTIME2);
 161         au_writel(mem_stcfg,MEM_STCFG2);
 162 }
 163
 164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
 165 {
 166         int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
 167
 168         switch(speed) {
 169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 170         case XFER_MW_DMA_2:
 171                 mem_sttime = SBC_IDE_TIMING(MDMA2);
 172
 173                 /* set configuration for RCS2# */
 174                 mem_stcfg &= ~TS_MASK;
 175                 mem_stcfg &= ~TCSOE_MASK;
 176                 mem_stcfg &= ~TOECS_MASK;
 177                 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
 178
 179                 break;
 180         case XFER_MW_DMA_1:
 181                 mem_sttime = SBC_IDE_TIMING(MDMA1);
 182
 183                 /* set configuration for RCS2# */
 184                 mem_stcfg &= ~TS_MASK;
 185                 mem_stcfg &= ~TCSOE_MASK;
 186                 mem_stcfg &= ~TOECS_MASK;
 187                 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
 188
 189                 break;
 190         case XFER_MW_DMA_0:
 191                 mem_sttime = SBC_IDE_TIMING(MDMA0);
 192
 193                 /* set configuration for RCS2# */
 194                 mem_stcfg |= TS_MASK;
 195                 mem_stcfg &= ~TCSOE_MASK;
 196                 mem_stcfg &= ~TOECS_MASK;
 197                 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
 198
 199                 break;
 200 #endif
 201         }
 202
 203         au_writel(mem_sttime,MEM_STTIME2);
 204         au_writel(mem_stcfg,MEM_STCFG2);
 205 }
 206
 207 /*
 208  * Multi-Word DMA + DbDMA functions
 209  */
 210
 211 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 212 static int auide_build_dmatable(ide_drive_t *drive)
 213 {
 214         int i, iswrite, count = 0;
 215         ide_hwif_t *hwif = HWIF(drive);
 216
 217         struct request *rq = HWGROUP(drive)->rq;
 218
 219         _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
 220         struct scatterlist *sg;
 221
 222         iswrite = (rq_data_dir(rq) == WRITE);
 223         /* Save for interrupt context */
 224         ahwif->drive = drive;
 225
 226         hwif->sg_nents = i = ide_build_sglist(drive, rq);
 227
 228         if (!i)
 229                 return 0;
 230
 231         /* fill the descriptors */
 232         sg = hwif->sg_table;
 233         while (i && sg_dma_len(sg)) {
 234                 u32 cur_addr;
 235                 u32 cur_len;
 236
 237                 cur_addr = sg_dma_address(sg);
 238                 cur_len = sg_dma_len(sg);
 239
 240                 while (cur_len) {
 241                         u32 flags = DDMA_FLAGS_NOIE;
 242                         unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
 243
 244                         if (++count >= PRD_ENTRIES) {
 245                                 printk(KERN_WARNING "%s: DMA table too small\n",
 246                                        drive->name);
 247                                 goto use_pio_instead;
 248                         }
 249
 250                         /* Lets enable intr for the last descriptor only */
 251                         if (1==i)
 252                                 flags = DDMA_FLAGS_IE;
 253                         else
 254                                 flags = DDMA_FLAGS_NOIE;
 255
 256                         if (iswrite) {
 257                                 if(!put_source_flags(ahwif->tx_chan,
 258                                                      (void*) sg_virt(sg),
 259                                                      tc, flags)) {
 260                                         printk(KERN_ERR "%s failed %d\n",
 261                                                __func__, __LINE__);
 262                                 }
 263                         } else
 264                         {
 265                                 if(!put_dest_flags(ahwif->rx_chan,
 266                                                    (void*) sg_virt(sg),
 267                                                    tc, flags)) {
 268                                         printk(KERN_ERR "%s failed %d\n",
 269                                                __func__, __LINE__);
 270                                 }
 271                         }
 272
 273                         cur_addr += tc;
 274                         cur_len -= tc;
 275                 }
 276                 sg = sg_next(sg);
 277                 i--;
 278         }
 279
 280         if (count)
 281                 return 1;
 282
 283  use_pio_instead:
 284         ide_destroy_dmatable(drive);
 285
 286         return 0; /* revert to PIO for this request */
 287 }
 288
 289 static int auide_dma_end(ide_drive_t *drive)
 290 {
 291         ide_hwif_t *hwif = HWIF(drive);
 292
 293         if (hwif->sg_nents) {
 294                 ide_destroy_dmatable(drive);
 295                 hwif->sg_nents = 0;
 296         }
 297
 298         return 0;
 299 }
 300
 301 static void auide_dma_start(ide_drive_t *drive )
 302 {
 303 }
 304
 305
 306 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
 307 {
 308         /* issue cmd to drive */
 309         ide_execute_command(drive, command, &ide_dma_intr,
 310                             (2*WAIT_CMD), NULL);
 311 }
 312
 313 static int auide_dma_setup(ide_drive_t *drive)
 314 {
 315         struct request *rq = HWGROUP(drive)->rq;
 316
 317         if (!auide_build_dmatable(drive)) {
 318                 ide_map_sg(drive, rq);
 319                 return 1;
 320         }
 321
 322         drive->waiting_for_dma = 1;
 323         return 0;
 324 }
 325
 326 static int auide_dma_test_irq(ide_drive_t *drive)
 327 {
 328         if (drive->waiting_for_dma == 0)
 329                 printk(KERN_WARNING "%s: ide_dma_test_irq \
 330                                      called while not waiting\n", drive->name);
 331
 332         /* If dbdma didn't execute the STOP command yet, the
 333          * active bit is still set
 334          */
 335         drive->waiting_for_dma++;
 336         if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
 337                 printk(KERN_WARNING "%s: timeout waiting for ddma to \
 338                                      complete\n", drive->name);
 339                 return 1;
 340         }
 341         udelay(10);
 342         return 0;
 343 }
 344
 345 static void auide_dma_host_set(ide_drive_t *drive, int on)
 346 {
 347 }
 348
 349 static void auide_dma_lost_irq(ide_drive_t *drive)
 350 {
 351         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 352 }
 353
 354 static void auide_ddma_tx_callback(int irq, void *param)
 355 {
 356         _auide_hwif *ahwif = (_auide_hwif*)param;
 357         ahwif->drive->waiting_for_dma = 0;
 358 }
 359
 360 static void auide_ddma_rx_callback(int irq, void *param)
 361 {
 362         _auide_hwif *ahwif = (_auide_hwif*)param;
 363         ahwif->drive->waiting_for_dma = 0;
 364 }
 365
 366 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
 367
 368 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
 369 {
 370         dev->dev_id          = dev_id;
 371         dev->dev_physaddr    = (u32)IDE_PHYS_ADDR;
 372         dev->dev_intlevel    = 0;
 373         dev->dev_intpolarity = 0;
 374         dev->dev_tsize       = tsize;
 375         dev->dev_devwidth    = devwidth;
 376         dev->dev_flags       = flags;
 377 }
 378
 379 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 380 static void auide_dma_timeout(ide_drive_t *drive)
 381 {
 382         ide_hwif_t *hwif = HWIF(drive);
 383
 384         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 385
 386         if (auide_dma_test_irq(drive))
 387                 return;
 388
 389         auide_dma_end(drive);
 390 }
 391
 392 static const struct ide_dma_ops au1xxx_dma_ops = {
 393         .dma_host_set           = auide_dma_host_set,
 394         .dma_setup              = auide_dma_setup,
 395         .dma_exec_cmd           = auide_dma_exec_cmd,
 396         .dma_start              = auide_dma_start,
 397         .dma_end                = auide_dma_end,
 398         .dma_test_irq           = auide_dma_test_irq,
 399         .dma_lost_irq           = auide_dma_lost_irq,
 400         .dma_timeout            = auide_dma_timeout,
 401 };
 402
 403 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 404 {
 405         _auide_hwif *auide = (_auide_hwif *)hwif->hwif_data;
 406         dbdev_tab_t source_dev_tab, target_dev_tab;
 407         u32 dev_id, tsize, devwidth, flags;
 408
 409         dev_id   = IDE_DDMA_REQ;
 410
 411         tsize    =  8; /*  1 */
 412         devwidth = 32; /* 16 */
 413
 414 #ifdef IDE_AU1XXX_BURSTMODE
 415         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 416 #else
 417         flags = DEV_FLAGS_SYNC;
 418 #endif
 419
 420         /* setup dev_tab for tx channel */
 421         auide_init_dbdma_dev( &source_dev_tab,
 422                               dev_id,
 423                               tsize, devwidth, DEV_FLAGS_OUT | flags);
 424         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 425
 426         auide_init_dbdma_dev( &source_dev_tab,
 427                               dev_id,
 428                               tsize, devwidth, DEV_FLAGS_IN | flags);
 429         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 430
 431         /* We also need to add a target device for the DMA */
 432         auide_init_dbdma_dev( &target_dev_tab,
 433                               (u32)DSCR_CMD0_ALWAYS,
 434                               tsize, devwidth, DEV_FLAGS_ANYUSE);
 435         auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
 436
 437         /* Get a channel for TX */
 438         auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
 439                                                  auide->tx_dev_id,
 440                                                  auide_ddma_tx_callback,
 441                                                  (void*)auide);
 442
 443         /* Get a channel for RX */
 444         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 445                                                  auide->target_dev_id,
 446                                                  auide_ddma_rx_callback,
 447                                                  (void*)auide);
 448
 449         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 450                                                              NUM_DESCRIPTORS);
 451         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 452                                                              NUM_DESCRIPTORS);
 453
 454         hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev,
 455                                                 PRD_ENTRIES * PRD_BYTES,        /* 1 Page */
 456                                                 &hwif->dmatable_dma, GFP_KERNEL);
 457
 458         au1xxx_dbdma_start( auide->tx_chan );
 459         au1xxx_dbdma_start( auide->rx_chan );
 460
 461         return 0;
 462 }
 463 #else
 464 static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
 465 {
 466         _auide_hwif *auide = (_auide_hwif *)hwif->hwif_data;
 467         dbdev_tab_t source_dev_tab;
 468         int flags;
 469
 470 #ifdef IDE_AU1XXX_BURSTMODE
 471         flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
 472 #else
 473         flags = DEV_FLAGS_SYNC;
 474 #endif
 475
 476         /* setup dev_tab for tx channel */
 477         auide_init_dbdma_dev( &source_dev_tab,
 478                               (u32)DSCR_CMD0_ALWAYS,
 479                               8, 32, DEV_FLAGS_OUT | flags);
 480         auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 481
 482         auide_init_dbdma_dev( &source_dev_tab,
 483                               (u32)DSCR_CMD0_ALWAYS,
 484                               8, 32, DEV_FLAGS_IN | flags);
 485         auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
 486
 487         /* Get a channel for TX */
 488         auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
 489                                                  auide->tx_dev_id,
 490                                                  NULL,
 491                                                  (void*)auide);
 492
 493         /* Get a channel for RX */
 494         auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
 495                                                  DSCR_CMD0_ALWAYS,
 496                                                  NULL,
 497                                                  (void*)auide);
 498
 499         auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
 500                                                              NUM_DESCRIPTORS);
 501         auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
 502                                                              NUM_DESCRIPTORS);
 503
 504         au1xxx_dbdma_start( auide->tx_chan );
 505         au1xxx_dbdma_start( auide->rx_chan );
 506
 507         return 0;
 508 }
 509 #endif
 510
 511 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
 512 {
 513         int i;
 514         unsigned long *ata_regs = hw->io_ports_array;
 515
 516         /* FIXME? */
 517         for (i = 0; i < 8; i++)
 518                 *ata_regs++ = ahwif->regbase + (i << IDE_REG_SHIFT);
 519
 520         /* set the Alternative Status register */
 521         *ata_regs = ahwif->regbase + (14 << IDE_REG_SHIFT);
 522 }
 523
 524 static const struct ide_port_ops au1xxx_port_ops = {
 525         .set_pio_mode           = au1xxx_set_pio_mode,
 526         .set_dma_mode           = auide_set_dma_mode,
 527 };
 528
 529 static const struct ide_port_info au1xxx_port_info = {
 530         .init_dma               = auide_ddma_init,
 531         .port_ops               = &au1xxx_port_ops,
 532 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 533         .dma_ops                = &au1xxx_dma_ops,
 534 #endif
 535         .host_flags             = IDE_HFLAG_POST_SET_MODE |
 536                                   IDE_HFLAG_NO_IO_32BIT |
 537                                   IDE_HFLAG_UNMASK_IRQS,
 538         .pio_mask               = ATA_PIO4,
 539 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 540         .mwdma_mask             = ATA_MWDMA2,
 541 #endif
 542 };
 543
 544 static int au_ide_probe(struct device *dev)
 545 {
 546         struct platform_device *pdev = to_platform_device(dev);
 547         _auide_hwif *ahwif = &auide_hwif;
 548         ide_hwif_t *hwif;
 549         struct resource *res;
 550         int ret = 0;
 551         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 552         hw_regs_t hw;
 553
 554 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
 555         char *mode = "MWDMA2";
 556 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
 557         char *mode = "PIO+DDMA(offload)";
 558 #endif
 559
 560         memset(&auide_hwif, 0, sizeof(_auide_hwif));
 561         ahwif->irq = platform_get_irq(pdev, 0);
 562
 563         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 564
 565         if (res == NULL) {
 566                 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
 567                 ret = -ENODEV;
 568                 goto out;
 569         }
 570         if (ahwif->irq < 0) {
 571                 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
 572                 ret = -ENODEV;
 573                 goto out;
 574         }
 575
 576         if (!request_mem_region(res->start, res->end - res->start + 1,
 577                                 pdev->name)) {
 578                 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
 579                 ret =  -EBUSY;
 580                 goto out;
 581         }
 582
 583         ahwif->regbase = (u32)ioremap(res->start, res->end - res->start + 1);
 584         if (ahwif->regbase == 0) {
 585                 ret = -ENOMEM;
 586                 goto out;
 587         }
 588
 589         hwif = ide_find_port();
 590         if (hwif == NULL) {
 591                 ret = -ENOENT;
 592                 goto out;
 593         }
 594
 595         memset(&hw, 0, sizeof(hw));
 596         auide_setup_ports(&hw, ahwif);
 597         hw.irq = ahwif->irq;
 598         hw.dev = dev;
 599         hw.chipset = ide_au1xxx;
 600
 601         ide_init_port_hw(hwif, &hw);
 602
 603         hwif->dev = dev;
 604
 605         /* If the user has selected DDMA assisted copies,
 606            then set up a few local I/O function entry points
 607         */
 608
 609 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
 610         hwif->input_data  = au1xxx_input_data;
 611         hwif->output_data = au1xxx_output_data;
 612 #endif
 613         hwif->select_data               = 0;    /* no chipset-specific code */
 614         hwif->config_data               = 0;    /* no chipset-specific code */
 615
 616         auide_hwif.hwif                 = hwif;
 617         hwif->hwif_data                 = &auide_hwif;
 618
 619         idx[0] = hwif->index;
 620
 621         ide_device_add(idx, &au1xxx_port_info);
 622
 623         dev_set_drvdata(dev, hwif);
 624
 625         printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
 626
 627  out:
 628         return ret;
 629 }
 630
 631 static int au_ide_remove(struct device *dev)
 632 {
 633         struct platform_device *pdev = to_platform_device(dev);
 634         struct resource *res;
 635         ide_hwif_t *hwif = dev_get_drvdata(dev);
 636         _auide_hwif *ahwif = &auide_hwif;
 637
 638         ide_unregister(hwif);
 639
 640         iounmap((void *)ahwif->regbase);
 641
 642         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 643         release_mem_region(res->start, res->end - res->start + 1);
 644
 645         return 0;
 646 }
 647
 648 static struct device_driver au1200_ide_driver = {
 649         .name           = "au1200-ide",
 650         .bus            = &platform_bus_type,
 651         .probe          = au_ide_probe,
 652         .remove         = au_ide_remove,
 653 };
 654
 655 static int __init au_ide_init(void)
 656 {
 657         return driver_register(&au1200_ide_driver);
 658 }
 659
 660 static void __exit au_ide_exit(void)
 661 {
 662         driver_unregister(&au1200_ide_driver);
 663 }
 664
 665 MODULE_LICENSE("GPL");
 666 MODULE_DESCRIPTION("AU1200 IDE driver");
 667
 668 module_init(au_ide_init);
 669 module_exit(au_ide_exit);