ide: add struct ide_host (take 3)
[deliverable/linux.git] / drivers / ide / pci / cmd640.c
1 /*
2 * Copyright (C) 1995-1996 Linus Torvalds & authors (see below)
3 */
4
5 /*
6 * Original authors: abramov@cecmow.enet.dec.com (Igor Abramov)
7 * mlord@pobox.com (Mark Lord)
8 *
9 * See linux/MAINTAINERS for address of current maintainer.
10 *
11 * This file provides support for the advanced features and bugs
12 * of IDE interfaces using the CMD Technologies 0640 IDE interface chip.
13 *
14 * These chips are basically fucked by design, and getting this driver
15 * to work on every motherboard design that uses this screwed chip seems
16 * bloody well impossible. However, we're still trying.
17 *
18 * Version 0.97 worked for everybody.
19 *
20 * User feedback is essential. Many thanks to the beta test team:
21 *
22 * A.Hartgers@stud.tue.nl, JZDQC@CUNYVM.CUNY.edu, abramov@cecmow.enet.dec.com,
23 * bardj@utopia.ppp.sn.no, bart@gaga.tue.nl, bbol001@cs.auckland.ac.nz,
24 * chrisc@dbass.demon.co.uk, dalecki@namu26.Num.Math.Uni-Goettingen.de,
25 * derekn@vw.ece.cmu.edu, florian@btp2x3.phy.uni-bayreuth.de,
26 * flynn@dei.unipd.it, gadio@netvision.net.il, godzilla@futuris.net,
27 * j@pobox.com, jkemp1@mises.uni-paderborn.de, jtoppe@hiwaay.net,
28 * kerouac@ssnet.com, meskes@informatik.rwth-aachen.de, hzoli@cs.elte.hu,
29 * peter@udgaard.isgtec.com, phil@tazenda.demon.co.uk, roadcapw@cfw.com,
30 * s0033las@sun10.vsz.bme.hu, schaffer@tam.cornell.edu, sjd@slip.net,
31 * steve@ei.org, ulrpeg@bigcomm.gun.de, ism@tardis.ed.ac.uk, mack@cray.com
32 * liug@mama.indstate.edu, and others.
33 *
34 * Version 0.01 Initial version, hacked out of ide.c,
35 * and #include'd rather than compiled separately.
36 * This will get cleaned up in a subsequent release.
37 *
38 * Version 0.02 Fixes for vlb initialization code, enable prefetch
39 * for versions 'B' and 'C' of chip by default,
40 * some code cleanup.
41 *
42 * Version 0.03 Added reset of secondary interface,
43 * and black list for devices which are not compatible
44 * with prefetch mode. Separate function for setting
45 * prefetch is added, possibly it will be called some
46 * day from ioctl processing code.
47 *
48 * Version 0.04 Now configs/compiles separate from ide.c
49 *
50 * Version 0.05 Major rewrite of interface timing code.
51 * Added new function cmd640_set_mode to set PIO mode
52 * from ioctl call. New drives added to black list.
53 *
54 * Version 0.06 More code cleanup. Prefetch is enabled only for
55 * detected hard drives, not included in prefetch
56 * black list.
57 *
58 * Version 0.07 Changed to more conservative drive tuning policy.
59 * Unknown drives, which report PIO < 4 are set to
60 * (reported_PIO - 1) if it is supported, or to PIO0.
61 * List of known drives extended by info provided by
62 * CMD at their ftp site.
63 *
64 * Version 0.08 Added autotune/noautotune support.
65 *
66 * Version 0.09 Try to be smarter about 2nd port enabling.
67 * Version 0.10 Be nice and don't reset 2nd port.
68 * Version 0.11 Try to handle more weird situations.
69 *
70 * Version 0.12 Lots of bug fixes from Laszlo Peter
71 * irq unmasking disabled for reliability.
72 * try to be even smarter about the second port.
73 * tidy up source code formatting.
74 * Version 0.13 permit irq unmasking again.
75 * Version 0.90 massive code cleanup, some bugs fixed.
76 * defaults all drives to PIO mode0, prefetch off.
77 * autotune is OFF by default, with compile time flag.
78 * prefetch can be turned OFF/ON using "hdparm -p8/-p9"
79 * (requires hdparm-3.1 or newer)
80 * Version 0.91 first release to linux-kernel list.
81 * Version 0.92 move initial reg dump to separate callable function
82 * change "readahead" to "prefetch" to avoid confusion
83 * Version 0.95 respect original BIOS timings unless autotuning.
84 * tons of code cleanup and rearrangement.
85 * added CONFIG_BLK_DEV_CMD640_ENHANCED option
86 * prevent use of unmask when prefetch is on
87 * Version 0.96 prevent use of io_32bit when prefetch is off
88 * Version 0.97 fix VLB secondary interface for sjd@slip.net
89 * other minor tune-ups: 0.96 was very good.
90 * Version 0.98 ignore PCI version when disabled by BIOS
91 * Version 0.99 display setup/active/recovery clocks with PIO mode
92 * Version 1.00 Mmm.. cannot depend on PCMD_ENA in all systems
93 * Version 1.01 slow/fast devsel can be selected with "hdparm -p6/-p7"
94 * ("fast" is necessary for 32bit I/O in some systems)
95 * Version 1.02 fix bug that resulted in slow "setup times"
96 * (patch courtesy of Zoltan Hidvegi)
97 */
98
99 #define CMD640_PREFETCH_MASKS 1
100
101 /*#define CMD640_DUMP_REGS */
102
103 #include <linux/types.h>
104 #include <linux/kernel.h>
105 #include <linux/delay.h>
106 #include <linux/hdreg.h>
107 #include <linux/ide.h>
108 #include <linux/init.h>
109
110 #include <asm/io.h>
111
112 #define DRV_NAME "cmd640"
113
114 static int cmd640_vlb;
115
116 /*
117 * CMD640 specific registers definition.
118 */
119
120 #define VID 0x00
121 #define DID 0x02
122 #define PCMD 0x04
123 #define PCMD_ENA 0x01
124 #define PSTTS 0x06
125 #define REVID 0x08
126 #define PROGIF 0x09
127 #define SUBCL 0x0a
128 #define BASCL 0x0b
129 #define BaseA0 0x10
130 #define BaseA1 0x14
131 #define BaseA2 0x18
132 #define BaseA3 0x1c
133 #define INTLINE 0x3c
134 #define INPINE 0x3d
135
136 #define CFR 0x50
137 #define CFR_DEVREV 0x03
138 #define CFR_IDE01INTR 0x04
139 #define CFR_DEVID 0x18
140 #define CFR_AT_VESA_078h 0x20
141 #define CFR_DSA1 0x40
142 #define CFR_DSA0 0x80
143
144 #define CNTRL 0x51
145 #define CNTRL_DIS_RA0 0x40
146 #define CNTRL_DIS_RA1 0x80
147 #define CNTRL_ENA_2ND 0x08
148
149 #define CMDTIM 0x52
150 #define ARTTIM0 0x53
151 #define DRWTIM0 0x54
152 #define ARTTIM1 0x55
153 #define DRWTIM1 0x56
154 #define ARTTIM23 0x57
155 #define ARTTIM23_DIS_RA2 0x04
156 #define ARTTIM23_DIS_RA3 0x08
157 #define DRWTIM23 0x58
158 #define BRST 0x59
159
160 /*
161 * Registers and masks for easy access by drive index:
162 */
163 static u8 prefetch_regs[4] = {CNTRL, CNTRL, ARTTIM23, ARTTIM23};
164 static u8 prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3};
165
166 #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
167
168 static u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
169 static u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM23, DRWTIM23};
170
171 /*
172 * Current cmd640 timing values for each drive.
173 * The defaults for each are the slowest possible timings.
174 */
175 static u8 setup_counts[4] = {4, 4, 4, 4}; /* Address setup count (in clocks) */
176 static u8 active_counts[4] = {16, 16, 16, 16}; /* Active count (encoded) */
177 static u8 recovery_counts[4] = {16, 16, 16, 16}; /* Recovery count (encoded) */
178
179 #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
180
181 static DEFINE_SPINLOCK(cmd640_lock);
182
183 /*
184 * Interface to access cmd640x registers
185 */
186 static unsigned int cmd640_key;
187 static void (*__put_cmd640_reg)(u16 reg, u8 val);
188 static u8 (*__get_cmd640_reg)(u16 reg);
189
190 /*
191 * This is read from the CFR reg, and is used in several places.
192 */
193 static unsigned int cmd640_chip_version;
194
195 /*
196 * The CMD640x chip does not support DWORD config write cycles, but some
197 * of the BIOSes use them to implement the config services.
198 * Therefore, we must use direct IO instead.
199 */
200
201 /* PCI method 1 access */
202
203 static void put_cmd640_reg_pci1(u16 reg, u8 val)
204 {
205 outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
206 outb_p(val, (reg & 3) | 0xcfc);
207 }
208
209 static u8 get_cmd640_reg_pci1(u16 reg)
210 {
211 outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
212 return inb_p((reg & 3) | 0xcfc);
213 }
214
215 /* PCI method 2 access (from CMD datasheet) */
216
217 static void put_cmd640_reg_pci2(u16 reg, u8 val)
218 {
219 outb_p(0x10, 0xcf8);
220 outb_p(val, cmd640_key + reg);
221 outb_p(0, 0xcf8);
222 }
223
224 static u8 get_cmd640_reg_pci2(u16 reg)
225 {
226 u8 b;
227
228 outb_p(0x10, 0xcf8);
229 b = inb_p(cmd640_key + reg);
230 outb_p(0, 0xcf8);
231 return b;
232 }
233
234 /* VLB access */
235
236 static void put_cmd640_reg_vlb(u16 reg, u8 val)
237 {
238 outb_p(reg, cmd640_key);
239 outb_p(val, cmd640_key + 4);
240 }
241
242 static u8 get_cmd640_reg_vlb(u16 reg)
243 {
244 outb_p(reg, cmd640_key);
245 return inb_p(cmd640_key + 4);
246 }
247
248 static u8 get_cmd640_reg(u16 reg)
249 {
250 unsigned long flags;
251 u8 b;
252
253 spin_lock_irqsave(&cmd640_lock, flags);
254 b = __get_cmd640_reg(reg);
255 spin_unlock_irqrestore(&cmd640_lock, flags);
256 return b;
257 }
258
259 static void put_cmd640_reg(u16 reg, u8 val)
260 {
261 unsigned long flags;
262
263 spin_lock_irqsave(&cmd640_lock, flags);
264 __put_cmd640_reg(reg, val);
265 spin_unlock_irqrestore(&cmd640_lock, flags);
266 }
267
268 static int __init match_pci_cmd640_device(void)
269 {
270 const u8 ven_dev[4] = {0x95, 0x10, 0x40, 0x06};
271 unsigned int i;
272 for (i = 0; i < 4; i++) {
273 if (get_cmd640_reg(i) != ven_dev[i])
274 return 0;
275 }
276 #ifdef STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT
277 if ((get_cmd640_reg(PCMD) & PCMD_ENA) == 0) {
278 printk("ide: cmd640 on PCI disabled by BIOS\n");
279 return 0;
280 }
281 #endif /* STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT */
282 return 1; /* success */
283 }
284
285 /*
286 * Probe for CMD640x -- pci method 1
287 */
288 static int __init probe_for_cmd640_pci1(void)
289 {
290 __get_cmd640_reg = get_cmd640_reg_pci1;
291 __put_cmd640_reg = put_cmd640_reg_pci1;
292 for (cmd640_key = 0x80000000;
293 cmd640_key <= 0x8000f800;
294 cmd640_key += 0x800) {
295 if (match_pci_cmd640_device())
296 return 1; /* success */
297 }
298 return 0;
299 }
300
301 /*
302 * Probe for CMD640x -- pci method 2
303 */
304 static int __init probe_for_cmd640_pci2(void)
305 {
306 __get_cmd640_reg = get_cmd640_reg_pci2;
307 __put_cmd640_reg = put_cmd640_reg_pci2;
308 for (cmd640_key = 0xc000; cmd640_key <= 0xcf00; cmd640_key += 0x100) {
309 if (match_pci_cmd640_device())
310 return 1; /* success */
311 }
312 return 0;
313 }
314
315 /*
316 * Probe for CMD640x -- vlb
317 */
318 static int __init probe_for_cmd640_vlb(void)
319 {
320 u8 b;
321
322 __get_cmd640_reg = get_cmd640_reg_vlb;
323 __put_cmd640_reg = put_cmd640_reg_vlb;
324 cmd640_key = 0x178;
325 b = get_cmd640_reg(CFR);
326 if (b == 0xff || b == 0x00 || (b & CFR_AT_VESA_078h)) {
327 cmd640_key = 0x78;
328 b = get_cmd640_reg(CFR);
329 if (b == 0xff || b == 0x00 || !(b & CFR_AT_VESA_078h))
330 return 0;
331 }
332 return 1; /* success */
333 }
334
335 /*
336 * Returns 1 if an IDE interface/drive exists at 0x170,
337 * Returns 0 otherwise.
338 */
339 static int __init secondary_port_responding(void)
340 {
341 unsigned long flags;
342
343 spin_lock_irqsave(&cmd640_lock, flags);
344
345 outb_p(0x0a, 0x176); /* select drive0 */
346 udelay(100);
347 if ((inb_p(0x176) & 0x1f) != 0x0a) {
348 outb_p(0x1a, 0x176); /* select drive1 */
349 udelay(100);
350 if ((inb_p(0x176) & 0x1f) != 0x1a) {
351 spin_unlock_irqrestore(&cmd640_lock, flags);
352 return 0; /* nothing responded */
353 }
354 }
355 spin_unlock_irqrestore(&cmd640_lock, flags);
356 return 1; /* success */
357 }
358
359 #ifdef CMD640_DUMP_REGS
360 /*
361 * Dump out all cmd640 registers. May be called from ide.c
362 */
363 static void cmd640_dump_regs(void)
364 {
365 unsigned int reg = cmd640_vlb ? 0x50 : 0x00;
366
367 /* Dump current state of chip registers */
368 printk("ide: cmd640 internal register dump:");
369 for (; reg <= 0x59; reg++) {
370 if (!(reg & 0x0f))
371 printk("\n%04x:", reg);
372 printk(" %02x", get_cmd640_reg(reg));
373 }
374 printk("\n");
375 }
376 #endif
377
378 #ifndef CONFIG_BLK_DEV_CMD640_ENHANCED
379 /*
380 * Check whether prefetch is on for a drive,
381 * and initialize the unmask flags for safe operation.
382 */
383 static void __init check_prefetch(ide_drive_t *drive, unsigned int index)
384 {
385 u8 b = get_cmd640_reg(prefetch_regs[index]);
386
387 if (b & prefetch_masks[index]) { /* is prefetch off? */
388 drive->no_unmask = 0;
389 drive->no_io_32bit = 1;
390 drive->io_32bit = 0;
391 } else {
392 #if CMD640_PREFETCH_MASKS
393 drive->no_unmask = 1;
394 drive->unmask = 0;
395 #endif
396 drive->no_io_32bit = 0;
397 }
398 }
399 #else
400 /*
401 * Sets prefetch mode for a drive.
402 */
403 static void set_prefetch_mode(ide_drive_t *drive, unsigned int index, int mode)
404 {
405 unsigned long flags;
406 int reg = prefetch_regs[index];
407 u8 b;
408
409 spin_lock_irqsave(&cmd640_lock, flags);
410 b = __get_cmd640_reg(reg);
411 if (mode) { /* want prefetch on? */
412 #if CMD640_PREFETCH_MASKS
413 drive->no_unmask = 1;
414 drive->unmask = 0;
415 #endif
416 drive->no_io_32bit = 0;
417 b &= ~prefetch_masks[index]; /* enable prefetch */
418 } else {
419 drive->no_unmask = 0;
420 drive->no_io_32bit = 1;
421 drive->io_32bit = 0;
422 b |= prefetch_masks[index]; /* disable prefetch */
423 }
424 __put_cmd640_reg(reg, b);
425 spin_unlock_irqrestore(&cmd640_lock, flags);
426 }
427
428 /*
429 * Dump out current drive clocks settings
430 */
431 static void display_clocks(unsigned int index)
432 {
433 u8 active_count, recovery_count;
434
435 active_count = active_counts[index];
436 if (active_count == 1)
437 ++active_count;
438 recovery_count = recovery_counts[index];
439 if (active_count > 3 && recovery_count == 1)
440 ++recovery_count;
441 if (cmd640_chip_version > 1)
442 recovery_count += 1; /* cmd640b uses (count + 1)*/
443 printk(", clocks=%d/%d/%d\n", setup_counts[index], active_count, recovery_count);
444 }
445
446 /*
447 * Pack active and recovery counts into single byte representation
448 * used by controller
449 */
450 static inline u8 pack_nibbles(u8 upper, u8 lower)
451 {
452 return ((upper & 0x0f) << 4) | (lower & 0x0f);
453 }
454
455 /*
456 * This routine writes the prepared setup/active/recovery counts
457 * for a drive into the cmd640 chipset registers to active them.
458 */
459 static void program_drive_counts(ide_drive_t *drive, unsigned int index)
460 {
461 unsigned long flags;
462 u8 setup_count = setup_counts[index];
463 u8 active_count = active_counts[index];
464 u8 recovery_count = recovery_counts[index];
465
466 /*
467 * Set up address setup count and drive read/write timing registers.
468 * Primary interface has individual count/timing registers for
469 * each drive. Secondary interface has one common set of registers,
470 * so we merge the timings, using the slowest value for each timing.
471 */
472 if (index > 1) {
473 ide_hwif_t *hwif = drive->hwif;
474 ide_drive_t *peer = &hwif->drives[!drive->select.b.unit];
475 unsigned int mate = index ^ 1;
476
477 if (peer->present) {
478 if (setup_count < setup_counts[mate])
479 setup_count = setup_counts[mate];
480 if (active_count < active_counts[mate])
481 active_count = active_counts[mate];
482 if (recovery_count < recovery_counts[mate])
483 recovery_count = recovery_counts[mate];
484 }
485 }
486
487 /*
488 * Convert setup_count to internal chipset representation
489 */
490 switch (setup_count) {
491 case 4: setup_count = 0x00; break;
492 case 3: setup_count = 0x80; break;
493 case 1:
494 case 2: setup_count = 0x40; break;
495 default: setup_count = 0xc0; /* case 5 */
496 }
497
498 /*
499 * Now that everything is ready, program the new timings
500 */
501 spin_lock_irqsave(&cmd640_lock, flags);
502 /*
503 * Program the address_setup clocks into ARTTIM reg,
504 * and then the active/recovery counts into the DRWTIM reg
505 * (this converts counts of 16 into counts of zero -- okay).
506 */
507 setup_count |= __get_cmd640_reg(arttim_regs[index]) & 0x3f;
508 __put_cmd640_reg(arttim_regs[index], setup_count);
509 __put_cmd640_reg(drwtim_regs[index], pack_nibbles(active_count, recovery_count));
510 spin_unlock_irqrestore(&cmd640_lock, flags);
511 }
512
513 /*
514 * Set a specific pio_mode for a drive
515 */
516 static void cmd640_set_mode(ide_drive_t *drive, unsigned int index,
517 u8 pio_mode, unsigned int cycle_time)
518 {
519 struct ide_timing *t;
520 int setup_time, active_time, recovery_time, clock_time;
521 u8 setup_count, active_count, recovery_count, recovery_count2, cycle_count;
522 int bus_speed;
523
524 if (cmd640_vlb)
525 bus_speed = ide_vlb_clk ? ide_vlb_clk : 50;
526 else
527 bus_speed = ide_pci_clk ? ide_pci_clk : 33;
528
529 if (pio_mode > 5)
530 pio_mode = 5;
531
532 t = ide_timing_find_mode(XFER_PIO_0 + pio_mode);
533 setup_time = t->setup;
534 active_time = t->active;
535
536 recovery_time = cycle_time - (setup_time + active_time);
537 clock_time = 1000 / bus_speed;
538 cycle_count = DIV_ROUND_UP(cycle_time, clock_time);
539
540 setup_count = DIV_ROUND_UP(setup_time, clock_time);
541
542 active_count = DIV_ROUND_UP(active_time, clock_time);
543 if (active_count < 2)
544 active_count = 2; /* minimum allowed by cmd640 */
545
546 recovery_count = DIV_ROUND_UP(recovery_time, clock_time);
547 recovery_count2 = cycle_count - (setup_count + active_count);
548 if (recovery_count2 > recovery_count)
549 recovery_count = recovery_count2;
550 if (recovery_count < 2)
551 recovery_count = 2; /* minimum allowed by cmd640 */
552 if (recovery_count > 17) {
553 active_count += recovery_count - 17;
554 recovery_count = 17;
555 }
556 if (active_count > 16)
557 active_count = 16; /* maximum allowed by cmd640 */
558 if (cmd640_chip_version > 1)
559 recovery_count -= 1; /* cmd640b uses (count + 1)*/
560 if (recovery_count > 16)
561 recovery_count = 16; /* maximum allowed by cmd640 */
562
563 setup_counts[index] = setup_count;
564 active_counts[index] = active_count;
565 recovery_counts[index] = recovery_count;
566
567 /*
568 * In a perfect world, we might set the drive pio mode here
569 * (using WIN_SETFEATURE) before continuing.
570 *
571 * But we do not, because:
572 * 1) this is the wrong place to do it (proper is do_special() in ide.c)
573 * 2) in practice this is rarely, if ever, necessary
574 */
575 program_drive_counts(drive, index);
576 }
577
578 static void cmd640_set_pio_mode(ide_drive_t *drive, const u8 pio)
579 {
580 unsigned int index = 0, cycle_time;
581 u8 b;
582
583 switch (pio) {
584 case 6: /* set fast-devsel off */
585 case 7: /* set fast-devsel on */
586 b = get_cmd640_reg(CNTRL) & ~0x27;
587 if (pio & 1)
588 b |= 0x27;
589 put_cmd640_reg(CNTRL, b);
590 printk("%s: %sabled cmd640 fast host timing (devsel)\n",
591 drive->name, (pio & 1) ? "en" : "dis");
592 return;
593 case 8: /* set prefetch off */
594 case 9: /* set prefetch on */
595 set_prefetch_mode(drive, index, pio & 1);
596 printk("%s: %sabled cmd640 prefetch\n",
597 drive->name, (pio & 1) ? "en" : "dis");
598 return;
599 }
600
601 cycle_time = ide_pio_cycle_time(drive, pio);
602 cmd640_set_mode(drive, index, pio, cycle_time);
603
604 printk("%s: selected cmd640 PIO mode%d (%dns)",
605 drive->name, pio, cycle_time);
606
607 display_clocks(index);
608 }
609 #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
610
611 static void cmd640_init_dev(ide_drive_t *drive)
612 {
613 unsigned int i = drive->hwif->channel * 2 + drive->select.b.unit;
614
615 #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
616 /*
617 * Reset timing to the slowest speed and turn off prefetch.
618 * This way, the drive identify code has a better chance.
619 */
620 setup_counts[i] = 4; /* max possible */
621 active_counts[i] = 16; /* max possible */
622 recovery_counts[i] = 16; /* max possible */
623 program_drive_counts(drive, i);
624 set_prefetch_mode(drive, i, 0);
625 printk(KERN_INFO DRV_NAME ": drive%d timings/prefetch cleared\n", i);
626 #else
627 /*
628 * Set the drive unmask flags to match the prefetch setting.
629 */
630 check_prefetch(drive, i);
631 printk(KERN_INFO DRV_NAME ": drive%d timings/prefetch(%s) preserved\n",
632 i, drive->no_io_32bit ? "off" : "on");
633 #endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
634 }
635
636
637 static const struct ide_port_ops cmd640_port_ops = {
638 .init_dev = cmd640_init_dev,
639 #ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
640 .set_pio_mode = cmd640_set_pio_mode,
641 #endif
642 };
643
644 static int pci_conf1(void)
645 {
646 unsigned long flags;
647 u32 tmp;
648
649 spin_lock_irqsave(&cmd640_lock, flags);
650 outb(0x01, 0xCFB);
651 tmp = inl(0xCF8);
652 outl(0x80000000, 0xCF8);
653 if (inl(0xCF8) == 0x80000000) {
654 outl(tmp, 0xCF8);
655 spin_unlock_irqrestore(&cmd640_lock, flags);
656 return 1;
657 }
658 outl(tmp, 0xCF8);
659 spin_unlock_irqrestore(&cmd640_lock, flags);
660 return 0;
661 }
662
663 static int pci_conf2(void)
664 {
665 unsigned long flags;
666
667 spin_lock_irqsave(&cmd640_lock, flags);
668 outb(0x00, 0xCFB);
669 outb(0x00, 0xCF8);
670 outb(0x00, 0xCFA);
671 if (inb(0xCF8) == 0x00 && inb(0xCF8) == 0x00) {
672 spin_unlock_irqrestore(&cmd640_lock, flags);
673 return 1;
674 }
675 spin_unlock_irqrestore(&cmd640_lock, flags);
676 return 0;
677 }
678
679 static const struct ide_port_info cmd640_port_info __initdata = {
680 .chipset = ide_cmd640,
681 .host_flags = IDE_HFLAG_SERIALIZE |
682 IDE_HFLAG_NO_DMA |
683 IDE_HFLAG_ABUSE_PREFETCH |
684 IDE_HFLAG_ABUSE_FAST_DEVSEL,
685 .port_ops = &cmd640_port_ops,
686 .pio_mask = ATA_PIO5,
687 };
688
689 static int cmd640x_init_one(unsigned long base, unsigned long ctl)
690 {
691 if (!request_region(base, 8, DRV_NAME)) {
692 printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX not free.\n",
693 DRV_NAME, base, base + 7);
694 return -EBUSY;
695 }
696
697 if (!request_region(ctl, 1, DRV_NAME)) {
698 printk(KERN_ERR "%s: I/O resource 0x%lX not free.\n",
699 DRV_NAME, ctl);
700 release_region(base, 8);
701 return -EBUSY;
702 }
703
704 return 0;
705 }
706
707 /*
708 * Probe for a cmd640 chipset, and initialize it if found.
709 */
710 static int __init cmd640x_init(void)
711 {
712 struct ide_host *host;
713 int second_port_cmd640 = 0, rc;
714 const char *bus_type, *port2;
715 u8 b, cfr;
716 hw_regs_t hw[2], *hws[] = { NULL, NULL, NULL, NULL };
717
718 if (cmd640_vlb && probe_for_cmd640_vlb()) {
719 bus_type = "VLB";
720 } else {
721 cmd640_vlb = 0;
722 /* Find out what kind of PCI probing is supported otherwise
723 Justin Gibbs will sulk.. */
724 if (pci_conf1() && probe_for_cmd640_pci1())
725 bus_type = "PCI (type1)";
726 else if (pci_conf2() && probe_for_cmd640_pci2())
727 bus_type = "PCI (type2)";
728 else
729 return 0;
730 }
731 /*
732 * Undocumented magic (there is no 0x5b reg in specs)
733 */
734 put_cmd640_reg(0x5b, 0xbd);
735 if (get_cmd640_reg(0x5b) != 0xbd) {
736 printk(KERN_ERR "ide: cmd640 init failed: wrong value in reg 0x5b\n");
737 return 0;
738 }
739 put_cmd640_reg(0x5b, 0);
740
741 #ifdef CMD640_DUMP_REGS
742 cmd640_dump_regs();
743 #endif
744
745 /*
746 * Documented magic begins here
747 */
748 cfr = get_cmd640_reg(CFR);
749 cmd640_chip_version = cfr & CFR_DEVREV;
750 if (cmd640_chip_version == 0) {
751 printk("ide: bad cmd640 revision: %d\n", cmd640_chip_version);
752 return 0;
753 }
754
755 rc = cmd640x_init_one(0x1f0, 0x3f6);
756 if (rc)
757 return rc;
758
759 rc = cmd640x_init_one(0x170, 0x376);
760 if (rc) {
761 release_region(0x3f6, 1);
762 release_region(0x1f0, 8);
763 return rc;
764 }
765
766 memset(&hw, 0, sizeof(hw));
767
768 ide_std_init_ports(&hw[0], 0x1f0, 0x3f6);
769 hw[0].irq = 14;
770 hw[0].chipset = ide_cmd640;
771
772 ide_std_init_ports(&hw[1], 0x170, 0x376);
773 hw[1].irq = 15;
774 hw[1].chipset = ide_cmd640;
775
776 printk(KERN_INFO "cmd640: buggy cmd640%c interface on %s, config=0x%02x"
777 "\n", 'a' + cmd640_chip_version - 1, bus_type, cfr);
778
779 /*
780 * Initialize data for primary port
781 */
782 hws[0] = &hw[0];
783
784 /*
785 * Ensure compatibility by always using the slowest timings
786 * for access to the drive's command register block,
787 * and reset the prefetch burstsize to default (512 bytes).
788 *
789 * Maybe we need a way to NOT do these on *some* systems?
790 */
791 put_cmd640_reg(CMDTIM, 0);
792 put_cmd640_reg(BRST, 0x40);
793
794 b = get_cmd640_reg(CNTRL);
795
796 /*
797 * Try to enable the secondary interface, if not already enabled
798 */
799 if (secondary_port_responding()) {
800 if ((b & CNTRL_ENA_2ND)) {
801 second_port_cmd640 = 1;
802 port2 = "okay";
803 } else if (cmd640_vlb) {
804 second_port_cmd640 = 1;
805 port2 = "alive";
806 } else
807 port2 = "not cmd640";
808 } else {
809 put_cmd640_reg(CNTRL, b ^ CNTRL_ENA_2ND); /* toggle the bit */
810 if (secondary_port_responding()) {
811 second_port_cmd640 = 1;
812 port2 = "enabled";
813 } else {
814 put_cmd640_reg(CNTRL, b); /* restore original setting */
815 port2 = "not responding";
816 }
817 }
818
819 /*
820 * Initialize data for secondary cmd640 port, if enabled
821 */
822 if (second_port_cmd640)
823 hws[1] = &hw[1];
824
825 printk(KERN_INFO "cmd640: %sserialized, secondary interface %s\n",
826 second_port_cmd640 ? "" : "not ", port2);
827
828 #ifdef CMD640_DUMP_REGS
829 cmd640_dump_regs();
830 #endif
831
832 host = ide_host_alloc(&cmd640_port_info, hws);
833 if (host)
834 ide_host_register(host, &cmd640_port_info, hws);
835
836 return 1;
837 }
838
839 module_param_named(probe_vlb, cmd640_vlb, bool, 0);
840 MODULE_PARM_DESC(probe_vlb, "probe for VLB version of CMD640 chipset");
841
842 module_init(cmd640x_init);
843
844 MODULE_LICENSE("GPL");
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