drivers/ide/pci/cs5530.c

   1 /*
   2  * linux/drivers/ide/pci/cs5530.c               Version 0.72    Mar 10 2007
   3  *
   4  * Copyright (C) 2000                   Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2000                   Mark Lord <mlord@pobox.com>
   6  * Copyright (C) 2007                   Bartlomiej Zolnierkiewicz
   7  *
   8  * May be copied or modified under the terms of the GNU General Public License
   9  *
  10  * Development of this chipset driver was funded
  11  * by the nice folks at National Semiconductor.
  12  *
  13  * Documentation:
  14  *      CS5530 documentation available from National Semiconductor.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/timer.h>
  22 #include <linux/mm.h>
  23 #include <linux/ioport.h>
  24 #include <linux/blkdev.h>
  25 #include <linux/hdreg.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/pci.h>
  28 #include <linux/init.h>
  29 #include <linux/ide.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33 /**
  34  *      cs5530_xfer_set_mode    -       set a new transfer mode at the drive
  35  *      @drive: drive to tune
  36  *      @mode: new mode
  37  *
  38  *      Logging wrapper to the IDE driver speed configuration. This can
  39  *      probably go away now.
  40  */
  41
  42 static int cs5530_set_xfer_mode (ide_drive_t *drive, u8 mode)
  43 {
  44         printk(KERN_DEBUG "%s: cs5530_set_xfer_mode(%s)\n",
  45                 drive->name, ide_xfer_verbose(mode));
  46         return (ide_config_drive_speed(drive, mode));
  47 }
  48
  49 /*
  50  * Here are the standard PIO mode 0-4 timings for each "format".
  51  * Format-0 uses fast data reg timings, with slower command reg timings.
  52  * Format-1 uses fast timings for all registers, but won't work with all drives.
  53  */
  54 static unsigned int cs5530_pio_timings[2][5] = {
  55         {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
  56         {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
  57 };
  58
  59 /*
  60  * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
  61  */
  62 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
  63 #define CS5530_BASEREG(hwif)    (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
  64
  65 /**
  66  *      cs5530_tuneproc         -       select/set PIO modes
  67  *
  68  *      cs5530_tuneproc() handles selection/setting of PIO modes
  69  *      for both the chipset and drive.
  70  *
  71  *      The ide_init_cs5530() routine guarantees that all drives
  72  *      will have valid default PIO timings set up before we get here.
  73  */
  74
  75 static void cs5530_tuneproc (ide_drive_t *drive, u8 pio)        /* pio=255 means "autotune" */
  76 {
  77         ide_hwif_t      *hwif = HWIF(drive);
  78         unsigned int    format;
  79         unsigned long basereg = CS5530_BASEREG(hwif);
  80         static u8       modes[5] = { XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4};
  81
  82         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
  83         if (!cs5530_set_xfer_mode(drive, modes[pio])) {
  84                 format = (inl(basereg + 4) >> 31) & 1;
  85                 outl(cs5530_pio_timings[format][pio],
  86                         basereg+(drive->select.b.unit<<3));
  87         }
  88 }
  89
  90 /**
  91  *      cs5530_udma_filter      -       UDMA filter
  92  *      @drive: drive
  93  *
  94  *      cs5530_udma_filter() does UDMA mask filtering for the given drive
  95  *      taking into the consideration capabilities of the mate device.
  96  *
  97  *      The CS5530 specifies that two drives sharing a cable cannot mix
  98  *      UDMA/MDMA.  It has to be one or the other, for the pair, though
  99  *      different timings can still be chosen for each drive.  We could
 100  *      set the appropriate timing bits on the fly, but that might be
 101  *      a bit confusing.  So, for now we statically handle this requirement
 102  *      by looking at our mate drive to see what it is capable of, before
 103  *      choosing a mode for our own drive.
 104  *
 105  *      Note: This relies on the fact we never fail from UDMA to MWDMA2
 106  *      but instead drop to PIO.
 107  */
 108
 109 static u8 cs5530_udma_filter(ide_drive_t *drive)
 110 {
 111         ide_hwif_t *hwif = drive->hwif;
 112         ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
 113         struct hd_driveid *mateid = mate->id;
 114         u8 mask = hwif->ultra_mask;
 115
 116         if (mate->present == 0)
 117                 goto out;
 118
 119         if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
 120                 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
 121                         goto out;
 122                 if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
 123                         mask = 0;
 124         }
 125 out:
 126         return mask;
 127 }
 128
 129 /**
 130  *      cs5530_config_dma       -       set DMA/UDMA mode
 131  *      @drive: drive to tune
 132  *
 133  *      cs5530_config_dma() handles setting of DMA/UDMA mode
 134  *      for both the chipset and drive.
 135  */
 136
 137 static int cs5530_config_dma(ide_drive_t *drive)
 138 {
 139         ide_hwif_t *hwif = drive->hwif;
 140         unsigned int reg, timings = 0;
 141         unsigned long basereg;
 142         u8 unit = drive->dn & 1, mode = 0;
 143
 144         if (ide_use_dma(drive))
 145                 mode = ide_max_dma_mode(drive);
 146
 147         /*
 148          * Tell the drive to switch to the new mode; abort on failure.
 149          */
 150         if (!mode || cs5530_set_xfer_mode(drive, mode))
 151                 return 1;       /* failure */
 152
 153         /*
 154          * Now tune the chipset to match the drive:
 155          */
 156         switch (mode) {
 157                 case XFER_UDMA_0:       timings = 0x00921250; break;
 158                 case XFER_UDMA_1:       timings = 0x00911140; break;
 159                 case XFER_UDMA_2:       timings = 0x00911030; break;
 160                 case XFER_MW_DMA_0:     timings = 0x00077771; break;
 161                 case XFER_MW_DMA_1:     timings = 0x00012121; break;
 162                 case XFER_MW_DMA_2:     timings = 0x00002020; break;
 163                 default:
 164                         BUG();
 165                         break;
 166         }
 167         basereg = CS5530_BASEREG(hwif);
 168         reg = inl(basereg + 4);                 /* get drive0 config register */
 169         timings |= reg & 0x80000000;            /* preserve PIO format bit */
 170         if (unit == 0) {                        /* are we configuring drive0? */
 171                 outl(timings, basereg + 4);     /* write drive0 config register */
 172         } else {
 173                 if (timings & 0x00100000)
 174                         reg |=  0x00100000;     /* enable UDMA timings for both drives */
 175                 else
 176                         reg &= ~0x00100000;     /* disable UDMA timings for both drives */
 177                 outl(reg, basereg + 4);         /* write drive0 config register */
 178                 outl(timings, basereg + 12);    /* write drive1 config register */
 179         }
 180
 181         return 0;       /* success */
 182 }
 183
 184 /**
 185  *      init_chipset_5530       -       set up 5530 bridge
 186  *      @dev: PCI device
 187  *      @name: device name
 188  *
 189  *      Initialize the cs5530 bridge for reliable IDE DMA operation.
 190  */
 191
 192 static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const char *name)
 193 {
 194         struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
 195         unsigned long flags;
 196
 197         dev = NULL;
 198         while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
 199                 switch (dev->device) {
 200                         case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
 201                                 master_0 = pci_dev_get(dev);
 202                                 break;
 203                         case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
 204                                 cs5530_0 = pci_dev_get(dev);
 205                                 break;
 206                 }
 207         }
 208         if (!master_0) {
 209                 printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
 210                 goto out;
 211         }
 212         if (!cs5530_0) {
 213                 printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
 214                 goto out;
 215         }
 216
 217         spin_lock_irqsave(&ide_lock, flags);
 218                 /* all CPUs (there should only be one CPU with this chipset) */
 219
 220         /*
 221          * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
 222          * -->  OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
 223          */
 224
 225         pci_set_master(cs5530_0);
 226         pci_set_mwi(cs5530_0);
 227
 228         /*
 229          * Set PCI CacheLineSize to 16-bytes:
 230          * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
 231          */
 232
 233         pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
 234
 235         /*
 236          * Disable trapping of UDMA register accesses (Win98 hack):
 237          * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
 238          */
 239
 240         pci_write_config_word(cs5530_0, 0xd0, 0x5006);
 241
 242         /*
 243          * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
 244          * The other settings are what is necessary to get the register
 245          * into a sane state for IDE DMA operation.
 246          */
 247
 248         pci_write_config_byte(master_0, 0x40, 0x1e);
 249
 250         /*
 251          * Set max PCI burst size (16-bytes seems to work best):
 252          *         16bytes: set bit-1 at 0x41 (reg value of 0x16)
 253          *      all others: clear bit-1 at 0x41, and do:
 254          *        128bytes: OR 0x00 at 0x41
 255          *        256bytes: OR 0x04 at 0x41
 256          *        512bytes: OR 0x08 at 0x41
 257          *       1024bytes: OR 0x0c at 0x41
 258          */
 259
 260         pci_write_config_byte(master_0, 0x41, 0x14);
 261
 262         /*
 263          * These settings are necessary to get the chip
 264          * into a sane state for IDE DMA operation.
 265          */
 266
 267         pci_write_config_byte(master_0, 0x42, 0x00);
 268         pci_write_config_byte(master_0, 0x43, 0xc1);
 269
 270         spin_unlock_irqrestore(&ide_lock, flags);
 271
 272 out:
 273         pci_dev_put(master_0);
 274         pci_dev_put(cs5530_0);
 275         return 0;
 276 }
 277
 278 /**
 279  *      init_hwif_cs5530        -       initialise an IDE channel
 280  *      @hwif: IDE to initialize
 281  *
 282  *      This gets invoked by the IDE driver once for each channel. It
 283  *      performs channel-specific pre-initialization before drive probing.
 284  */
 285
 286 static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
 287 {
 288         unsigned long basereg;
 289         u32 d0_timings;
 290         hwif->autodma = 0;
 291
 292         if (hwif->mate)
 293                 hwif->serialized = hwif->mate->serialized = 1;
 294
 295         hwif->tuneproc = &cs5530_tuneproc;
 296         basereg = CS5530_BASEREG(hwif);
 297         d0_timings = inl(basereg + 0);
 298         if (CS5530_BAD_PIO(d0_timings)) {
 299                 /* PIO timings not initialized? */
 300                 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
 301                 if (!hwif->drives[0].autotune)
 302                         hwif->drives[0].autotune = 1;
 303                         /* needs autotuning later */
 304         }
 305         if (CS5530_BAD_PIO(inl(basereg + 8))) {
 306                 /* PIO timings not initialized? */
 307                 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
 308                 if (!hwif->drives[1].autotune)
 309                         hwif->drives[1].autotune = 1;
 310                         /* needs autotuning later */
 311         }
 312
 313         hwif->atapi_dma = 1;
 314         hwif->ultra_mask = 0x07;
 315         hwif->mwdma_mask = 0x07;
 316
 317         hwif->udma_filter = cs5530_udma_filter;
 318         hwif->ide_dma_check = &cs5530_config_dma;
 319         if (!noautodma)
 320                 hwif->autodma = 1;
 321         hwif->drives[0].autodma = hwif->autodma;
 322         hwif->drives[1].autodma = hwif->autodma;
 323 }
 324
 325 static ide_pci_device_t cs5530_chipset __devinitdata = {
 326         .name           = "CS5530",
 327         .init_chipset   = init_chipset_cs5530,
 328         .init_hwif      = init_hwif_cs5530,
 329         .channels       = 2,
 330         .autodma        = AUTODMA,
 331         .bootable       = ON_BOARD,
 332 };
 333
 334 static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 335 {
 336         return ide_setup_pci_device(dev, &cs5530_chipset);
 337 }
 338
 339 static struct pci_device_id cs5530_pci_tbl[] = {
 340         { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 341         { 0, },
 342 };
 343 MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
 344
 345 static struct pci_driver driver = {
 346         .name           = "CS5530 IDE",
 347         .id_table       = cs5530_pci_tbl,
 348         .probe          = cs5530_init_one,
 349 };
 350
 351 static int __init cs5530_ide_init(void)
 352 {
 353         return ide_pci_register_driver(&driver);
 354 }
 355
 356 module_init(cs5530_ide_init);
 357
 358 MODULE_AUTHOR("Mark Lord");
 359 MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
 360 MODULE_LICENSE("GPL");