drivers/ide/pci/cs5530.c

   1 /*
   2  * linux/drivers/ide/pci/cs5530.c               Version 0.74    Jul 28 2007
   3  *
   4  * Copyright (C) 2000                   Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2000                   Mark Lord <mlord@pobox.com>
   6  * Copyright (C) 2007                   Bartlomiej Zolnierkiewicz
   7  *
   8  * May be copied or modified under the terms of the GNU General Public License
   9  *
  10  * Development of this chipset driver was funded
  11  * by the nice folks at National Semiconductor.
  12  *
  13  * Documentation:
  14  *      CS5530 documentation available from National Semiconductor.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/timer.h>
  22 #include <linux/mm.h>
  23 #include <linux/ioport.h>
  24 #include <linux/blkdev.h>
  25 #include <linux/hdreg.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/pci.h>
  28 #include <linux/init.h>
  29 #include <linux/ide.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33 /**
  34  *      cs5530_xfer_set_mode    -       set a new transfer mode at the drive
  35  *      @drive: drive to tune
  36  *      @mode: new mode
  37  *
  38  *      Logging wrapper to the IDE driver speed configuration. This can
  39  *      probably go away now.
  40  */
  41
  42 static int cs5530_set_xfer_mode (ide_drive_t *drive, u8 mode)
  43 {
  44         printk(KERN_DEBUG "%s: cs5530_set_xfer_mode(%s)\n",
  45                 drive->name, ide_xfer_verbose(mode));
  46         return (ide_config_drive_speed(drive, mode));
  47 }
  48
  49 /*
  50  * Here are the standard PIO mode 0-4 timings for each "format".
  51  * Format-0 uses fast data reg timings, with slower command reg timings.
  52  * Format-1 uses fast timings for all registers, but won't work with all drives.
  53  */
  54 static unsigned int cs5530_pio_timings[2][5] = {
  55         {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
  56         {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
  57 };
  58
  59 /*
  60  * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
  61  */
  62 #define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
  63 #define CS5530_BASEREG(hwif)    (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
  64
  65 static void cs5530_tunepio(ide_drive_t *drive, u8 pio)
  66 {
  67         unsigned long basereg = CS5530_BASEREG(drive->hwif);
  68         unsigned int format = (inl(basereg + 4) >> 31) & 1;
  69
  70         outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
  71 }
  72
  73 /**
  74  *      cs5530_set_pio_mode     -       set PIO mode
  75  *      @drive: drive
  76  *      @pio: PIO mode number
  77  *
  78  *      Handles setting of PIO mode for both the chipset and drive.
  79  *
  80  *      The init_hwif_cs5530() routine guarantees that all drives
  81  *      will have valid default PIO timings set up before we get here.
  82  */
  83
  84 static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio)
  85 {
  86         if (cs5530_set_xfer_mode(drive, XFER_PIO_0 + pio) == 0)
  87                 cs5530_tunepio(drive, pio);
  88 }
  89
  90 /**
  91  *      cs5530_udma_filter      -       UDMA filter
  92  *      @drive: drive
  93  *
  94  *      cs5530_udma_filter() does UDMA mask filtering for the given drive
  95  *      taking into the consideration capabilities of the mate device.
  96  *
  97  *      The CS5530 specifies that two drives sharing a cable cannot mix
  98  *      UDMA/MDMA.  It has to be one or the other, for the pair, though
  99  *      different timings can still be chosen for each drive.  We could
 100  *      set the appropriate timing bits on the fly, but that might be
 101  *      a bit confusing.  So, for now we statically handle this requirement
 102  *      by looking at our mate drive to see what it is capable of, before
 103  *      choosing a mode for our own drive.
 104  *
 105  *      Note: This relies on the fact we never fail from UDMA to MWDMA2
 106  *      but instead drop to PIO.
 107  */
 108
 109 static u8 cs5530_udma_filter(ide_drive_t *drive)
 110 {
 111         ide_hwif_t *hwif = drive->hwif;
 112         ide_drive_t *mate = &hwif->drives[(drive->dn & 1) ^ 1];
 113         struct hd_driveid *mateid = mate->id;
 114         u8 mask = hwif->ultra_mask;
 115
 116         if (mate->present == 0)
 117                 goto out;
 118
 119         if ((mateid->capability & 1) && __ide_dma_bad_drive(mate) == 0) {
 120                 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
 121                         goto out;
 122                 if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
 123                         mask = 0;
 124         }
 125 out:
 126         return mask;
 127 }
 128
 129 /**
 130  *      cs5530_config_dma       -       set DMA/UDMA mode
 131  *      @drive: drive to tune
 132  *
 133  *      cs5530_config_dma() handles setting of DMA/UDMA mode
 134  *      for both the chipset and drive.
 135  */
 136
 137 static int cs5530_config_dma(ide_drive_t *drive)
 138 {
 139         if (ide_tune_dma(drive))
 140                 return 0;
 141
 142         return 1;
 143 }
 144
 145 static int cs5530_tune_chipset(ide_drive_t *drive, const u8 mode)
 146 {
 147         unsigned long basereg;
 148         unsigned int reg, timings = 0;
 149
 150         /*
 151          * Tell the drive to switch to the new mode; abort on failure.
 152          */
 153         if (cs5530_set_xfer_mode(drive, mode))
 154                 return 1;       /* failure */
 155
 156         /*
 157          * Now tune the chipset to match the drive:
 158          */
 159         switch (mode) {
 160                 case XFER_UDMA_0:       timings = 0x00921250; break;
 161                 case XFER_UDMA_1:       timings = 0x00911140; break;
 162                 case XFER_UDMA_2:       timings = 0x00911030; break;
 163                 case XFER_MW_DMA_0:     timings = 0x00077771; break;
 164                 case XFER_MW_DMA_1:     timings = 0x00012121; break;
 165                 case XFER_MW_DMA_2:     timings = 0x00002020; break;
 166                 default:
 167                         BUG();
 168                         break;
 169         }
 170         basereg = CS5530_BASEREG(drive->hwif);
 171         reg = inl(basereg + 4);                 /* get drive0 config register */
 172         timings |= reg & 0x80000000;            /* preserve PIO format bit */
 173         if ((drive-> dn & 1) == 0) {            /* are we configuring drive0? */
 174                 outl(timings, basereg + 4);     /* write drive0 config register */
 175         } else {
 176                 if (timings & 0x00100000)
 177                         reg |=  0x00100000;     /* enable UDMA timings for both drives */
 178                 else
 179                         reg &= ~0x00100000;     /* disable UDMA timings for both drives */
 180                 outl(reg, basereg + 4);         /* write drive0 config register */
 181                 outl(timings, basereg + 12);    /* write drive1 config register */
 182         }
 183
 184         return 0;       /* success */
 185 }
 186
 187 /**
 188  *      init_chipset_5530       -       set up 5530 bridge
 189  *      @dev: PCI device
 190  *      @name: device name
 191  *
 192  *      Initialize the cs5530 bridge for reliable IDE DMA operation.
 193  */
 194
 195 static unsigned int __devinit init_chipset_cs5530 (struct pci_dev *dev, const char *name)
 196 {
 197         struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
 198         unsigned long flags;
 199
 200         if (pci_resource_start(dev, 4) == 0)
 201                 return -EFAULT;
 202
 203         dev = NULL;
 204         while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
 205                 switch (dev->device) {
 206                         case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
 207                                 master_0 = pci_dev_get(dev);
 208                                 break;
 209                         case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
 210                                 cs5530_0 = pci_dev_get(dev);
 211                                 break;
 212                 }
 213         }
 214         if (!master_0) {
 215                 printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
 216                 goto out;
 217         }
 218         if (!cs5530_0) {
 219                 printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
 220                 goto out;
 221         }
 222
 223         spin_lock_irqsave(&ide_lock, flags);
 224                 /* all CPUs (there should only be one CPU with this chipset) */
 225
 226         /*
 227          * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
 228          * -->  OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
 229          */
 230
 231         pci_set_master(cs5530_0);
 232         pci_try_set_mwi(cs5530_0);
 233
 234         /*
 235          * Set PCI CacheLineSize to 16-bytes:
 236          * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
 237          */
 238
 239         pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
 240
 241         /*
 242          * Disable trapping of UDMA register accesses (Win98 hack):
 243          * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
 244          */
 245
 246         pci_write_config_word(cs5530_0, 0xd0, 0x5006);
 247
 248         /*
 249          * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
 250          * The other settings are what is necessary to get the register
 251          * into a sane state for IDE DMA operation.
 252          */
 253
 254         pci_write_config_byte(master_0, 0x40, 0x1e);
 255
 256         /*
 257          * Set max PCI burst size (16-bytes seems to work best):
 258          *         16bytes: set bit-1 at 0x41 (reg value of 0x16)
 259          *      all others: clear bit-1 at 0x41, and do:
 260          *        128bytes: OR 0x00 at 0x41
 261          *        256bytes: OR 0x04 at 0x41
 262          *        512bytes: OR 0x08 at 0x41
 263          *       1024bytes: OR 0x0c at 0x41
 264          */
 265
 266         pci_write_config_byte(master_0, 0x41, 0x14);
 267
 268         /*
 269          * These settings are necessary to get the chip
 270          * into a sane state for IDE DMA operation.
 271          */
 272
 273         pci_write_config_byte(master_0, 0x42, 0x00);
 274         pci_write_config_byte(master_0, 0x43, 0xc1);
 275
 276         spin_unlock_irqrestore(&ide_lock, flags);
 277
 278 out:
 279         pci_dev_put(master_0);
 280         pci_dev_put(cs5530_0);
 281         return 0;
 282 }
 283
 284 /**
 285  *      init_hwif_cs5530        -       initialise an IDE channel
 286  *      @hwif: IDE to initialize
 287  *
 288  *      This gets invoked by the IDE driver once for each channel. It
 289  *      performs channel-specific pre-initialization before drive probing.
 290  */
 291
 292 static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
 293 {
 294         unsigned long basereg;
 295         u32 d0_timings;
 296         hwif->autodma = 0;
 297
 298         if (hwif->mate)
 299                 hwif->serialized = hwif->mate->serialized = 1;
 300
 301         hwif->set_pio_mode = &cs5530_set_pio_mode;
 302         hwif->speedproc = &cs5530_tune_chipset;
 303
 304         basereg = CS5530_BASEREG(hwif);
 305         d0_timings = inl(basereg + 0);
 306         if (CS5530_BAD_PIO(d0_timings)) {
 307                 /* PIO timings not initialized? */
 308                 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
 309                 if (!hwif->drives[0].autotune)
 310                         hwif->drives[0].autotune = 1;
 311                         /* needs autotuning later */
 312         }
 313         if (CS5530_BAD_PIO(inl(basereg + 8))) {
 314                 /* PIO timings not initialized? */
 315                 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
 316                 if (!hwif->drives[1].autotune)
 317                         hwif->drives[1].autotune = 1;
 318                         /* needs autotuning later */
 319         }
 320
 321         if (hwif->dma_base == 0)
 322                 return;
 323
 324         hwif->atapi_dma = 1;
 325         hwif->ultra_mask = 0x07;
 326         hwif->mwdma_mask = 0x07;
 327
 328         hwif->udma_filter = cs5530_udma_filter;
 329         hwif->ide_dma_check = &cs5530_config_dma;
 330         if (!noautodma)
 331                 hwif->autodma = 1;
 332         hwif->drives[0].autodma = hwif->autodma;
 333         hwif->drives[1].autodma = hwif->autodma;
 334 }
 335
 336 static ide_pci_device_t cs5530_chipset __devinitdata = {
 337         .name           = "CS5530",
 338         .init_chipset   = init_chipset_cs5530,
 339         .init_hwif      = init_hwif_cs5530,
 340         .autodma        = AUTODMA,
 341         .bootable       = ON_BOARD,
 342         .pio_mask       = ATA_PIO4,
 343 };
 344
 345 static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 346 {
 347         return ide_setup_pci_device(dev, &cs5530_chipset);
 348 }
 349
 350 static struct pci_device_id cs5530_pci_tbl[] = {
 351         { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 352         { 0, },
 353 };
 354 MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
 355
 356 static struct pci_driver driver = {
 357         .name           = "CS5530 IDE",
 358         .id_table       = cs5530_pci_tbl,
 359         .probe          = cs5530_init_one,
 360 };
 361
 362 static int __init cs5530_ide_init(void)
 363 {
 364         return ide_pci_register_driver(&driver);
 365 }
 366
 367 module_init(cs5530_ide_init);
 368
 369 MODULE_AUTHOR("Mark Lord");
 370 MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
 371 MODULE_LICENSE("GPL");