drivers/ide/pci/cy82c693.c

   1 /*
   2  * linux/drivers/ide/pci/cy82c693.c             Version 0.44    Nov 8, 2007
   3  *
   4  *  Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
   5  *  Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
   6  *
   7  * CYPRESS CY82C693 chipset IDE controller
   8  *
   9  * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
  10  * Writing the driver was quite simple, since most of the job is
  11  * done by the generic pci-ide support.
  12  * The hard part was finding the CY82C693's datasheet on Cypress's
  13  * web page :-(. But Altavista solved this problem :-).
  14  *
  15  *
  16  * Notes:
  17  * - I recently got a 16.8G IBM DTTA, so I was able to test it with
  18  *   a large and fast disk - the results look great, so I'd say the
  19  *   driver is working fine :-)
  20  *   hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
  21  * - this is my first linux driver, so there's probably a lot  of room
  22  *   for optimizations and bug fixing, so feel free to do it.
  23  * - use idebus=xx parameter to set PCI bus speed - needed to calc
  24  *   timings for PIO modes (default will be 40)
  25  * - if using PIO mode it's a good idea to set the PIO mode and
  26  *   32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
  27  * - I had some problems with my IBM DHEA with PIO modes < 2
  28  *   (lost interrupts) ?????
  29  * - first tests with DMA look okay, they seem to work, but there is a
  30  *   problem with sound - the BusMaster IDE TimeOut should fixed this
  31  *
  32  * Ancient History:
  33  * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
  34  * ASK@1999-01-23: v0.33 made a few minor code clean ups
  35  *                       removed DMA clock speed setting by default
  36  *                       added boot message
  37  * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
  38  *                       added support to set DMA Controller Clock Speed
  39  * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
  40  *                       on some drives.
  41  * ASK@1998-10-29: v0.3 added support to set DMA modes
  42  * ASK@1998-10-28: v0.2 added support to set PIO modes
  43  * ASK@1998-10-27: v0.1 first version - chipset detection
  44  *
  45  */
  46
  47 #include <linux/module.h>
  48 #include <linux/types.h>
  49 #include <linux/pci.h>
  50 #include <linux/delay.h>
  51 #include <linux/ide.h>
  52 #include <linux/init.h>
  53
  54 #include <asm/io.h>
  55
  56 /* the current version */
  57 #define CY82_VERSION    "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
  58
  59 /*
  60  *      The following are used to debug the driver.
  61  */
  62 #define CY82C693_DEBUG_LOGS     0
  63 #define CY82C693_DEBUG_INFO     0
  64
  65 /* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
  66 #undef CY82C693_SETDMA_CLOCK
  67
  68 /*
  69  *      NOTE: the value for busmaster timeout is tricky and I got it by
  70  *      trial and error!  By using a to low value will cause DMA timeouts
  71  *      and drop IDE performance, and by using a to high value will cause
  72  *      audio playback to scatter.
  73  *      If you know a better value or how to calc it, please let me know.
  74  */
  75
  76 /* twice the value written in cy82c693ub datasheet */
  77 #define BUSMASTER_TIMEOUT       0x50
  78 /*
  79  * the value above was tested on my machine and it seems to work okay
  80  */
  81
  82 /* here are the offset definitions for the registers */
  83 #define CY82_IDE_CMDREG         0x04
  84 #define CY82_IDE_ADDRSETUP      0x48
  85 #define CY82_IDE_MASTER_IOR     0x4C
  86 #define CY82_IDE_MASTER_IOW     0x4D
  87 #define CY82_IDE_SLAVE_IOR      0x4E
  88 #define CY82_IDE_SLAVE_IOW      0x4F
  89 #define CY82_IDE_MASTER_8BIT    0x50
  90 #define CY82_IDE_SLAVE_8BIT     0x51
  91
  92 #define CY82_INDEX_PORT         0x22
  93 #define CY82_DATA_PORT          0x23
  94
  95 #define CY82_INDEX_CTRLREG1     0x01
  96 #define CY82_INDEX_CHANNEL0     0x30
  97 #define CY82_INDEX_CHANNEL1     0x31
  98 #define CY82_INDEX_TIMEOUT      0x32
  99
 100 /* the min and max PCI bus speed in MHz - from datasheet */
 101 #define CY82C963_MIN_BUS_SPEED  25
 102 #define CY82C963_MAX_BUS_SPEED  33
 103
 104 /* the struct for the PIO mode timings */
 105 typedef struct pio_clocks_s {
 106         u8      address_time;   /* Address setup (clocks) */
 107         u8      time_16r;       /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
 108         u8      time_16w;       /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
 109         u8      time_8;         /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
 110 } pio_clocks_t;
 111
 112 /*
 113  * calc clocks using bus_speed
 114  * returns (rounded up) time in bus clocks for time in ns
 115  */
 116 static int calc_clk (int time, int bus_speed)
 117 {
 118         int clocks;
 119
 120         clocks = (time*bus_speed+999)/1000 -1;
 121
 122         if (clocks < 0)
 123                 clocks = 0;
 124
 125         if (clocks > 0x0F)
 126                 clocks = 0x0F;
 127
 128         return clocks;
 129 }
 130
 131 /*
 132  * compute the values for the clock registers for PIO
 133  * mode and pci_clk [MHz] speed
 134  *
 135  * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
 136  *       for mode 3 and 4 drives 8 and 16-bit timings are the same
 137  *
 138  */
 139 static void compute_clocks (u8 pio, pio_clocks_t *p_pclk)
 140 {
 141         int clk1, clk2;
 142         int bus_speed = system_bus_clock();     /* get speed of PCI bus */
 143
 144         /* we don't check against CY82C693's min and max speed,
 145          * so you can play with the idebus=xx parameter
 146          */
 147
 148         /* let's calc the address setup time clocks */
 149         p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
 150
 151         /* let's calc the active and recovery time clocks */
 152         clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
 153
 154         /* calc recovery timing */
 155         clk2 =  ide_pio_timings[pio].cycle_time -
 156                 ide_pio_timings[pio].active_time -
 157                 ide_pio_timings[pio].setup_time;
 158
 159         clk2 = calc_clk(clk2, bus_speed);
 160
 161         clk1 = (clk1<<4)|clk2;  /* combine active and recovery clocks */
 162
 163         /* note: we use the same values for 16bit IOR and IOW
 164          *      those are all the same, since I don't have other
 165          *      timings than those from ide-lib.c
 166          */
 167
 168         p_pclk->time_16r = (u8)clk1;
 169         p_pclk->time_16w = (u8)clk1;
 170
 171         /* what are good values for 8bit ?? */
 172         p_pclk->time_8 = (u8)clk1;
 173 }
 174
 175 /*
 176  * set DMA mode a specific channel for CY82C693
 177  */
 178
 179 static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
 180 {
 181         ide_hwif_t *hwif = drive->hwif;
 182         u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
 183
 184         index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
 185
 186 #if CY82C693_DEBUG_LOGS
 187         /* for debug let's show the previous values */
 188
 189         outb(index, CY82_INDEX_PORT);
 190         data = inb(CY82_DATA_PORT);
 191
 192         printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
 193                 drive->name, HWIF(drive)->channel, drive->select.b.unit,
 194                 (data&0x3), ((data>>2)&1));
 195 #endif /* CY82C693_DEBUG_LOGS */
 196
 197         data = (mode & 3) | (single << 2);
 198
 199         outb(index, CY82_INDEX_PORT);
 200         outb(data, CY82_DATA_PORT);
 201
 202 #if CY82C693_DEBUG_INFO
 203         printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
 204                 drive->name, HWIF(drive)->channel, drive->select.b.unit,
 205                 mode & 3, single);
 206 #endif /* CY82C693_DEBUG_INFO */
 207
 208         /*
 209          * note: below we set the value for Bus Master IDE TimeOut Register
 210          * I'm not absolutly sure what this does, but it solved my problem
 211          * with IDE DMA and sound, so I now can play sound and work with
 212          * my IDE driver at the same time :-)
 213          *
 214          * If you know the correct (best) value for this register please
 215          * let me know - ASK
 216          */
 217
 218         data = BUSMASTER_TIMEOUT;
 219         outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
 220         outb(data, CY82_DATA_PORT);
 221
 222 #if CY82C693_DEBUG_INFO
 223         printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
 224                 drive->name, data);
 225 #endif /* CY82C693_DEBUG_INFO */
 226 }
 227
 228 static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
 229 {
 230         ide_hwif_t *hwif = HWIF(drive);
 231         struct pci_dev *dev = to_pci_dev(hwif->dev);
 232         pio_clocks_t pclk;
 233         unsigned int addrCtrl;
 234
 235         /* select primary or secondary channel */
 236         if (hwif->index > 0) {  /* drive is on the secondary channel */
 237                 dev = pci_get_slot(dev->bus, dev->devfn+1);
 238                 if (!dev) {
 239                         printk(KERN_ERR "%s: tune_drive: "
 240                                 "Cannot find secondary interface!\n",
 241                                 drive->name);
 242                         return;
 243                 }
 244         }
 245
 246 #if CY82C693_DEBUG_LOGS
 247         /* for debug let's show the register values */
 248
 249         if (drive->select.b.unit == 0) {
 250                 /*
 251                  * get master drive registers
 252                  * address setup control register
 253                  * is 32 bit !!!
 254                  */
 255                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 256                 addrCtrl &= 0x0F;
 257
 258                 /* now let's get the remaining registers */
 259                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
 260                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
 261                 pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
 262         } else {
 263                 /*
 264                  * set slave drive registers
 265                  * address setup control register
 266                  * is 32 bit !!!
 267                  */
 268                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 269
 270                 addrCtrl &= 0xF0;
 271                 addrCtrl >>= 4;
 272
 273                 /* now let's get the remaining registers */
 274                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
 275                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
 276                 pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
 277         }
 278
 279         printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
 280                 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
 281                 drive->name, hwif->channel, drive->select.b.unit,
 282                 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 283 #endif /* CY82C693_DEBUG_LOGS */
 284
 285         /* let's calc the values for this PIO mode */
 286         compute_clocks(pio, &pclk);
 287
 288         /* now let's write  the clocks registers */
 289         if (drive->select.b.unit == 0) {
 290                 /*
 291                  * set master drive
 292                  * address setup control register
 293                  * is 32 bit !!!
 294                  */
 295                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 296
 297                 addrCtrl &= (~0xF);
 298                 addrCtrl |= (unsigned int)pclk.address_time;
 299                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 300
 301                 /* now let's set the remaining registers */
 302                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
 303                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
 304                 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
 305
 306                 addrCtrl &= 0xF;
 307         } else {
 308                 /*
 309                  * set slave drive
 310                  * address setup control register
 311                  * is 32 bit !!!
 312                  */
 313                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 314
 315                 addrCtrl &= (~0xF0);
 316                 addrCtrl |= ((unsigned int)pclk.address_time<<4);
 317                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 318
 319                 /* now let's set the remaining registers */
 320                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
 321                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
 322                 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
 323
 324                 addrCtrl >>= 4;
 325                 addrCtrl &= 0xF;
 326         }
 327
 328 #if CY82C693_DEBUG_INFO
 329         printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
 330                 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
 331                 drive->name, hwif->channel, drive->select.b.unit,
 332                 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 333 #endif /* CY82C693_DEBUG_INFO */
 334 }
 335
 336 /*
 337  * this function is called during init and is used to setup the cy82c693 chip
 338  */
 339 static unsigned int __devinit init_chipset_cy82c693(struct pci_dev *dev, const char *name)
 340 {
 341         if (PCI_FUNC(dev->devfn) != 1)
 342                 return 0;
 343
 344 #ifdef CY82C693_SETDMA_CLOCK
 345         u8 data = 0;
 346 #endif /* CY82C693_SETDMA_CLOCK */
 347
 348         /* write info about this verion of the driver */
 349         printk(KERN_INFO CY82_VERSION "\n");
 350
 351 #ifdef CY82C693_SETDMA_CLOCK
 352        /* okay let's set the DMA clock speed */
 353
 354         outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 355         data = inb(CY82_DATA_PORT);
 356
 357 #if CY82C693_DEBUG_INFO
 358         printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
 359                 name, data);
 360 #endif /* CY82C693_DEBUG_INFO */
 361
 362         /*
 363          * for some reason sometimes the DMA controller
 364          * speed is set to ATCLK/2 ???? - we fix this here
 365          *
 366          * note: i don't know what causes this strange behaviour,
 367          *       but even changing the dma speed doesn't solve it :-(
 368          *       the ide performance is still only half the normal speed
 369          *
 370          *       if anybody knows what goes wrong with my machine, please
 371          *       let me know - ASK
 372          */
 373
 374         data |= 0x03;
 375
 376         outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 377         outb(data, CY82_DATA_PORT);
 378
 379 #if CY82C693_DEBUG_INFO
 380         printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
 381                 name, data);
 382 #endif /* CY82C693_DEBUG_INFO */
 383
 384 #endif /* CY82C693_SETDMA_CLOCK */
 385         return 0;
 386 }
 387
 388 /*
 389  * the init function - called for each ide channel once
 390  */
 391 static void __devinit init_hwif_cy82c693(ide_hwif_t *hwif)
 392 {
 393         hwif->set_pio_mode = &cy82c693_set_pio_mode;
 394         hwif->set_dma_mode = &cy82c693_set_dma_mode;
 395 }
 396
 397 static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
 398 {
 399         static ide_hwif_t *primary;
 400         struct pci_dev *dev = to_pci_dev(hwif->dev);
 401
 402         if (PCI_FUNC(dev->devfn) == 1)
 403                 primary = hwif;
 404         else {
 405                 hwif->mate = primary;
 406                 hwif->channel = 1;
 407         }
 408 }
 409
 410 static const struct ide_port_info cy82c693_chipset __devinitdata = {
 411         .name           = "CY82C693",
 412         .init_chipset   = init_chipset_cy82c693,
 413         .init_iops      = init_iops_cy82c693,
 414         .init_hwif      = init_hwif_cy82c693,
 415         .chipset        = ide_cy82c693,
 416         .host_flags     = IDE_HFLAG_SINGLE | IDE_HFLAG_CY82C693 |
 417                           IDE_HFLAG_BOOTABLE,
 418         .pio_mask       = ATA_PIO4,
 419         .swdma_mask     = ATA_SWDMA2,
 420         .mwdma_mask     = ATA_MWDMA2,
 421 };
 422
 423 static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 424 {
 425         struct pci_dev *dev2;
 426         int ret = -ENODEV;
 427
 428         /* CY82C693 is more than only a IDE controller.
 429            Function 1 is primary IDE channel, function 2 - secondary. */
 430         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
 431             PCI_FUNC(dev->devfn) == 1) {
 432                 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
 433                 ret = ide_setup_pci_devices(dev, dev2, &cy82c693_chipset);
 434                 /* We leak pci refs here but thats ok - we can't be unloaded */
 435         }
 436         return ret;
 437 }
 438
 439 static const struct pci_device_id cy82c693_pci_tbl[] = {
 440         { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
 441         { 0, },
 442 };
 443 MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
 444
 445 static struct pci_driver driver = {
 446         .name           = "Cypress_IDE",
 447         .id_table       = cy82c693_pci_tbl,
 448         .probe          = cy82c693_init_one,
 449 };
 450
 451 static int __init cy82c693_ide_init(void)
 452 {
 453         return ide_pci_register_driver(&driver);
 454 }
 455
 456 module_init(cy82c693_ide_init);
 457
 458 MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
 459 MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
 460 MODULE_LICENSE("GPL");