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ide: add IDE_HFLAG_ABUSE_SET_DMA_MODE host flag
[deliverable/linux.git] / drivers / ide / pci / hpt366.c
1 /*
2 * linux/drivers/ide/pci/hpt366.c Version 1.30 Dec 12, 2007
3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
9 *
10 * Thanks to HighPoint Technologies for their assistance, and hardware.
11 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
12 * donation of an ABit BP6 mainboard, processor, and memory acellerated
13 * development and support.
14 *
15 *
16 * HighPoint has its own drivers (open source except for the RAID part)
17 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
18 * This may be useful to anyone wanting to work on this driver, however do not
19 * trust them too much since the code tends to become less and less meaningful
20 * as the time passes... :-/
21 *
22 * Note that final HPT370 support was done by force extraction of GPL.
23 *
24 * - add function for getting/setting power status of drive
25 * - the HPT370's state machine can get confused. reset it before each dma
26 * xfer to prevent that from happening.
27 * - reset state engine whenever we get an error.
28 * - check for busmaster state at end of dma.
29 * - use new highpoint timings.
30 * - detect bus speed using highpoint register.
31 * - use pll if we don't have a clock table. added a 66MHz table that's
32 * just 2x the 33MHz table.
33 * - removed turnaround. NOTE: we never want to switch between pll and
34 * pci clocks as the chip can glitch in those cases. the highpoint
35 * approved workaround slows everything down too much to be useful. in
36 * addition, we would have to serialize access to each chip.
37 * Adrian Sun <a.sun@sun.com>
38 *
39 * add drive timings for 66MHz PCI bus,
40 * fix ATA Cable signal detection, fix incorrect /proc info
41 * add /proc display for per-drive PIO/DMA/UDMA mode and
42 * per-channel ATA-33/66 Cable detect.
43 * Duncan Laurie <void@sun.com>
44 *
45 * fixup /proc output for multiple controllers
46 * Tim Hockin <thockin@sun.com>
47 *
48 * On hpt366:
49 * Reset the hpt366 on error, reset on dma
50 * Fix disabling Fast Interrupt hpt366.
51 * Mike Waychison <crlf@sun.com>
52 *
53 * Added support for 372N clocking and clock switching. The 372N needs
54 * different clocks on read/write. This requires overloading rw_disk and
55 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
56 * keeping me sane.
57 * Alan Cox <alan@redhat.com>
58 *
59 * - fix the clock turnaround code: it was writing to the wrong ports when
60 * called for the secondary channel, caching the current clock mode per-
61 * channel caused the cached register value to get out of sync with the
62 * actual one, the channels weren't serialized, the turnaround shouldn't
63 * be done on 66 MHz PCI bus
64 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
65 * does not allow for this speed anyway
66 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
67 * their primary channel is kind of virtual, it isn't tied to any pins)
68 * - fix/remove bad/unused timing tables and use one set of tables for the whole
69 * HPT37x chip family; save space by introducing the separate transfer mode
70 * table in which the mode lookup is done
71 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
72 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
73 * read it only from the function 0 of HPT374 chips
74 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
75 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
76 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
77 * they tamper with its fields
78 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
79 * since they may tamper with its fields
80 * - prefix the driver startup messages with the real chip name
81 * - claim the extra 240 bytes of I/O space for all chips
82 * - optimize the UltraDMA filtering and the drive list lookup code
83 * - use pci_get_slot() to get to the function 1 of HPT36x/374
84 * - cache offset of the channel's misc. control registers (MCRs) being used
85 * throughout the driver
86 * - only touch the relevant MCR when detecting the cable type on HPT374's
87 * function 1
88 * - rename all the register related variables consistently
89 * - move all the interrupt twiddling code from the speedproc handlers into
90 * init_hwif_hpt366(), also grouping all the DMA related code together there
91 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
92 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
93 * when setting an UltraDMA mode
94 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
95 * the best possible one
96 * - clean up DMA timeout handling for HPT370
97 * - switch to using the enumeration type to differ between the numerous chip
98 * variants, matching PCI device/revision ID with the chip type early, at the
99 * init_setup stage
100 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
101 * stop duplicating it for each channel by storing the pointer in the pci_dev
102 * structure: first, at the init_setup stage, point it to a static "template"
103 * with only the chip type and its specific base DPLL frequency, the highest
104 * UltraDMA mode, and the chip settings table pointer filled, then, at the
105 * init_chipset stage, allocate per-chip instance and fill it with the rest
106 * of the necessary information
107 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
108 * switch to calculating PCI clock frequency based on the chip's base DPLL
109 * frequency
110 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
111 * anything newer than HPT370/A (except HPT374 that is not capable of this
112 * mode according to the manual)
113 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
114 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
115 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
116 * the register setting lists into the table indexed by the clock selected
117 * - set the correct hwif->ultra_mask for each individual chip
118 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
120 */
121
122 #include <linux/types.h>
123 #include <linux/module.h>
124 #include <linux/kernel.h>
125 #include <linux/delay.h>
126 #include <linux/timer.h>
127 #include <linux/mm.h>
128 #include <linux/ioport.h>
129 #include <linux/blkdev.h>
130 #include <linux/hdreg.h>
131
132 #include <linux/interrupt.h>
133 #include <linux/pci.h>
134 #include <linux/init.h>
135 #include <linux/ide.h>
136
137 #include <asm/uaccess.h>
138 #include <asm/io.h>
139 #include <asm/irq.h>
140
141 /* various tuning parameters */
142 #define HPT_RESET_STATE_ENGINE
143 #undef HPT_DELAY_INTERRUPT
144 #define HPT_SERIALIZE_IO 0
145
146 static const char *quirk_drives[] = {
147 "QUANTUM FIREBALLlct08 08",
148 "QUANTUM FIREBALLP KA6.4",
149 "QUANTUM FIREBALLP LM20.4",
150 "QUANTUM FIREBALLP LM20.5",
151 NULL
152 };
153
154 static const char *bad_ata100_5[] = {
155 "IBM-DTLA-307075",
156 "IBM-DTLA-307060",
157 "IBM-DTLA-307045",
158 "IBM-DTLA-307030",
159 "IBM-DTLA-307020",
160 "IBM-DTLA-307015",
161 "IBM-DTLA-305040",
162 "IBM-DTLA-305030",
163 "IBM-DTLA-305020",
164 "IC35L010AVER07-0",
165 "IC35L020AVER07-0",
166 "IC35L030AVER07-0",
167 "IC35L040AVER07-0",
168 "IC35L060AVER07-0",
169 "WDC AC310200R",
170 NULL
171 };
172
173 static const char *bad_ata66_4[] = {
174 "IBM-DTLA-307075",
175 "IBM-DTLA-307060",
176 "IBM-DTLA-307045",
177 "IBM-DTLA-307030",
178 "IBM-DTLA-307020",
179 "IBM-DTLA-307015",
180 "IBM-DTLA-305040",
181 "IBM-DTLA-305030",
182 "IBM-DTLA-305020",
183 "IC35L010AVER07-0",
184 "IC35L020AVER07-0",
185 "IC35L030AVER07-0",
186 "IC35L040AVER07-0",
187 "IC35L060AVER07-0",
188 "WDC AC310200R",
189 "MAXTOR STM3320620A",
190 NULL
191 };
192
193 static const char *bad_ata66_3[] = {
194 "WDC AC310200R",
195 NULL
196 };
197
198 static const char *bad_ata33[] = {
199 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
200 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
201 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
202 "Maxtor 90510D4",
203 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
204 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
205 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
206 NULL
207 };
208
209 static u8 xfer_speeds[] = {
210 XFER_UDMA_6,
211 XFER_UDMA_5,
212 XFER_UDMA_4,
213 XFER_UDMA_3,
214 XFER_UDMA_2,
215 XFER_UDMA_1,
216 XFER_UDMA_0,
217
218 XFER_MW_DMA_2,
219 XFER_MW_DMA_1,
220 XFER_MW_DMA_0,
221
222 XFER_PIO_4,
223 XFER_PIO_3,
224 XFER_PIO_2,
225 XFER_PIO_1,
226 XFER_PIO_0
227 };
228
229 /* Key for bus clock timings
230 * 36x 37x
231 * bits bits
232 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
233 * cycles = value + 1
234 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
235 * cycles = value + 1
236 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
237 * register access.
238 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
239 * register access.
240 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
241 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
242 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
243 * MW DMA xfer.
244 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
245 * task file register access.
246 * 28 28 UDMA enable.
247 * 29 29 DMA enable.
248 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
249 * PIO xfer.
250 * 31 31 FIFO enable.
251 */
252
253 static u32 forty_base_hpt36x[] = {
254 /* XFER_UDMA_6 */ 0x900fd943,
255 /* XFER_UDMA_5 */ 0x900fd943,
256 /* XFER_UDMA_4 */ 0x900fd943,
257 /* XFER_UDMA_3 */ 0x900ad943,
258 /* XFER_UDMA_2 */ 0x900bd943,
259 /* XFER_UDMA_1 */ 0x9008d943,
260 /* XFER_UDMA_0 */ 0x9008d943,
261
262 /* XFER_MW_DMA_2 */ 0xa008d943,
263 /* XFER_MW_DMA_1 */ 0xa010d955,
264 /* XFER_MW_DMA_0 */ 0xa010d9fc,
265
266 /* XFER_PIO_4 */ 0xc008d963,
267 /* XFER_PIO_3 */ 0xc010d974,
268 /* XFER_PIO_2 */ 0xc010d997,
269 /* XFER_PIO_1 */ 0xc010d9c7,
270 /* XFER_PIO_0 */ 0xc018d9d9
271 };
272
273 static u32 thirty_three_base_hpt36x[] = {
274 /* XFER_UDMA_6 */ 0x90c9a731,
275 /* XFER_UDMA_5 */ 0x90c9a731,
276 /* XFER_UDMA_4 */ 0x90c9a731,
277 /* XFER_UDMA_3 */ 0x90cfa731,
278 /* XFER_UDMA_2 */ 0x90caa731,
279 /* XFER_UDMA_1 */ 0x90cba731,
280 /* XFER_UDMA_0 */ 0x90c8a731,
281
282 /* XFER_MW_DMA_2 */ 0xa0c8a731,
283 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
284 /* XFER_MW_DMA_0 */ 0xa0c8a797,
285
286 /* XFER_PIO_4 */ 0xc0c8a731,
287 /* XFER_PIO_3 */ 0xc0c8a742,
288 /* XFER_PIO_2 */ 0xc0d0a753,
289 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
290 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
291 };
292
293 static u32 twenty_five_base_hpt36x[] = {
294 /* XFER_UDMA_6 */ 0x90c98521,
295 /* XFER_UDMA_5 */ 0x90c98521,
296 /* XFER_UDMA_4 */ 0x90c98521,
297 /* XFER_UDMA_3 */ 0x90cf8521,
298 /* XFER_UDMA_2 */ 0x90cf8521,
299 /* XFER_UDMA_1 */ 0x90cb8521,
300 /* XFER_UDMA_0 */ 0x90cb8521,
301
302 /* XFER_MW_DMA_2 */ 0xa0ca8521,
303 /* XFER_MW_DMA_1 */ 0xa0ca8532,
304 /* XFER_MW_DMA_0 */ 0xa0ca8575,
305
306 /* XFER_PIO_4 */ 0xc0ca8521,
307 /* XFER_PIO_3 */ 0xc0ca8532,
308 /* XFER_PIO_2 */ 0xc0ca8542,
309 /* XFER_PIO_1 */ 0xc0d08572,
310 /* XFER_PIO_0 */ 0xc0d08585
311 };
312
313 #if 0
314 /* These are the timing tables from the HighPoint open source drivers... */
315 static u32 thirty_three_base_hpt37x[] = {
316 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
317 /* XFER_UDMA_5 */ 0x12446231,
318 /* XFER_UDMA_4 */ 0x12446231,
319 /* XFER_UDMA_3 */ 0x126c6231,
320 /* XFER_UDMA_2 */ 0x12486231,
321 /* XFER_UDMA_1 */ 0x124c6233,
322 /* XFER_UDMA_0 */ 0x12506297,
323
324 /* XFER_MW_DMA_2 */ 0x22406c31,
325 /* XFER_MW_DMA_1 */ 0x22406c33,
326 /* XFER_MW_DMA_0 */ 0x22406c97,
327
328 /* XFER_PIO_4 */ 0x06414e31,
329 /* XFER_PIO_3 */ 0x06414e42,
330 /* XFER_PIO_2 */ 0x06414e53,
331 /* XFER_PIO_1 */ 0x06814e93,
332 /* XFER_PIO_0 */ 0x06814ea7
333 };
334
335 static u32 fifty_base_hpt37x[] = {
336 /* XFER_UDMA_6 */ 0x12848242,
337 /* XFER_UDMA_5 */ 0x12848242,
338 /* XFER_UDMA_4 */ 0x12ac8242,
339 /* XFER_UDMA_3 */ 0x128c8242,
340 /* XFER_UDMA_2 */ 0x120c8242,
341 /* XFER_UDMA_1 */ 0x12148254,
342 /* XFER_UDMA_0 */ 0x121882ea,
343
344 /* XFER_MW_DMA_2 */ 0x22808242,
345 /* XFER_MW_DMA_1 */ 0x22808254,
346 /* XFER_MW_DMA_0 */ 0x228082ea,
347
348 /* XFER_PIO_4 */ 0x0a81f442,
349 /* XFER_PIO_3 */ 0x0a81f443,
350 /* XFER_PIO_2 */ 0x0a81f454,
351 /* XFER_PIO_1 */ 0x0ac1f465,
352 /* XFER_PIO_0 */ 0x0ac1f48a
353 };
354
355 static u32 sixty_six_base_hpt37x[] = {
356 /* XFER_UDMA_6 */ 0x1c869c62,
357 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
358 /* XFER_UDMA_4 */ 0x1c8a9c62,
359 /* XFER_UDMA_3 */ 0x1c8e9c62,
360 /* XFER_UDMA_2 */ 0x1c929c62,
361 /* XFER_UDMA_1 */ 0x1c9a9c62,
362 /* XFER_UDMA_0 */ 0x1c829c62,
363
364 /* XFER_MW_DMA_2 */ 0x2c829c62,
365 /* XFER_MW_DMA_1 */ 0x2c829c66,
366 /* XFER_MW_DMA_0 */ 0x2c829d2e,
367
368 /* XFER_PIO_4 */ 0x0c829c62,
369 /* XFER_PIO_3 */ 0x0c829c84,
370 /* XFER_PIO_2 */ 0x0c829ca6,
371 /* XFER_PIO_1 */ 0x0d029d26,
372 /* XFER_PIO_0 */ 0x0d029d5e
373 };
374 #else
375 /*
376 * The following are the new timing tables with PIO mode data/taskfile transfer
377 * overclocking fixed...
378 */
379
380 /* This table is taken from the HPT370 data manual rev. 1.02 */
381 static u32 thirty_three_base_hpt37x[] = {
382 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
383 /* XFER_UDMA_5 */ 0x16455031,
384 /* XFER_UDMA_4 */ 0x16455031,
385 /* XFER_UDMA_3 */ 0x166d5031,
386 /* XFER_UDMA_2 */ 0x16495031,
387 /* XFER_UDMA_1 */ 0x164d5033,
388 /* XFER_UDMA_0 */ 0x16515097,
389
390 /* XFER_MW_DMA_2 */ 0x26515031,
391 /* XFER_MW_DMA_1 */ 0x26515033,
392 /* XFER_MW_DMA_0 */ 0x26515097,
393
394 /* XFER_PIO_4 */ 0x06515021,
395 /* XFER_PIO_3 */ 0x06515022,
396 /* XFER_PIO_2 */ 0x06515033,
397 /* XFER_PIO_1 */ 0x06915065,
398 /* XFER_PIO_0 */ 0x06d1508a
399 };
400
401 static u32 fifty_base_hpt37x[] = {
402 /* XFER_UDMA_6 */ 0x1a861842,
403 /* XFER_UDMA_5 */ 0x1a861842,
404 /* XFER_UDMA_4 */ 0x1aae1842,
405 /* XFER_UDMA_3 */ 0x1a8e1842,
406 /* XFER_UDMA_2 */ 0x1a0e1842,
407 /* XFER_UDMA_1 */ 0x1a161854,
408 /* XFER_UDMA_0 */ 0x1a1a18ea,
409
410 /* XFER_MW_DMA_2 */ 0x2a821842,
411 /* XFER_MW_DMA_1 */ 0x2a821854,
412 /* XFER_MW_DMA_0 */ 0x2a8218ea,
413
414 /* XFER_PIO_4 */ 0x0a821842,
415 /* XFER_PIO_3 */ 0x0a821843,
416 /* XFER_PIO_2 */ 0x0a821855,
417 /* XFER_PIO_1 */ 0x0ac218a8,
418 /* XFER_PIO_0 */ 0x0b02190c
419 };
420
421 static u32 sixty_six_base_hpt37x[] = {
422 /* XFER_UDMA_6 */ 0x1c86fe62,
423 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
424 /* XFER_UDMA_4 */ 0x1c8afe62,
425 /* XFER_UDMA_3 */ 0x1c8efe62,
426 /* XFER_UDMA_2 */ 0x1c92fe62,
427 /* XFER_UDMA_1 */ 0x1c9afe62,
428 /* XFER_UDMA_0 */ 0x1c82fe62,
429
430 /* XFER_MW_DMA_2 */ 0x2c82fe62,
431 /* XFER_MW_DMA_1 */ 0x2c82fe66,
432 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
433
434 /* XFER_PIO_4 */ 0x0c82fe62,
435 /* XFER_PIO_3 */ 0x0c82fe84,
436 /* XFER_PIO_2 */ 0x0c82fea6,
437 /* XFER_PIO_1 */ 0x0d02ff26,
438 /* XFER_PIO_0 */ 0x0d42ff7f
439 };
440 #endif
441
442 #define HPT366_DEBUG_DRIVE_INFO 0
443 #define HPT371_ALLOW_ATA133_6 1
444 #define HPT302_ALLOW_ATA133_6 1
445 #define HPT372_ALLOW_ATA133_6 1
446 #define HPT370_ALLOW_ATA100_5 0
447 #define HPT366_ALLOW_ATA66_4 1
448 #define HPT366_ALLOW_ATA66_3 1
449 #define HPT366_MAX_DEVS 8
450
451 /* Supported ATA clock frequencies */
452 enum ata_clock {
453 ATA_CLOCK_25MHZ,
454 ATA_CLOCK_33MHZ,
455 ATA_CLOCK_40MHZ,
456 ATA_CLOCK_50MHZ,
457 ATA_CLOCK_66MHZ,
458 NUM_ATA_CLOCKS
459 };
460
461 struct hpt_timings {
462 u32 pio_mask;
463 u32 dma_mask;
464 u32 ultra_mask;
465 u32 *clock_table[NUM_ATA_CLOCKS];
466 };
467
468 /*
469 * Hold all the HighPoint chip information in one place.
470 */
471
472 struct hpt_info {
473 char *chip_name; /* Chip name */
474 u8 chip_type; /* Chip type */
475 u8 udma_mask; /* Allowed UltraDMA modes mask. */
476 u8 dpll_clk; /* DPLL clock in MHz */
477 u8 pci_clk; /* PCI clock in MHz */
478 struct hpt_timings *timings; /* Chipset timing data */
479 u8 clock; /* ATA clock selected */
480 };
481
482 /* Supported HighPoint chips */
483 enum {
484 HPT36x,
485 HPT370,
486 HPT370A,
487 HPT374,
488 HPT372,
489 HPT372A,
490 HPT302,
491 HPT371,
492 HPT372N,
493 HPT302N,
494 HPT371N
495 };
496
497 static struct hpt_timings hpt36x_timings = {
498 .pio_mask = 0xc1f8ffff,
499 .dma_mask = 0x303800ff,
500 .ultra_mask = 0x30070000,
501 .clock_table = {
502 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
503 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
504 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
505 [ATA_CLOCK_50MHZ] = NULL,
506 [ATA_CLOCK_66MHZ] = NULL
507 }
508 };
509
510 static struct hpt_timings hpt37x_timings = {
511 .pio_mask = 0xcfc3ffff,
512 .dma_mask = 0x31c001ff,
513 .ultra_mask = 0x303c0000,
514 .clock_table = {
515 [ATA_CLOCK_25MHZ] = NULL,
516 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
517 [ATA_CLOCK_40MHZ] = NULL,
518 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
519 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
520 }
521 };
522
523 static const struct hpt_info hpt36x __devinitdata = {
524 .chip_name = "HPT36x",
525 .chip_type = HPT36x,
526 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
527 .dpll_clk = 0, /* no DPLL */
528 .timings = &hpt36x_timings
529 };
530
531 static const struct hpt_info hpt370 __devinitdata = {
532 .chip_name = "HPT370",
533 .chip_type = HPT370,
534 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
535 .dpll_clk = 48,
536 .timings = &hpt37x_timings
537 };
538
539 static const struct hpt_info hpt370a __devinitdata = {
540 .chip_name = "HPT370A",
541 .chip_type = HPT370A,
542 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
543 .dpll_clk = 48,
544 .timings = &hpt37x_timings
545 };
546
547 static const struct hpt_info hpt374 __devinitdata = {
548 .chip_name = "HPT374",
549 .chip_type = HPT374,
550 .udma_mask = ATA_UDMA5,
551 .dpll_clk = 48,
552 .timings = &hpt37x_timings
553 };
554
555 static const struct hpt_info hpt372 __devinitdata = {
556 .chip_name = "HPT372",
557 .chip_type = HPT372,
558 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
559 .dpll_clk = 55,
560 .timings = &hpt37x_timings
561 };
562
563 static const struct hpt_info hpt372a __devinitdata = {
564 .chip_name = "HPT372A",
565 .chip_type = HPT372A,
566 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
567 .dpll_clk = 66,
568 .timings = &hpt37x_timings
569 };
570
571 static const struct hpt_info hpt302 __devinitdata = {
572 .chip_name = "HPT302",
573 .chip_type = HPT302,
574 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
575 .dpll_clk = 66,
576 .timings = &hpt37x_timings
577 };
578
579 static const struct hpt_info hpt371 __devinitdata = {
580 .chip_name = "HPT371",
581 .chip_type = HPT371,
582 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
583 .dpll_clk = 66,
584 .timings = &hpt37x_timings
585 };
586
587 static const struct hpt_info hpt372n __devinitdata = {
588 .chip_name = "HPT372N",
589 .chip_type = HPT372N,
590 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
591 .dpll_clk = 77,
592 .timings = &hpt37x_timings
593 };
594
595 static const struct hpt_info hpt302n __devinitdata = {
596 .chip_name = "HPT302N",
597 .chip_type = HPT302N,
598 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
599 .dpll_clk = 77,
600 .timings = &hpt37x_timings
601 };
602
603 static const struct hpt_info hpt371n __devinitdata = {
604 .chip_name = "HPT371N",
605 .chip_type = HPT371N,
606 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
607 .dpll_clk = 77,
608 .timings = &hpt37x_timings
609 };
610
611 static int check_in_drive_list(ide_drive_t *drive, const char **list)
612 {
613 struct hd_driveid *id = drive->id;
614
615 while (*list)
616 if (!strcmp(*list++,id->model))
617 return 1;
618 return 0;
619 }
620
621 /*
622 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
623 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
624 */
625
626 static u8 hpt3xx_udma_filter(ide_drive_t *drive)
627 {
628 ide_hwif_t *hwif = HWIF(drive);
629 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
630 u8 mask = hwif->ultra_mask;
631
632 switch (info->chip_type) {
633 case HPT36x:
634 if (!HPT366_ALLOW_ATA66_4 ||
635 check_in_drive_list(drive, bad_ata66_4))
636 mask = ATA_UDMA3;
637
638 if (!HPT366_ALLOW_ATA66_3 ||
639 check_in_drive_list(drive, bad_ata66_3))
640 mask = ATA_UDMA2;
641 break;
642 case HPT370:
643 if (!HPT370_ALLOW_ATA100_5 ||
644 check_in_drive_list(drive, bad_ata100_5))
645 mask = ATA_UDMA4;
646 break;
647 case HPT370A:
648 if (!HPT370_ALLOW_ATA100_5 ||
649 check_in_drive_list(drive, bad_ata100_5))
650 return ATA_UDMA4;
651 case HPT372 :
652 case HPT372A:
653 case HPT372N:
654 case HPT374 :
655 if (ide_dev_is_sata(drive->id))
656 mask &= ~0x0e;
657 /* Fall thru */
658 default:
659 return mask;
660 }
661
662 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
663 }
664
665 static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
666 {
667 ide_hwif_t *hwif = HWIF(drive);
668 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
669
670 switch (info->chip_type) {
671 case HPT372 :
672 case HPT372A:
673 case HPT372N:
674 case HPT374 :
675 if (ide_dev_is_sata(drive->id))
676 return 0x00;
677 /* Fall thru */
678 default:
679 return 0x07;
680 }
681 }
682
683 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
684 {
685 int i;
686
687 /*
688 * Lookup the transfer mode table to get the index into
689 * the timing table.
690 *
691 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
692 */
693 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
694 if (xfer_speeds[i] == speed)
695 break;
696
697 return info->timings->clock_table[info->clock][i];
698 }
699
700 static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
701 {
702 struct pci_dev *dev = HWIF(drive)->pci_dev;
703 struct hpt_info *info = pci_get_drvdata(dev);
704 struct hpt_timings *t = info->timings;
705 u8 itr_addr = 0x40 + (drive->dn * 4);
706 u32 old_itr = 0;
707 u32 new_itr = get_speed_setting(speed, info);
708 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
709 (speed < XFER_UDMA_0 ? t->dma_mask :
710 t->ultra_mask);
711
712 pci_read_config_dword(dev, itr_addr, &old_itr);
713 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
714 /*
715 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
716 * to avoid problems handling I/O errors later
717 */
718 new_itr &= ~0xc0000000;
719
720 pci_write_config_dword(dev, itr_addr, new_itr);
721 }
722
723 static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
724 {
725 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
726 }
727
728 static int hpt3xx_quirkproc(ide_drive_t *drive)
729 {
730 struct hd_driveid *id = drive->id;
731 const char **list = quirk_drives;
732
733 while (*list)
734 if (strstr(id->model, *list++))
735 return 1;
736 return 0;
737 }
738
739 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
740 {
741 ide_hwif_t *hwif = HWIF(drive);
742 struct pci_dev *dev = hwif->pci_dev;
743 struct hpt_info *info = pci_get_drvdata(dev);
744
745 if (drive->quirk_list) {
746 if (info->chip_type >= HPT370) {
747 u8 scr1 = 0;
748
749 pci_read_config_byte(dev, 0x5a, &scr1);
750 if (((scr1 & 0x10) >> 4) != mask) {
751 if (mask)
752 scr1 |= 0x10;
753 else
754 scr1 &= ~0x10;
755 pci_write_config_byte(dev, 0x5a, scr1);
756 }
757 } else {
758 if (mask)
759 disable_irq(hwif->irq);
760 else
761 enable_irq (hwif->irq);
762 }
763 } else
764 outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
765 IDE_CONTROL_REG);
766 }
767
768 /*
769 * This is specific to the HPT366 UDMA chipset
770 * by HighPoint|Triones Technologies, Inc.
771 */
772 static void hpt366_dma_lost_irq(ide_drive_t *drive)
773 {
774 struct pci_dev *dev = HWIF(drive)->pci_dev;
775 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
776
777 pci_read_config_byte(dev, 0x50, &mcr1);
778 pci_read_config_byte(dev, 0x52, &mcr3);
779 pci_read_config_byte(dev, 0x5a, &scr1);
780 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
781 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
782 if (scr1 & 0x10)
783 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
784 ide_dma_lost_irq(drive);
785 }
786
787 static void hpt370_clear_engine(ide_drive_t *drive)
788 {
789 ide_hwif_t *hwif = HWIF(drive);
790
791 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
792 udelay(10);
793 }
794
795 static void hpt370_irq_timeout(ide_drive_t *drive)
796 {
797 ide_hwif_t *hwif = HWIF(drive);
798 u16 bfifo = 0;
799 u8 dma_cmd;
800
801 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
802 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
803
804 /* get DMA command mode */
805 dma_cmd = inb(hwif->dma_command);
806 /* stop DMA */
807 outb(dma_cmd & ~0x1, hwif->dma_command);
808 hpt370_clear_engine(drive);
809 }
810
811 static void hpt370_ide_dma_start(ide_drive_t *drive)
812 {
813 #ifdef HPT_RESET_STATE_ENGINE
814 hpt370_clear_engine(drive);
815 #endif
816 ide_dma_start(drive);
817 }
818
819 static int hpt370_ide_dma_end(ide_drive_t *drive)
820 {
821 ide_hwif_t *hwif = HWIF(drive);
822 u8 dma_stat = inb(hwif->dma_status);
823
824 if (dma_stat & 0x01) {
825 /* wait a little */
826 udelay(20);
827 dma_stat = inb(hwif->dma_status);
828 if (dma_stat & 0x01)
829 hpt370_irq_timeout(drive);
830 }
831 return __ide_dma_end(drive);
832 }
833
834 static void hpt370_dma_timeout(ide_drive_t *drive)
835 {
836 hpt370_irq_timeout(drive);
837 ide_dma_timeout(drive);
838 }
839
840 /* returns 1 if DMA IRQ issued, 0 otherwise */
841 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
842 {
843 ide_hwif_t *hwif = HWIF(drive);
844 u16 bfifo = 0;
845 u8 dma_stat;
846
847 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
848 if (bfifo & 0x1FF) {
849 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
850 return 0;
851 }
852
853 dma_stat = inb(hwif->dma_status);
854 /* return 1 if INTR asserted */
855 if (dma_stat & 4)
856 return 1;
857
858 if (!drive->waiting_for_dma)
859 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
860 drive->name, __FUNCTION__);
861 return 0;
862 }
863
864 static int hpt374_ide_dma_end(ide_drive_t *drive)
865 {
866 ide_hwif_t *hwif = HWIF(drive);
867 struct pci_dev *dev = hwif->pci_dev;
868 u8 mcr = 0, mcr_addr = hwif->select_data;
869 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
870
871 pci_read_config_byte(dev, 0x6a, &bwsr);
872 pci_read_config_byte(dev, mcr_addr, &mcr);
873 if (bwsr & mask)
874 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
875 return __ide_dma_end(drive);
876 }
877
878 /**
879 * hpt3xxn_set_clock - perform clock switching dance
880 * @hwif: hwif to switch
881 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
882 *
883 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
884 */
885
886 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
887 {
888 unsigned long base = hwif->extra_base;
889 u8 scr2 = inb(base + 0x6b);
890
891 if ((scr2 & 0x7f) == mode)
892 return;
893
894 /* Tristate the bus */
895 outb(0x80, base + 0x63);
896 outb(0x80, base + 0x67);
897
898 /* Switch clock and reset channels */
899 outb(mode, base + 0x6b);
900 outb(0xc0, base + 0x69);
901
902 /*
903 * Reset the state machines.
904 * NOTE: avoid accidentally enabling the disabled channels.
905 */
906 outb(inb(base + 0x60) | 0x32, base + 0x60);
907 outb(inb(base + 0x64) | 0x32, base + 0x64);
908
909 /* Complete reset */
910 outb(0x00, base + 0x69);
911
912 /* Reconnect channels to bus */
913 outb(0x00, base + 0x63);
914 outb(0x00, base + 0x67);
915 }
916
917 /**
918 * hpt3xxn_rw_disk - prepare for I/O
919 * @drive: drive for command
920 * @rq: block request structure
921 *
922 * This is called when a disk I/O is issued to HPT3xxN.
923 * We need it because of the clock switching.
924 */
925
926 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
927 {
928 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
929 }
930
931 /*
932 * Set/get power state for a drive.
933 * NOTE: affects both drives on each channel.
934 *
935 * When we turn the power back on, we need to re-initialize things.
936 */
937 #define TRISTATE_BIT 0x8000
938
939 static int hpt3xx_busproc(ide_drive_t *drive, int state)
940 {
941 ide_hwif_t *hwif = HWIF(drive);
942 struct pci_dev *dev = hwif->pci_dev;
943 u8 mcr_addr = hwif->select_data + 2;
944 u8 resetmask = hwif->channel ? 0x80 : 0x40;
945 u8 bsr2 = 0;
946 u16 mcr = 0;
947
948 hwif->bus_state = state;
949
950 /* Grab the status. */
951 pci_read_config_word(dev, mcr_addr, &mcr);
952 pci_read_config_byte(dev, 0x59, &bsr2);
953
954 /*
955 * Set the state. We don't set it if we don't need to do so.
956 * Make sure that the drive knows that it has failed if it's off.
957 */
958 switch (state) {
959 case BUSSTATE_ON:
960 if (!(bsr2 & resetmask))
961 return 0;
962 hwif->drives[0].failures = hwif->drives[1].failures = 0;
963
964 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
965 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
966 return 0;
967 case BUSSTATE_OFF:
968 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
969 return 0;
970 mcr &= ~TRISTATE_BIT;
971 break;
972 case BUSSTATE_TRISTATE:
973 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
974 return 0;
975 mcr |= TRISTATE_BIT;
976 break;
977 default:
978 return -EINVAL;
979 }
980
981 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
982 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
983
984 pci_write_config_word(dev, mcr_addr, mcr);
985 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
986 return 0;
987 }
988
989 /**
990 * hpt37x_calibrate_dpll - calibrate the DPLL
991 * @dev: PCI device
992 *
993 * Perform a calibration cycle on the DPLL.
994 * Returns 1 if this succeeds
995 */
996 static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
997 {
998 u32 dpll = (f_high << 16) | f_low | 0x100;
999 u8 scr2;
1000 int i;
1001
1002 pci_write_config_dword(dev, 0x5c, dpll);
1003
1004 /* Wait for oscillator ready */
1005 for(i = 0; i < 0x5000; ++i) {
1006 udelay(50);
1007 pci_read_config_byte(dev, 0x5b, &scr2);
1008 if (scr2 & 0x80)
1009 break;
1010 }
1011 /* See if it stays ready (we'll just bail out if it's not yet) */
1012 for(i = 0; i < 0x1000; ++i) {
1013 pci_read_config_byte(dev, 0x5b, &scr2);
1014 /* DPLL destabilized? */
1015 if(!(scr2 & 0x80))
1016 return 0;
1017 }
1018 /* Turn off tuning, we have the DPLL set */
1019 pci_read_config_dword (dev, 0x5c, &dpll);
1020 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
1021 return 1;
1022 }
1023
1024 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1025 {
1026 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
1027 unsigned long io_base = pci_resource_start(dev, 4);
1028 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
1029 u8 chip_type;
1030 enum ata_clock clock;
1031
1032 if (info == NULL) {
1033 printk(KERN_ERR "%s: out of memory!\n", name);
1034 return -ENOMEM;
1035 }
1036
1037 /*
1038 * Copy everything from a static "template" structure
1039 * to just allocated per-chip hpt_info structure.
1040 */
1041 memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info));
1042 chip_type = info->chip_type;
1043
1044 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1045 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1046 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1047 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1048
1049 /*
1050 * First, try to estimate the PCI clock frequency...
1051 */
1052 if (chip_type >= HPT370) {
1053 u8 scr1 = 0;
1054 u16 f_cnt = 0;
1055 u32 temp = 0;
1056
1057 /* Interrupt force enable. */
1058 pci_read_config_byte(dev, 0x5a, &scr1);
1059 if (scr1 & 0x10)
1060 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1061
1062 /*
1063 * HighPoint does this for HPT372A.
1064 * NOTE: This register is only writeable via I/O space.
1065 */
1066 if (chip_type == HPT372A)
1067 outb(0x0e, io_base + 0x9c);
1068
1069 /*
1070 * Default to PCI clock. Make sure MA15/16 are set to output
1071 * to prevent drives having problems with 40-pin cables.
1072 */
1073 pci_write_config_byte(dev, 0x5b, 0x23);
1074
1075 /*
1076 * We'll have to read f_CNT value in order to determine
1077 * the PCI clock frequency according to the following ratio:
1078 *
1079 * f_CNT = Fpci * 192 / Fdpll
1080 *
1081 * First try reading the register in which the HighPoint BIOS
1082 * saves f_CNT value before reprogramming the DPLL from its
1083 * default setting (which differs for the various chips).
1084 *
1085 * NOTE: This register is only accessible via I/O space;
1086 * HPT374 BIOS only saves it for the function 0, so we have to
1087 * always read it from there -- no need to check the result of
1088 * pci_get_slot() for the function 0 as the whole device has
1089 * been already "pinned" (via function 1) in init_setup_hpt374()
1090 */
1091 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1092 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1093 dev->devfn - 1);
1094 unsigned long io_base = pci_resource_start(dev1, 4);
1095
1096 temp = inl(io_base + 0x90);
1097 pci_dev_put(dev1);
1098 } else
1099 temp = inl(io_base + 0x90);
1100
1101 /*
1102 * In case the signature check fails, we'll have to
1103 * resort to reading the f_CNT register itself in hopes
1104 * that nobody has touched the DPLL yet...
1105 */
1106 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1107 int i;
1108
1109 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1110 name);
1111
1112 /* Calculate the average value of f_CNT. */
1113 for (temp = i = 0; i < 128; i++) {
1114 pci_read_config_word(dev, 0x78, &f_cnt);
1115 temp += f_cnt & 0x1ff;
1116 mdelay(1);
1117 }
1118 f_cnt = temp / 128;
1119 } else
1120 f_cnt = temp & 0x1ff;
1121
1122 dpll_clk = info->dpll_clk;
1123 pci_clk = (f_cnt * dpll_clk) / 192;
1124
1125 /* Clamp PCI clock to bands. */
1126 if (pci_clk < 40)
1127 pci_clk = 33;
1128 else if(pci_clk < 45)
1129 pci_clk = 40;
1130 else if(pci_clk < 55)
1131 pci_clk = 50;
1132 else
1133 pci_clk = 66;
1134
1135 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1136 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1137 } else {
1138 u32 itr1 = 0;
1139
1140 pci_read_config_dword(dev, 0x40, &itr1);
1141
1142 /* Detect PCI clock by looking at cmd_high_time. */
1143 switch((itr1 >> 8) & 0x07) {
1144 case 0x09:
1145 pci_clk = 40;
1146 break;
1147 case 0x05:
1148 pci_clk = 25;
1149 break;
1150 case 0x07:
1151 default:
1152 pci_clk = 33;
1153 break;
1154 }
1155 }
1156
1157 /* Let's assume we'll use PCI clock for the ATA clock... */
1158 switch (pci_clk) {
1159 case 25:
1160 clock = ATA_CLOCK_25MHZ;
1161 break;
1162 case 33:
1163 default:
1164 clock = ATA_CLOCK_33MHZ;
1165 break;
1166 case 40:
1167 clock = ATA_CLOCK_40MHZ;
1168 break;
1169 case 50:
1170 clock = ATA_CLOCK_50MHZ;
1171 break;
1172 case 66:
1173 clock = ATA_CLOCK_66MHZ;
1174 break;
1175 }
1176
1177 /*
1178 * Only try the DPLL if we don't have a table for the PCI clock that
1179 * we are running at for HPT370/A, always use it for anything newer...
1180 *
1181 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1182 * We also don't like using the DPLL because this causes glitches
1183 * on PRST-/SRST- when the state engine gets reset...
1184 */
1185 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
1186 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1187 int adjust;
1188
1189 /*
1190 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1191 * supported/enabled, use 50 MHz DPLL clock otherwise...
1192 */
1193 if (info->udma_mask == ATA_UDMA6) {
1194 dpll_clk = 66;
1195 clock = ATA_CLOCK_66MHZ;
1196 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1197 dpll_clk = 50;
1198 clock = ATA_CLOCK_50MHZ;
1199 }
1200
1201 if (info->timings->clock_table[clock] == NULL) {
1202 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1203 kfree(info);
1204 return -EIO;
1205 }
1206
1207 /* Select the DPLL clock. */
1208 pci_write_config_byte(dev, 0x5b, 0x21);
1209
1210 /*
1211 * Adjust the DPLL based upon PCI clock, enable it,
1212 * and wait for stabilization...
1213 */
1214 f_low = (pci_clk * 48) / dpll_clk;
1215
1216 for (adjust = 0; adjust < 8; adjust++) {
1217 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1218 break;
1219
1220 /*
1221 * See if it'll settle at a fractionally different clock
1222 */
1223 if (adjust & 1)
1224 f_low -= adjust >> 1;
1225 else
1226 f_low += adjust >> 1;
1227 }
1228 if (adjust == 8) {
1229 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1230 kfree(info);
1231 return -EIO;
1232 }
1233
1234 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1235 } else {
1236 /* Mark the fact that we're not using the DPLL. */
1237 dpll_clk = 0;
1238
1239 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1240 }
1241
1242 /* Store the clock frequencies. */
1243 info->dpll_clk = dpll_clk;
1244 info->pci_clk = pci_clk;
1245 info->clock = clock;
1246
1247 /* Point to this chip's own instance of the hpt_info structure. */
1248 pci_set_drvdata(dev, info);
1249
1250 if (chip_type >= HPT370) {
1251 u8 mcr1, mcr4;
1252
1253 /*
1254 * Reset the state engines.
1255 * NOTE: Avoid accidentally enabling the disabled channels.
1256 */
1257 pci_read_config_byte (dev, 0x50, &mcr1);
1258 pci_read_config_byte (dev, 0x54, &mcr4);
1259 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1260 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1261 udelay(100);
1262 }
1263
1264 /*
1265 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1266 * the MISC. register to stretch the UltraDMA Tss timing.
1267 * NOTE: This register is only writeable via I/O space.
1268 */
1269 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1270
1271 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1272
1273 return dev->irq;
1274 }
1275
1276 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1277 {
1278 struct pci_dev *dev = hwif->pci_dev;
1279 struct hpt_info *info = pci_get_drvdata(dev);
1280 int serialize = HPT_SERIALIZE_IO;
1281 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1282 u8 chip_type = info->chip_type;
1283 u8 new_mcr, old_mcr = 0;
1284
1285 /* Cache the channel's MISC. control registers' offset */
1286 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1287
1288 hwif->set_pio_mode = &hpt3xx_set_pio_mode;
1289 hwif->set_dma_mode = &hpt3xx_set_mode;
1290
1291 hwif->quirkproc = &hpt3xx_quirkproc;
1292 hwif->maskproc = &hpt3xx_maskproc;
1293 hwif->busproc = &hpt3xx_busproc;
1294
1295 hwif->udma_filter = &hpt3xx_udma_filter;
1296 hwif->mdma_filter = &hpt3xx_mdma_filter;
1297
1298 /*
1299 * HPT3xxN chips have some complications:
1300 *
1301 * - on 33 MHz PCI we must clock switch
1302 * - on 66 MHz PCI we must NOT use the PCI clock
1303 */
1304 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1305 /*
1306 * Clock is shared between the channels,
1307 * so we'll have to serialize them... :-(
1308 */
1309 serialize = 1;
1310 hwif->rw_disk = &hpt3xxn_rw_disk;
1311 }
1312
1313 /* Serialize access to this device if needed */
1314 if (serialize && hwif->mate)
1315 hwif->serialized = hwif->mate->serialized = 1;
1316
1317 /*
1318 * Disable the "fast interrupt" prediction. Don't hold off
1319 * on interrupts. (== 0x01 despite what the docs say)
1320 */
1321 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1322
1323 if (info->chip_type >= HPT374)
1324 new_mcr = old_mcr & ~0x07;
1325 else if (info->chip_type >= HPT370) {
1326 new_mcr = old_mcr;
1327 new_mcr &= ~0x02;
1328
1329 #ifdef HPT_DELAY_INTERRUPT
1330 new_mcr &= ~0x01;
1331 #else
1332 new_mcr |= 0x01;
1333 #endif
1334 } else /* HPT366 and HPT368 */
1335 new_mcr = old_mcr & ~0x80;
1336
1337 if (new_mcr != old_mcr)
1338 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1339
1340 if (hwif->dma_base == 0)
1341 return;
1342
1343 /*
1344 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1345 * address lines to access an external EEPROM. To read valid
1346 * cable detect state the pins must be enabled as inputs.
1347 */
1348 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1349 /*
1350 * HPT374 PCI function 1
1351 * - set bit 15 of reg 0x52 to enable TCBLID as input
1352 * - set bit 15 of reg 0x56 to enable FCBLID as input
1353 */
1354 u8 mcr_addr = hwif->select_data + 2;
1355 u16 mcr;
1356
1357 pci_read_config_word (dev, mcr_addr, &mcr);
1358 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1359 /* now read cable id register */
1360 pci_read_config_byte (dev, 0x5a, &scr1);
1361 pci_write_config_word(dev, mcr_addr, mcr);
1362 } else if (chip_type >= HPT370) {
1363 /*
1364 * HPT370/372 and 374 pcifn 0
1365 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1366 */
1367 u8 scr2 = 0;
1368
1369 pci_read_config_byte (dev, 0x5b, &scr2);
1370 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1371 /* now read cable id register */
1372 pci_read_config_byte (dev, 0x5a, &scr1);
1373 pci_write_config_byte(dev, 0x5b, scr2);
1374 } else
1375 pci_read_config_byte (dev, 0x5a, &scr1);
1376
1377 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
1378 hwif->cbl = (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1379
1380 if (chip_type >= HPT374) {
1381 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1382 hwif->ide_dma_end = &hpt374_ide_dma_end;
1383 } else if (chip_type >= HPT370) {
1384 hwif->dma_start = &hpt370_ide_dma_start;
1385 hwif->ide_dma_end = &hpt370_ide_dma_end;
1386 hwif->dma_timeout = &hpt370_dma_timeout;
1387 } else
1388 hwif->dma_lost_irq = &hpt366_dma_lost_irq;
1389 }
1390
1391 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1392 {
1393 struct pci_dev *dev = hwif->pci_dev;
1394 u8 masterdma = 0, slavedma = 0;
1395 u8 dma_new = 0, dma_old = 0;
1396 unsigned long flags;
1397
1398 dma_old = inb(dmabase + 2);
1399
1400 local_irq_save(flags);
1401
1402 dma_new = dma_old;
1403 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1404 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1405
1406 if (masterdma & 0x30) dma_new |= 0x20;
1407 if ( slavedma & 0x30) dma_new |= 0x40;
1408 if (dma_new != dma_old)
1409 outb(dma_new, dmabase + 2);
1410
1411 local_irq_restore(flags);
1412
1413 ide_setup_dma(hwif, dmabase, 8);
1414 }
1415
1416 static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
1417 {
1418 if (dev2->irq != dev->irq) {
1419 /* FIXME: we need a core pci_set_interrupt() */
1420 dev2->irq = dev->irq;
1421 printk(KERN_INFO "HPT374: PCI config space interrupt fixed\n");
1422 }
1423 }
1424
1425 static void __devinit hpt371_init(struct pci_dev *dev)
1426 {
1427 u8 mcr1 = 0;
1428
1429 /*
1430 * HPT371 chips physically have only one channel, the secondary one,
1431 * but the primary channel registers do exist! Go figure...
1432 * So, we manually disable the non-existing channel here
1433 * (if the BIOS hasn't done this already).
1434 */
1435 pci_read_config_byte(dev, 0x50, &mcr1);
1436 if (mcr1 & 0x04)
1437 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1438 }
1439
1440 static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
1441 {
1442 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1443
1444 /*
1445 * Now we'll have to force both channels enabled if
1446 * at least one of them has been enabled by BIOS...
1447 */
1448 pci_read_config_byte(dev, 0x50, &mcr1);
1449 if (mcr1 & 0x30)
1450 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1451
1452 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1453 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1454
1455 if (pin1 != pin2 && dev->irq == dev2->irq) {
1456 printk(KERN_INFO "HPT36x: onboard version of chipset, "
1457 "pin1=%d pin2=%d\n", pin1, pin2);
1458 return 1;
1459 }
1460
1461 return 0;
1462 }
1463
1464 #define IDE_HFLAGS_HPT3XX \
1465 (IDE_HFLAG_NO_ATAPI_DMA | \
1466 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
1467 IDE_HFLAG_OFF_BOARD)
1468
1469 static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1470 { /* 0 */
1471 .name = "HPT36x",
1472 .init_chipset = init_chipset_hpt366,
1473 .init_hwif = init_hwif_hpt366,
1474 .init_dma = init_dma_hpt366,
1475 /*
1476 * HPT36x chips have one channel per function and have
1477 * both channel enable bits located differently and visible
1478 * to both functions -- really stupid design decision... :-(
1479 * Bit 4 is for the primary channel, bit 5 for the secondary.
1480 */
1481 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1482 .extra = 240,
1483 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
1484 .pio_mask = ATA_PIO4,
1485 .mwdma_mask = ATA_MWDMA2,
1486 },{ /* 1 */
1487 .name = "HPT372A",
1488 .init_chipset = init_chipset_hpt366,
1489 .init_hwif = init_hwif_hpt366,
1490 .init_dma = init_dma_hpt366,
1491 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1492 .extra = 240,
1493 .host_flags = IDE_HFLAGS_HPT3XX,
1494 .pio_mask = ATA_PIO4,
1495 .mwdma_mask = ATA_MWDMA2,
1496 },{ /* 2 */
1497 .name = "HPT302",
1498 .init_chipset = init_chipset_hpt366,
1499 .init_hwif = init_hwif_hpt366,
1500 .init_dma = init_dma_hpt366,
1501 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1502 .extra = 240,
1503 .host_flags = IDE_HFLAGS_HPT3XX,
1504 .pio_mask = ATA_PIO4,
1505 .mwdma_mask = ATA_MWDMA2,
1506 },{ /* 3 */
1507 .name = "HPT371",
1508 .init_chipset = init_chipset_hpt366,
1509 .init_hwif = init_hwif_hpt366,
1510 .init_dma = init_dma_hpt366,
1511 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1512 .extra = 240,
1513 .host_flags = IDE_HFLAGS_HPT3XX,
1514 .pio_mask = ATA_PIO4,
1515 .mwdma_mask = ATA_MWDMA2,
1516 },{ /* 4 */
1517 .name = "HPT374",
1518 .init_chipset = init_chipset_hpt366,
1519 .init_hwif = init_hwif_hpt366,
1520 .init_dma = init_dma_hpt366,
1521 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1522 .udma_mask = ATA_UDMA5,
1523 .extra = 240,
1524 .host_flags = IDE_HFLAGS_HPT3XX,
1525 .pio_mask = ATA_PIO4,
1526 .mwdma_mask = ATA_MWDMA2,
1527 },{ /* 5 */
1528 .name = "HPT372N",
1529 .init_chipset = init_chipset_hpt366,
1530 .init_hwif = init_hwif_hpt366,
1531 .init_dma = init_dma_hpt366,
1532 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1533 .extra = 240,
1534 .host_flags = IDE_HFLAGS_HPT3XX,
1535 .pio_mask = ATA_PIO4,
1536 .mwdma_mask = ATA_MWDMA2,
1537 }
1538 };
1539
1540 /**
1541 * hpt366_init_one - called when an HPT366 is found
1542 * @dev: the hpt366 device
1543 * @id: the matching pci id
1544 *
1545 * Called when the PCI registration layer (or the IDE initialization)
1546 * finds a device matching our IDE device tables.
1547 */
1548 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1549 {
1550 const struct hpt_info *info = NULL;
1551 struct pci_dev *dev2 = NULL;
1552 struct ide_port_info d;
1553 u8 idx = id->driver_data;
1554 u8 rev = dev->revision;
1555
1556 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1557 return -ENODEV;
1558
1559 switch (idx) {
1560 case 0:
1561 if (rev < 3)
1562 info = &hpt36x;
1563 else {
1564 static const struct hpt_info *hpt37x_info[] =
1565 { &hpt370, &hpt370a, &hpt372, &hpt372n };
1566
1567 info = hpt37x_info[min_t(u8, rev, 6) - 3];
1568 idx++;
1569 }
1570 break;
1571 case 1:
1572 info = (rev > 1) ? &hpt372n : &hpt372a;
1573 break;
1574 case 2:
1575 info = (rev > 1) ? &hpt302n : &hpt302;
1576 break;
1577 case 3:
1578 hpt371_init(dev);
1579 info = (rev > 1) ? &hpt371n : &hpt371;
1580 break;
1581 case 4:
1582 info = &hpt374;
1583 break;
1584 case 5:
1585 info = &hpt372n;
1586 break;
1587 }
1588
1589 d = hpt366_chipsets[idx];
1590
1591 d.name = info->chip_name;
1592 d.udma_mask = info->udma_mask;
1593
1594 pci_set_drvdata(dev, (void *)info);
1595
1596 if (info == &hpt36x || info == &hpt374)
1597 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1598
1599 if (dev2) {
1600 int ret;
1601
1602 pci_set_drvdata(dev2, (void *)info);
1603
1604 if (info == &hpt374)
1605 hpt374_init(dev, dev2);
1606 else {
1607 if (hpt36x_init(dev, dev2))
1608 d.host_flags |= IDE_HFLAG_BOOTABLE;
1609 }
1610
1611 ret = ide_setup_pci_devices(dev, dev2, &d);
1612 if (ret < 0)
1613 pci_dev_put(dev2);
1614 return ret;
1615 }
1616
1617 return ide_setup_pci_device(dev, &d);
1618 }
1619
1620 static const struct pci_device_id hpt366_pci_tbl[] = {
1621 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1622 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1623 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1624 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1625 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1626 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
1627 { 0, },
1628 };
1629 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1630
1631 static struct pci_driver driver = {
1632 .name = "HPT366_IDE",
1633 .id_table = hpt366_pci_tbl,
1634 .probe = hpt366_init_one,
1635 };
1636
1637 static int __init hpt366_ide_init(void)
1638 {
1639 return ide_pci_register_driver(&driver);
1640 }
1641
1642 module_init(hpt366_ide_init);
1643
1644 MODULE_AUTHOR("Andre Hedrick");
1645 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1646 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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