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ide: use PCI_VDEVICE() macro
[deliverable/linux.git] / drivers / ide / pci / hpt366.c
1 /*
2 * linux/drivers/ide/pci/hpt366.c Version 1.14 Oct 1, 2007
3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
8 *
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
13 *
14 *
15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
20 *
21 * Note that final HPT370 support was done by force extraction of GPL.
22 *
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
37 *
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
43 *
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
46 *
47 * On hpt366:
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
51 *
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
55 * keeping me sane.
56 * Alan Cox <alan@redhat.com>
57 *
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
64 * does not allow for this speed anyway
65 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
66 * their primary channel is kind of virtual, it isn't tied to any pins)
67 * - fix/remove bad/unused timing tables and use one set of tables for the whole
68 * HPT37x chip family; save space by introducing the separate transfer mode
69 * table in which the mode lookup is done
70 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
71 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
72 * read it only from the function 0 of HPT374 chips
73 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
74 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
75 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
76 * they tamper with its fields
77 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
78 * since they may tamper with its fields
79 * - prefix the driver startup messages with the real chip name
80 * - claim the extra 240 bytes of I/O space for all chips
81 * - optimize the UltraDMA filtering and the drive list lookup code
82 * - use pci_get_slot() to get to the function 1 of HPT36x/374
83 * - cache offset of the channel's misc. control registers (MCRs) being used
84 * throughout the driver
85 * - only touch the relevant MCR when detecting the cable type on HPT374's
86 * function 1
87 * - rename all the register related variables consistently
88 * - move all the interrupt twiddling code from the speedproc handlers into
89 * init_hwif_hpt366(), also grouping all the DMA related code together there
90 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
91 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
92 * when setting an UltraDMA mode
93 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
94 * the best possible one
95 * - clean up DMA timeout handling for HPT370
96 * - switch to using the enumeration type to differ between the numerous chip
97 * variants, matching PCI device/revision ID with the chip type early, at the
98 * init_setup stage
99 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
100 * stop duplicating it for each channel by storing the pointer in the pci_dev
101 * structure: first, at the init_setup stage, point it to a static "template"
102 * with only the chip type and its specific base DPLL frequency, the highest
103 * UltraDMA mode, and the chip settings table pointer filled, then, at the
104 * init_chipset stage, allocate per-chip instance and fill it with the rest
105 * of the necessary information
106 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
107 * switch to calculating PCI clock frequency based on the chip's base DPLL
108 * frequency
109 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
110 * anything newer than HPT370/A (except HPT374 that is not capable of this
111 * mode according to the manual)
112 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
113 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
114 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
115 * the register setting lists into the table indexed by the clock selected
116 * - set the correct hwif->ultra_mask for each individual chip
117 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
118 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
119 */
120
121 #include <linux/types.h>
122 #include <linux/module.h>
123 #include <linux/kernel.h>
124 #include <linux/delay.h>
125 #include <linux/timer.h>
126 #include <linux/mm.h>
127 #include <linux/ioport.h>
128 #include <linux/blkdev.h>
129 #include <linux/hdreg.h>
130
131 #include <linux/interrupt.h>
132 #include <linux/pci.h>
133 #include <linux/init.h>
134 #include <linux/ide.h>
135
136 #include <asm/uaccess.h>
137 #include <asm/io.h>
138 #include <asm/irq.h>
139
140 /* various tuning parameters */
141 #define HPT_RESET_STATE_ENGINE
142 #undef HPT_DELAY_INTERRUPT
143 #define HPT_SERIALIZE_IO 0
144
145 static const char *quirk_drives[] = {
146 "QUANTUM FIREBALLlct08 08",
147 "QUANTUM FIREBALLP KA6.4",
148 "QUANTUM FIREBALLP LM20.4",
149 "QUANTUM FIREBALLP LM20.5",
150 NULL
151 };
152
153 static const char *bad_ata100_5[] = {
154 "IBM-DTLA-307075",
155 "IBM-DTLA-307060",
156 "IBM-DTLA-307045",
157 "IBM-DTLA-307030",
158 "IBM-DTLA-307020",
159 "IBM-DTLA-307015",
160 "IBM-DTLA-305040",
161 "IBM-DTLA-305030",
162 "IBM-DTLA-305020",
163 "IC35L010AVER07-0",
164 "IC35L020AVER07-0",
165 "IC35L030AVER07-0",
166 "IC35L040AVER07-0",
167 "IC35L060AVER07-0",
168 "WDC AC310200R",
169 NULL
170 };
171
172 static const char *bad_ata66_4[] = {
173 "IBM-DTLA-307075",
174 "IBM-DTLA-307060",
175 "IBM-DTLA-307045",
176 "IBM-DTLA-307030",
177 "IBM-DTLA-307020",
178 "IBM-DTLA-307015",
179 "IBM-DTLA-305040",
180 "IBM-DTLA-305030",
181 "IBM-DTLA-305020",
182 "IC35L010AVER07-0",
183 "IC35L020AVER07-0",
184 "IC35L030AVER07-0",
185 "IC35L040AVER07-0",
186 "IC35L060AVER07-0",
187 "WDC AC310200R",
188 "MAXTOR STM3320620A",
189 NULL
190 };
191
192 static const char *bad_ata66_3[] = {
193 "WDC AC310200R",
194 NULL
195 };
196
197 static const char *bad_ata33[] = {
198 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
199 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
200 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
201 "Maxtor 90510D4",
202 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
203 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
204 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
205 NULL
206 };
207
208 static u8 xfer_speeds[] = {
209 XFER_UDMA_6,
210 XFER_UDMA_5,
211 XFER_UDMA_4,
212 XFER_UDMA_3,
213 XFER_UDMA_2,
214 XFER_UDMA_1,
215 XFER_UDMA_0,
216
217 XFER_MW_DMA_2,
218 XFER_MW_DMA_1,
219 XFER_MW_DMA_0,
220
221 XFER_PIO_4,
222 XFER_PIO_3,
223 XFER_PIO_2,
224 XFER_PIO_1,
225 XFER_PIO_0
226 };
227
228 /* Key for bus clock timings
229 * 36x 37x
230 * bits bits
231 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
232 * cycles = value + 1
233 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
234 * cycles = value + 1
235 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
236 * register access.
237 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
238 * register access.
239 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
240 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
241 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
242 * MW DMA xfer.
243 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
244 * task file register access.
245 * 28 28 UDMA enable.
246 * 29 29 DMA enable.
247 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
248 * PIO xfer.
249 * 31 31 FIFO enable.
250 */
251
252 static u32 forty_base_hpt36x[] = {
253 /* XFER_UDMA_6 */ 0x900fd943,
254 /* XFER_UDMA_5 */ 0x900fd943,
255 /* XFER_UDMA_4 */ 0x900fd943,
256 /* XFER_UDMA_3 */ 0x900ad943,
257 /* XFER_UDMA_2 */ 0x900bd943,
258 /* XFER_UDMA_1 */ 0x9008d943,
259 /* XFER_UDMA_0 */ 0x9008d943,
260
261 /* XFER_MW_DMA_2 */ 0xa008d943,
262 /* XFER_MW_DMA_1 */ 0xa010d955,
263 /* XFER_MW_DMA_0 */ 0xa010d9fc,
264
265 /* XFER_PIO_4 */ 0xc008d963,
266 /* XFER_PIO_3 */ 0xc010d974,
267 /* XFER_PIO_2 */ 0xc010d997,
268 /* XFER_PIO_1 */ 0xc010d9c7,
269 /* XFER_PIO_0 */ 0xc018d9d9
270 };
271
272 static u32 thirty_three_base_hpt36x[] = {
273 /* XFER_UDMA_6 */ 0x90c9a731,
274 /* XFER_UDMA_5 */ 0x90c9a731,
275 /* XFER_UDMA_4 */ 0x90c9a731,
276 /* XFER_UDMA_3 */ 0x90cfa731,
277 /* XFER_UDMA_2 */ 0x90caa731,
278 /* XFER_UDMA_1 */ 0x90cba731,
279 /* XFER_UDMA_0 */ 0x90c8a731,
280
281 /* XFER_MW_DMA_2 */ 0xa0c8a731,
282 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
283 /* XFER_MW_DMA_0 */ 0xa0c8a797,
284
285 /* XFER_PIO_4 */ 0xc0c8a731,
286 /* XFER_PIO_3 */ 0xc0c8a742,
287 /* XFER_PIO_2 */ 0xc0d0a753,
288 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
289 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
290 };
291
292 static u32 twenty_five_base_hpt36x[] = {
293 /* XFER_UDMA_6 */ 0x90c98521,
294 /* XFER_UDMA_5 */ 0x90c98521,
295 /* XFER_UDMA_4 */ 0x90c98521,
296 /* XFER_UDMA_3 */ 0x90cf8521,
297 /* XFER_UDMA_2 */ 0x90cf8521,
298 /* XFER_UDMA_1 */ 0x90cb8521,
299 /* XFER_UDMA_0 */ 0x90cb8521,
300
301 /* XFER_MW_DMA_2 */ 0xa0ca8521,
302 /* XFER_MW_DMA_1 */ 0xa0ca8532,
303 /* XFER_MW_DMA_0 */ 0xa0ca8575,
304
305 /* XFER_PIO_4 */ 0xc0ca8521,
306 /* XFER_PIO_3 */ 0xc0ca8532,
307 /* XFER_PIO_2 */ 0xc0ca8542,
308 /* XFER_PIO_1 */ 0xc0d08572,
309 /* XFER_PIO_0 */ 0xc0d08585
310 };
311
312 static u32 thirty_three_base_hpt37x[] = {
313 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
314 /* XFER_UDMA_5 */ 0x12446231,
315 /* XFER_UDMA_4 */ 0x12446231,
316 /* XFER_UDMA_3 */ 0x126c6231,
317 /* XFER_UDMA_2 */ 0x12486231,
318 /* XFER_UDMA_1 */ 0x124c6233,
319 /* XFER_UDMA_0 */ 0x12506297,
320
321 /* XFER_MW_DMA_2 */ 0x22406c31,
322 /* XFER_MW_DMA_1 */ 0x22406c33,
323 /* XFER_MW_DMA_0 */ 0x22406c97,
324
325 /* XFER_PIO_4 */ 0x06414e31,
326 /* XFER_PIO_3 */ 0x06414e42,
327 /* XFER_PIO_2 */ 0x06414e53,
328 /* XFER_PIO_1 */ 0x06814e93,
329 /* XFER_PIO_0 */ 0x06814ea7
330 };
331
332 static u32 fifty_base_hpt37x[] = {
333 /* XFER_UDMA_6 */ 0x12848242,
334 /* XFER_UDMA_5 */ 0x12848242,
335 /* XFER_UDMA_4 */ 0x12ac8242,
336 /* XFER_UDMA_3 */ 0x128c8242,
337 /* XFER_UDMA_2 */ 0x120c8242,
338 /* XFER_UDMA_1 */ 0x12148254,
339 /* XFER_UDMA_0 */ 0x121882ea,
340
341 /* XFER_MW_DMA_2 */ 0x22808242,
342 /* XFER_MW_DMA_1 */ 0x22808254,
343 /* XFER_MW_DMA_0 */ 0x228082ea,
344
345 /* XFER_PIO_4 */ 0x0a81f442,
346 /* XFER_PIO_3 */ 0x0a81f443,
347 /* XFER_PIO_2 */ 0x0a81f454,
348 /* XFER_PIO_1 */ 0x0ac1f465,
349 /* XFER_PIO_0 */ 0x0ac1f48a
350 };
351
352 static u32 sixty_six_base_hpt37x[] = {
353 /* XFER_UDMA_6 */ 0x1c869c62,
354 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
355 /* XFER_UDMA_4 */ 0x1c8a9c62,
356 /* XFER_UDMA_3 */ 0x1c8e9c62,
357 /* XFER_UDMA_2 */ 0x1c929c62,
358 /* XFER_UDMA_1 */ 0x1c9a9c62,
359 /* XFER_UDMA_0 */ 0x1c829c62,
360
361 /* XFER_MW_DMA_2 */ 0x2c829c62,
362 /* XFER_MW_DMA_1 */ 0x2c829c66,
363 /* XFER_MW_DMA_0 */ 0x2c829d2e,
364
365 /* XFER_PIO_4 */ 0x0c829c62,
366 /* XFER_PIO_3 */ 0x0c829c84,
367 /* XFER_PIO_2 */ 0x0c829ca6,
368 /* XFER_PIO_1 */ 0x0d029d26,
369 /* XFER_PIO_0 */ 0x0d029d5e
370 };
371
372 #define HPT366_DEBUG_DRIVE_INFO 0
373 #define HPT371_ALLOW_ATA133_6 1
374 #define HPT302_ALLOW_ATA133_6 1
375 #define HPT372_ALLOW_ATA133_6 1
376 #define HPT370_ALLOW_ATA100_5 0
377 #define HPT366_ALLOW_ATA66_4 1
378 #define HPT366_ALLOW_ATA66_3 1
379 #define HPT366_MAX_DEVS 8
380
381 /* Supported ATA clock frequencies */
382 enum ata_clock {
383 ATA_CLOCK_25MHZ,
384 ATA_CLOCK_33MHZ,
385 ATA_CLOCK_40MHZ,
386 ATA_CLOCK_50MHZ,
387 ATA_CLOCK_66MHZ,
388 NUM_ATA_CLOCKS
389 };
390
391 /*
392 * Hold all the HighPoint chip information in one place.
393 */
394
395 struct hpt_info {
396 u8 chip_type; /* Chip type */
397 u8 max_ultra; /* Max. UltraDMA mode allowed */
398 u8 dpll_clk; /* DPLL clock in MHz */
399 u8 pci_clk; /* PCI clock in MHz */
400 u32 **settings; /* Chipset settings table */
401 };
402
403 /* Supported HighPoint chips */
404 enum {
405 HPT36x,
406 HPT370,
407 HPT370A,
408 HPT374,
409 HPT372,
410 HPT372A,
411 HPT302,
412 HPT371,
413 HPT372N,
414 HPT302N,
415 HPT371N
416 };
417
418 static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
419 twenty_five_base_hpt36x,
420 thirty_three_base_hpt36x,
421 forty_base_hpt36x,
422 NULL,
423 NULL
424 };
425
426 static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
427 NULL,
428 thirty_three_base_hpt37x,
429 NULL,
430 fifty_base_hpt37x,
431 sixty_six_base_hpt37x
432 };
433
434 static struct hpt_info hpt36x __devinitdata = {
435 .chip_type = HPT36x,
436 .max_ultra = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? 4 : 3) : 2,
437 .dpll_clk = 0, /* no DPLL */
438 .settings = hpt36x_settings
439 };
440
441 static struct hpt_info hpt370 __devinitdata = {
442 .chip_type = HPT370,
443 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
444 .dpll_clk = 48,
445 .settings = hpt37x_settings
446 };
447
448 static struct hpt_info hpt370a __devinitdata = {
449 .chip_type = HPT370A,
450 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
451 .dpll_clk = 48,
452 .settings = hpt37x_settings
453 };
454
455 static struct hpt_info hpt374 __devinitdata = {
456 .chip_type = HPT374,
457 .max_ultra = 5,
458 .dpll_clk = 48,
459 .settings = hpt37x_settings
460 };
461
462 static struct hpt_info hpt372 __devinitdata = {
463 .chip_type = HPT372,
464 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
465 .dpll_clk = 55,
466 .settings = hpt37x_settings
467 };
468
469 static struct hpt_info hpt372a __devinitdata = {
470 .chip_type = HPT372A,
471 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
472 .dpll_clk = 66,
473 .settings = hpt37x_settings
474 };
475
476 static struct hpt_info hpt302 __devinitdata = {
477 .chip_type = HPT302,
478 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
479 .dpll_clk = 66,
480 .settings = hpt37x_settings
481 };
482
483 static struct hpt_info hpt371 __devinitdata = {
484 .chip_type = HPT371,
485 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
486 .dpll_clk = 66,
487 .settings = hpt37x_settings
488 };
489
490 static struct hpt_info hpt372n __devinitdata = {
491 .chip_type = HPT372N,
492 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
493 .dpll_clk = 77,
494 .settings = hpt37x_settings
495 };
496
497 static struct hpt_info hpt302n __devinitdata = {
498 .chip_type = HPT302N,
499 .max_ultra = HPT302_ALLOW_ATA133_6 ? 6 : 5,
500 .dpll_clk = 77,
501 .settings = hpt37x_settings
502 };
503
504 static struct hpt_info hpt371n __devinitdata = {
505 .chip_type = HPT371N,
506 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
507 .dpll_clk = 77,
508 .settings = hpt37x_settings
509 };
510
511 static int check_in_drive_list(ide_drive_t *drive, const char **list)
512 {
513 struct hd_driveid *id = drive->id;
514
515 while (*list)
516 if (!strcmp(*list++,id->model))
517 return 1;
518 return 0;
519 }
520
521 /*
522 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
523 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
524 */
525
526 static u8 hpt3xx_udma_filter(ide_drive_t *drive)
527 {
528 ide_hwif_t *hwif = HWIF(drive);
529 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
530 u8 mask = hwif->ultra_mask;
531
532 switch (info->chip_type) {
533 case HPT36x:
534 if (!HPT366_ALLOW_ATA66_4 ||
535 check_in_drive_list(drive, bad_ata66_4))
536 mask = ATA_UDMA3;
537
538 if (!HPT366_ALLOW_ATA66_3 ||
539 check_in_drive_list(drive, bad_ata66_3))
540 mask = ATA_UDMA2;
541 break;
542 case HPT370:
543 if (!HPT370_ALLOW_ATA100_5 ||
544 check_in_drive_list(drive, bad_ata100_5))
545 mask = ATA_UDMA4;
546 break;
547 case HPT370A:
548 if (!HPT370_ALLOW_ATA100_5 ||
549 check_in_drive_list(drive, bad_ata100_5))
550 return ATA_UDMA4;
551 case HPT372 :
552 case HPT372A:
553 case HPT372N:
554 case HPT374 :
555 if (ide_dev_is_sata(drive->id))
556 mask &= ~0x0e;
557 /* Fall thru */
558 default:
559 return mask;
560 }
561
562 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
563 }
564
565 static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
566 {
567 ide_hwif_t *hwif = HWIF(drive);
568 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
569
570 switch (info->chip_type) {
571 case HPT372 :
572 case HPT372A:
573 case HPT372N:
574 case HPT374 :
575 if (ide_dev_is_sata(drive->id))
576 return 0x00;
577 /* Fall thru */
578 default:
579 return 0x07;
580 }
581 }
582
583 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
584 {
585 int i;
586
587 /*
588 * Lookup the transfer mode table to get the index into
589 * the timing table.
590 *
591 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
592 */
593 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
594 if (xfer_speeds[i] == speed)
595 break;
596 /*
597 * NOTE: info->settings only points to the pointer
598 * to the list of the actual register values
599 */
600 return (*info->settings)[i];
601 }
602
603 static void hpt36x_set_mode(ide_drive_t *drive, const u8 speed)
604 {
605 ide_hwif_t *hwif = HWIF(drive);
606 struct pci_dev *dev = hwif->pci_dev;
607 struct hpt_info *info = pci_get_drvdata(dev);
608 u8 itr_addr = drive->dn ? 0x44 : 0x40;
609 u32 old_itr = 0;
610 u32 itr_mask, new_itr;
611
612 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
613 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff);
614
615 new_itr = get_speed_setting(speed, info);
616
617 /*
618 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
619 * to avoid problems handling I/O errors later
620 */
621 pci_read_config_dword(dev, itr_addr, &old_itr);
622 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
623 new_itr &= ~0xc0000000;
624
625 pci_write_config_dword(dev, itr_addr, new_itr);
626 }
627
628 static void hpt37x_set_mode(ide_drive_t *drive, const u8 speed)
629 {
630 ide_hwif_t *hwif = HWIF(drive);
631 struct pci_dev *dev = hwif->pci_dev;
632 struct hpt_info *info = pci_get_drvdata(dev);
633 u8 itr_addr = 0x40 + (drive->dn * 4);
634 u32 old_itr = 0;
635 u32 itr_mask, new_itr;
636
637 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
638 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
639
640 new_itr = get_speed_setting(speed, info);
641
642 pci_read_config_dword(dev, itr_addr, &old_itr);
643 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
644
645 if (speed < XFER_MW_DMA_0)
646 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
647 pci_write_config_dword(dev, itr_addr, new_itr);
648 }
649
650 static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
651 {
652 ide_hwif_t *hwif = HWIF(drive);
653 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
654
655 if (info->chip_type >= HPT370)
656 hpt37x_set_mode(drive, speed);
657 else /* hpt368: hpt_minimum_revision(dev, 2) */
658 hpt36x_set_mode(drive, speed);
659 }
660
661 static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
662 {
663 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
664 }
665
666 static int hpt3xx_quirkproc(ide_drive_t *drive)
667 {
668 struct hd_driveid *id = drive->id;
669 const char **list = quirk_drives;
670
671 while (*list)
672 if (strstr(id->model, *list++))
673 return 1;
674 return 0;
675 }
676
677 static void hpt3xx_intrproc(ide_drive_t *drive)
678 {
679 ide_hwif_t *hwif = HWIF(drive);
680
681 if (drive->quirk_list)
682 return;
683 /* drives in the quirk_list may not like intr setups/cleanups */
684 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
685 }
686
687 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
688 {
689 ide_hwif_t *hwif = HWIF(drive);
690 struct pci_dev *dev = hwif->pci_dev;
691 struct hpt_info *info = pci_get_drvdata(dev);
692
693 if (drive->quirk_list) {
694 if (info->chip_type >= HPT370) {
695 u8 scr1 = 0;
696
697 pci_read_config_byte(dev, 0x5a, &scr1);
698 if (((scr1 & 0x10) >> 4) != mask) {
699 if (mask)
700 scr1 |= 0x10;
701 else
702 scr1 &= ~0x10;
703 pci_write_config_byte(dev, 0x5a, scr1);
704 }
705 } else {
706 if (mask)
707 disable_irq(hwif->irq);
708 else
709 enable_irq (hwif->irq);
710 }
711 } else
712 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
713 IDE_CONTROL_REG);
714 }
715
716 /*
717 * This is specific to the HPT366 UDMA chipset
718 * by HighPoint|Triones Technologies, Inc.
719 */
720 static void hpt366_dma_lost_irq(ide_drive_t *drive)
721 {
722 struct pci_dev *dev = HWIF(drive)->pci_dev;
723 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
724
725 pci_read_config_byte(dev, 0x50, &mcr1);
726 pci_read_config_byte(dev, 0x52, &mcr3);
727 pci_read_config_byte(dev, 0x5a, &scr1);
728 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
729 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
730 if (scr1 & 0x10)
731 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
732 ide_dma_lost_irq(drive);
733 }
734
735 static void hpt370_clear_engine(ide_drive_t *drive)
736 {
737 ide_hwif_t *hwif = HWIF(drive);
738
739 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
740 udelay(10);
741 }
742
743 static void hpt370_irq_timeout(ide_drive_t *drive)
744 {
745 ide_hwif_t *hwif = HWIF(drive);
746 u16 bfifo = 0;
747 u8 dma_cmd;
748
749 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
750 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
751
752 /* get DMA command mode */
753 dma_cmd = hwif->INB(hwif->dma_command);
754 /* stop DMA */
755 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
756 hpt370_clear_engine(drive);
757 }
758
759 static void hpt370_ide_dma_start(ide_drive_t *drive)
760 {
761 #ifdef HPT_RESET_STATE_ENGINE
762 hpt370_clear_engine(drive);
763 #endif
764 ide_dma_start(drive);
765 }
766
767 static int hpt370_ide_dma_end(ide_drive_t *drive)
768 {
769 ide_hwif_t *hwif = HWIF(drive);
770 u8 dma_stat = hwif->INB(hwif->dma_status);
771
772 if (dma_stat & 0x01) {
773 /* wait a little */
774 udelay(20);
775 dma_stat = hwif->INB(hwif->dma_status);
776 if (dma_stat & 0x01)
777 hpt370_irq_timeout(drive);
778 }
779 return __ide_dma_end(drive);
780 }
781
782 static void hpt370_dma_timeout(ide_drive_t *drive)
783 {
784 hpt370_irq_timeout(drive);
785 ide_dma_timeout(drive);
786 }
787
788 /* returns 1 if DMA IRQ issued, 0 otherwise */
789 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
790 {
791 ide_hwif_t *hwif = HWIF(drive);
792 u16 bfifo = 0;
793 u8 dma_stat;
794
795 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
796 if (bfifo & 0x1FF) {
797 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
798 return 0;
799 }
800
801 dma_stat = inb(hwif->dma_status);
802 /* return 1 if INTR asserted */
803 if (dma_stat & 4)
804 return 1;
805
806 if (!drive->waiting_for_dma)
807 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
808 drive->name, __FUNCTION__);
809 return 0;
810 }
811
812 static int hpt374_ide_dma_end(ide_drive_t *drive)
813 {
814 ide_hwif_t *hwif = HWIF(drive);
815 struct pci_dev *dev = hwif->pci_dev;
816 u8 mcr = 0, mcr_addr = hwif->select_data;
817 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
818
819 pci_read_config_byte(dev, 0x6a, &bwsr);
820 pci_read_config_byte(dev, mcr_addr, &mcr);
821 if (bwsr & mask)
822 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
823 return __ide_dma_end(drive);
824 }
825
826 /**
827 * hpt3xxn_set_clock - perform clock switching dance
828 * @hwif: hwif to switch
829 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
830 *
831 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
832 */
833
834 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
835 {
836 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
837
838 if ((scr2 & 0x7f) == mode)
839 return;
840
841 /* Tristate the bus */
842 hwif->OUTB(0x80, hwif->dma_master + 0x73);
843 hwif->OUTB(0x80, hwif->dma_master + 0x77);
844
845 /* Switch clock and reset channels */
846 hwif->OUTB(mode, hwif->dma_master + 0x7b);
847 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
848
849 /*
850 * Reset the state machines.
851 * NOTE: avoid accidentally enabling the disabled channels.
852 */
853 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
854 hwif->dma_master + 0x70);
855 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
856 hwif->dma_master + 0x74);
857
858 /* Complete reset */
859 hwif->OUTB(0x00, hwif->dma_master + 0x79);
860
861 /* Reconnect channels to bus */
862 hwif->OUTB(0x00, hwif->dma_master + 0x73);
863 hwif->OUTB(0x00, hwif->dma_master + 0x77);
864 }
865
866 /**
867 * hpt3xxn_rw_disk - prepare for I/O
868 * @drive: drive for command
869 * @rq: block request structure
870 *
871 * This is called when a disk I/O is issued to HPT3xxN.
872 * We need it because of the clock switching.
873 */
874
875 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
876 {
877 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
878 }
879
880 /*
881 * Set/get power state for a drive.
882 * NOTE: affects both drives on each channel.
883 *
884 * When we turn the power back on, we need to re-initialize things.
885 */
886 #define TRISTATE_BIT 0x8000
887
888 static int hpt3xx_busproc(ide_drive_t *drive, int state)
889 {
890 ide_hwif_t *hwif = HWIF(drive);
891 struct pci_dev *dev = hwif->pci_dev;
892 u8 mcr_addr = hwif->select_data + 2;
893 u8 resetmask = hwif->channel ? 0x80 : 0x40;
894 u8 bsr2 = 0;
895 u16 mcr = 0;
896
897 hwif->bus_state = state;
898
899 /* Grab the status. */
900 pci_read_config_word(dev, mcr_addr, &mcr);
901 pci_read_config_byte(dev, 0x59, &bsr2);
902
903 /*
904 * Set the state. We don't set it if we don't need to do so.
905 * Make sure that the drive knows that it has failed if it's off.
906 */
907 switch (state) {
908 case BUSSTATE_ON:
909 if (!(bsr2 & resetmask))
910 return 0;
911 hwif->drives[0].failures = hwif->drives[1].failures = 0;
912
913 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
914 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
915 return 0;
916 case BUSSTATE_OFF:
917 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
918 return 0;
919 mcr &= ~TRISTATE_BIT;
920 break;
921 case BUSSTATE_TRISTATE:
922 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
923 return 0;
924 mcr |= TRISTATE_BIT;
925 break;
926 default:
927 return -EINVAL;
928 }
929
930 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
931 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
932
933 pci_write_config_word(dev, mcr_addr, mcr);
934 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
935 return 0;
936 }
937
938 /**
939 * hpt37x_calibrate_dpll - calibrate the DPLL
940 * @dev: PCI device
941 *
942 * Perform a calibration cycle on the DPLL.
943 * Returns 1 if this succeeds
944 */
945 static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
946 {
947 u32 dpll = (f_high << 16) | f_low | 0x100;
948 u8 scr2;
949 int i;
950
951 pci_write_config_dword(dev, 0x5c, dpll);
952
953 /* Wait for oscillator ready */
954 for(i = 0; i < 0x5000; ++i) {
955 udelay(50);
956 pci_read_config_byte(dev, 0x5b, &scr2);
957 if (scr2 & 0x80)
958 break;
959 }
960 /* See if it stays ready (we'll just bail out if it's not yet) */
961 for(i = 0; i < 0x1000; ++i) {
962 pci_read_config_byte(dev, 0x5b, &scr2);
963 /* DPLL destabilized? */
964 if(!(scr2 & 0x80))
965 return 0;
966 }
967 /* Turn off tuning, we have the DPLL set */
968 pci_read_config_dword (dev, 0x5c, &dpll);
969 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
970 return 1;
971 }
972
973 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
974 {
975 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
976 unsigned long io_base = pci_resource_start(dev, 4);
977 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
978 u8 chip_type;
979 enum ata_clock clock;
980
981 if (info == NULL) {
982 printk(KERN_ERR "%s: out of memory!\n", name);
983 return -ENOMEM;
984 }
985
986 /*
987 * Copy everything from a static "template" structure
988 * to just allocated per-chip hpt_info structure.
989 */
990 memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info));
991 chip_type = info->chip_type;
992
993 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
994 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
995 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
996 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
997
998 /*
999 * First, try to estimate the PCI clock frequency...
1000 */
1001 if (chip_type >= HPT370) {
1002 u8 scr1 = 0;
1003 u16 f_cnt = 0;
1004 u32 temp = 0;
1005
1006 /* Interrupt force enable. */
1007 pci_read_config_byte(dev, 0x5a, &scr1);
1008 if (scr1 & 0x10)
1009 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1010
1011 /*
1012 * HighPoint does this for HPT372A.
1013 * NOTE: This register is only writeable via I/O space.
1014 */
1015 if (chip_type == HPT372A)
1016 outb(0x0e, io_base + 0x9c);
1017
1018 /*
1019 * Default to PCI clock. Make sure MA15/16 are set to output
1020 * to prevent drives having problems with 40-pin cables.
1021 */
1022 pci_write_config_byte(dev, 0x5b, 0x23);
1023
1024 /*
1025 * We'll have to read f_CNT value in order to determine
1026 * the PCI clock frequency according to the following ratio:
1027 *
1028 * f_CNT = Fpci * 192 / Fdpll
1029 *
1030 * First try reading the register in which the HighPoint BIOS
1031 * saves f_CNT value before reprogramming the DPLL from its
1032 * default setting (which differs for the various chips).
1033 *
1034 * NOTE: This register is only accessible via I/O space;
1035 * HPT374 BIOS only saves it for the function 0, so we have to
1036 * always read it from there -- no need to check the result of
1037 * pci_get_slot() for the function 0 as the whole device has
1038 * been already "pinned" (via function 1) in init_setup_hpt374()
1039 */
1040 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1041 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1042 dev->devfn - 1);
1043 unsigned long io_base = pci_resource_start(dev1, 4);
1044
1045 temp = inl(io_base + 0x90);
1046 pci_dev_put(dev1);
1047 } else
1048 temp = inl(io_base + 0x90);
1049
1050 /*
1051 * In case the signature check fails, we'll have to
1052 * resort to reading the f_CNT register itself in hopes
1053 * that nobody has touched the DPLL yet...
1054 */
1055 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1056 int i;
1057
1058 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1059 name);
1060
1061 /* Calculate the average value of f_CNT. */
1062 for (temp = i = 0; i < 128; i++) {
1063 pci_read_config_word(dev, 0x78, &f_cnt);
1064 temp += f_cnt & 0x1ff;
1065 mdelay(1);
1066 }
1067 f_cnt = temp / 128;
1068 } else
1069 f_cnt = temp & 0x1ff;
1070
1071 dpll_clk = info->dpll_clk;
1072 pci_clk = (f_cnt * dpll_clk) / 192;
1073
1074 /* Clamp PCI clock to bands. */
1075 if (pci_clk < 40)
1076 pci_clk = 33;
1077 else if(pci_clk < 45)
1078 pci_clk = 40;
1079 else if(pci_clk < 55)
1080 pci_clk = 50;
1081 else
1082 pci_clk = 66;
1083
1084 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1085 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1086 } else {
1087 u32 itr1 = 0;
1088
1089 pci_read_config_dword(dev, 0x40, &itr1);
1090
1091 /* Detect PCI clock by looking at cmd_high_time. */
1092 switch((itr1 >> 8) & 0x07) {
1093 case 0x09:
1094 pci_clk = 40;
1095 break;
1096 case 0x05:
1097 pci_clk = 25;
1098 break;
1099 case 0x07:
1100 default:
1101 pci_clk = 33;
1102 break;
1103 }
1104 }
1105
1106 /* Let's assume we'll use PCI clock for the ATA clock... */
1107 switch (pci_clk) {
1108 case 25:
1109 clock = ATA_CLOCK_25MHZ;
1110 break;
1111 case 33:
1112 default:
1113 clock = ATA_CLOCK_33MHZ;
1114 break;
1115 case 40:
1116 clock = ATA_CLOCK_40MHZ;
1117 break;
1118 case 50:
1119 clock = ATA_CLOCK_50MHZ;
1120 break;
1121 case 66:
1122 clock = ATA_CLOCK_66MHZ;
1123 break;
1124 }
1125
1126 /*
1127 * Only try the DPLL if we don't have a table for the PCI clock that
1128 * we are running at for HPT370/A, always use it for anything newer...
1129 *
1130 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1131 * We also don't like using the DPLL because this causes glitches
1132 * on PRST-/SRST- when the state engine gets reset...
1133 */
1134 if (chip_type >= HPT374 || info->settings[clock] == NULL) {
1135 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1136 int adjust;
1137
1138 /*
1139 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1140 * supported/enabled, use 50 MHz DPLL clock otherwise...
1141 */
1142 if (info->max_ultra == 6) {
1143 dpll_clk = 66;
1144 clock = ATA_CLOCK_66MHZ;
1145 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1146 dpll_clk = 50;
1147 clock = ATA_CLOCK_50MHZ;
1148 }
1149
1150 if (info->settings[clock] == NULL) {
1151 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1152 kfree(info);
1153 return -EIO;
1154 }
1155
1156 /* Select the DPLL clock. */
1157 pci_write_config_byte(dev, 0x5b, 0x21);
1158
1159 /*
1160 * Adjust the DPLL based upon PCI clock, enable it,
1161 * and wait for stabilization...
1162 */
1163 f_low = (pci_clk * 48) / dpll_clk;
1164
1165 for (adjust = 0; adjust < 8; adjust++) {
1166 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1167 break;
1168
1169 /*
1170 * See if it'll settle at a fractionally different clock
1171 */
1172 if (adjust & 1)
1173 f_low -= adjust >> 1;
1174 else
1175 f_low += adjust >> 1;
1176 }
1177 if (adjust == 8) {
1178 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1179 kfree(info);
1180 return -EIO;
1181 }
1182
1183 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1184 } else {
1185 /* Mark the fact that we're not using the DPLL. */
1186 dpll_clk = 0;
1187
1188 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1189 }
1190
1191 /*
1192 * Advance the table pointer to a slot which points to the list
1193 * of the register values settings matching the clock being used.
1194 */
1195 info->settings += clock;
1196
1197 /* Store the clock frequencies. */
1198 info->dpll_clk = dpll_clk;
1199 info->pci_clk = pci_clk;
1200
1201 /* Point to this chip's own instance of the hpt_info structure. */
1202 pci_set_drvdata(dev, info);
1203
1204 if (chip_type >= HPT370) {
1205 u8 mcr1, mcr4;
1206
1207 /*
1208 * Reset the state engines.
1209 * NOTE: Avoid accidentally enabling the disabled channels.
1210 */
1211 pci_read_config_byte (dev, 0x50, &mcr1);
1212 pci_read_config_byte (dev, 0x54, &mcr4);
1213 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1214 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1215 udelay(100);
1216 }
1217
1218 /*
1219 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1220 * the MISC. register to stretch the UltraDMA Tss timing.
1221 * NOTE: This register is only writeable via I/O space.
1222 */
1223 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1224
1225 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1226
1227 return dev->irq;
1228 }
1229
1230 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1231 {
1232 struct pci_dev *dev = hwif->pci_dev;
1233 struct hpt_info *info = pci_get_drvdata(dev);
1234 int serialize = HPT_SERIALIZE_IO;
1235 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1236 u8 chip_type = info->chip_type;
1237 u8 new_mcr, old_mcr = 0;
1238
1239 /* Cache the channel's MISC. control registers' offset */
1240 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1241
1242 hwif->set_pio_mode = &hpt3xx_set_pio_mode;
1243 hwif->set_dma_mode = &hpt3xx_set_mode;
1244 hwif->quirkproc = &hpt3xx_quirkproc;
1245 hwif->intrproc = &hpt3xx_intrproc;
1246 hwif->maskproc = &hpt3xx_maskproc;
1247 hwif->busproc = &hpt3xx_busproc;
1248
1249 hwif->udma_filter = &hpt3xx_udma_filter;
1250 hwif->mdma_filter = &hpt3xx_mdma_filter;
1251
1252 /*
1253 * HPT3xxN chips have some complications:
1254 *
1255 * - on 33 MHz PCI we must clock switch
1256 * - on 66 MHz PCI we must NOT use the PCI clock
1257 */
1258 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1259 /*
1260 * Clock is shared between the channels,
1261 * so we'll have to serialize them... :-(
1262 */
1263 serialize = 1;
1264 hwif->rw_disk = &hpt3xxn_rw_disk;
1265 }
1266
1267 /* Serialize access to this device if needed */
1268 if (serialize && hwif->mate)
1269 hwif->serialized = hwif->mate->serialized = 1;
1270
1271 /*
1272 * Disable the "fast interrupt" prediction. Don't hold off
1273 * on interrupts. (== 0x01 despite what the docs say)
1274 */
1275 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1276
1277 if (info->chip_type >= HPT374)
1278 new_mcr = old_mcr & ~0x07;
1279 else if (info->chip_type >= HPT370) {
1280 new_mcr = old_mcr;
1281 new_mcr &= ~0x02;
1282
1283 #ifdef HPT_DELAY_INTERRUPT
1284 new_mcr &= ~0x01;
1285 #else
1286 new_mcr |= 0x01;
1287 #endif
1288 } else /* HPT366 and HPT368 */
1289 new_mcr = old_mcr & ~0x80;
1290
1291 if (new_mcr != old_mcr)
1292 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1293
1294 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1295
1296 if (hwif->dma_base == 0)
1297 return;
1298
1299 hwif->ultra_mask = hwif->cds->udma_mask;
1300 hwif->mwdma_mask = 0x07;
1301
1302 /*
1303 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1304 * address lines to access an external EEPROM. To read valid
1305 * cable detect state the pins must be enabled as inputs.
1306 */
1307 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1308 /*
1309 * HPT374 PCI function 1
1310 * - set bit 15 of reg 0x52 to enable TCBLID as input
1311 * - set bit 15 of reg 0x56 to enable FCBLID as input
1312 */
1313 u8 mcr_addr = hwif->select_data + 2;
1314 u16 mcr;
1315
1316 pci_read_config_word (dev, mcr_addr, &mcr);
1317 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1318 /* now read cable id register */
1319 pci_read_config_byte (dev, 0x5a, &scr1);
1320 pci_write_config_word(dev, mcr_addr, mcr);
1321 } else if (chip_type >= HPT370) {
1322 /*
1323 * HPT370/372 and 374 pcifn 0
1324 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1325 */
1326 u8 scr2 = 0;
1327
1328 pci_read_config_byte (dev, 0x5b, &scr2);
1329 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1330 /* now read cable id register */
1331 pci_read_config_byte (dev, 0x5a, &scr1);
1332 pci_write_config_byte(dev, 0x5b, scr2);
1333 } else
1334 pci_read_config_byte (dev, 0x5a, &scr1);
1335
1336 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
1337 hwif->cbl = (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1338
1339 if (chip_type >= HPT374) {
1340 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1341 hwif->ide_dma_end = &hpt374_ide_dma_end;
1342 } else if (chip_type >= HPT370) {
1343 hwif->dma_start = &hpt370_ide_dma_start;
1344 hwif->ide_dma_end = &hpt370_ide_dma_end;
1345 hwif->dma_timeout = &hpt370_dma_timeout;
1346 } else
1347 hwif->dma_lost_irq = &hpt366_dma_lost_irq;
1348
1349 if (!noautodma)
1350 hwif->autodma = 1;
1351 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1352 }
1353
1354 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1355 {
1356 struct pci_dev *dev = hwif->pci_dev;
1357 u8 masterdma = 0, slavedma = 0;
1358 u8 dma_new = 0, dma_old = 0;
1359 unsigned long flags;
1360
1361 dma_old = hwif->INB(dmabase + 2);
1362
1363 local_irq_save(flags);
1364
1365 dma_new = dma_old;
1366 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1367 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1368
1369 if (masterdma & 0x30) dma_new |= 0x20;
1370 if ( slavedma & 0x30) dma_new |= 0x40;
1371 if (dma_new != dma_old)
1372 hwif->OUTB(dma_new, dmabase + 2);
1373
1374 local_irq_restore(flags);
1375
1376 ide_setup_dma(hwif, dmabase, 8);
1377 }
1378
1379 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1380 {
1381 struct pci_dev *dev2;
1382
1383 if (PCI_FUNC(dev->devfn) & 1)
1384 return -ENODEV;
1385
1386 pci_set_drvdata(dev, &hpt374);
1387
1388 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1389 int ret;
1390
1391 pci_set_drvdata(dev2, &hpt374);
1392
1393 if (dev2->irq != dev->irq) {
1394 /* FIXME: we need a core pci_set_interrupt() */
1395 dev2->irq = dev->irq;
1396 printk(KERN_WARNING "%s: PCI config space interrupt "
1397 "fixed.\n", d->name);
1398 }
1399 ret = ide_setup_pci_devices(dev, dev2, d);
1400 if (ret < 0)
1401 pci_dev_put(dev2);
1402 return ret;
1403 }
1404 return ide_setup_pci_device(dev, d);
1405 }
1406
1407 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1408 {
1409 pci_set_drvdata(dev, &hpt372n);
1410
1411 return ide_setup_pci_device(dev, d);
1412 }
1413
1414 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1415 {
1416 struct hpt_info *info;
1417 u8 mcr1 = 0;
1418
1419 if (dev->revision > 1) {
1420 d->name = "HPT371N";
1421
1422 info = &hpt371n;
1423 } else
1424 info = &hpt371;
1425
1426 /*
1427 * HPT371 chips physically have only one channel, the secondary one,
1428 * but the primary channel registers do exist! Go figure...
1429 * So, we manually disable the non-existing channel here
1430 * (if the BIOS hasn't done this already).
1431 */
1432 pci_read_config_byte(dev, 0x50, &mcr1);
1433 if (mcr1 & 0x04)
1434 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1435
1436 pci_set_drvdata(dev, info);
1437
1438 return ide_setup_pci_device(dev, d);
1439 }
1440
1441 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1442 {
1443 struct hpt_info *info;
1444
1445 if (dev->revision > 1) {
1446 d->name = "HPT372N";
1447
1448 info = &hpt372n;
1449 } else
1450 info = &hpt372a;
1451 pci_set_drvdata(dev, info);
1452
1453 return ide_setup_pci_device(dev, d);
1454 }
1455
1456 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1457 {
1458 struct hpt_info *info;
1459
1460 if (dev->revision > 1) {
1461 d->name = "HPT302N";
1462
1463 info = &hpt302n;
1464 } else
1465 info = &hpt302;
1466 pci_set_drvdata(dev, info);
1467
1468 return ide_setup_pci_device(dev, d);
1469 }
1470
1471 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1472 {
1473 struct pci_dev *dev2;
1474 u8 rev = dev->revision;
1475 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
1476 "HPT370", "HPT370A", "HPT372",
1477 "HPT372N" };
1478 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
1479 &hpt370, &hpt370a, &hpt372,
1480 &hpt372n };
1481
1482 if (PCI_FUNC(dev->devfn) & 1)
1483 return -ENODEV;
1484
1485 switch (rev) {
1486 case 0:
1487 case 1:
1488 case 2:
1489 /*
1490 * HPT36x chips have one channel per function and have
1491 * both channel enable bits located differently and visible
1492 * to both functions -- really stupid design decision... :-(
1493 * Bit 4 is for the primary channel, bit 5 for the secondary.
1494 */
1495 d->host_flags |= IDE_HFLAG_SINGLE;
1496 d->enablebits[0].mask = d->enablebits[0].val = 0x10;
1497
1498 d->udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ?
1499 ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2;
1500 break;
1501 case 3:
1502 case 4:
1503 d->udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4;
1504 break;
1505 default:
1506 rev = 6;
1507 /* fall thru */
1508 case 5:
1509 case 6:
1510 d->udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5;
1511 break;
1512 }
1513
1514 d->name = chipset_names[rev];
1515
1516 pci_set_drvdata(dev, info[rev]);
1517
1518 if (rev > 2)
1519 goto init_single;
1520
1521 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1522 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1523 int ret;
1524
1525 pci_set_drvdata(dev2, info[rev]);
1526
1527 /*
1528 * Now we'll have to force both channels enabled if
1529 * at least one of them has been enabled by BIOS...
1530 */
1531 pci_read_config_byte(dev, 0x50, &mcr1);
1532 if (mcr1 & 0x30)
1533 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1534
1535 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1536 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1537 if (pin1 != pin2 && dev->irq == dev2->irq) {
1538 d->bootable = ON_BOARD;
1539 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1540 d->name, pin1, pin2);
1541 }
1542 ret = ide_setup_pci_devices(dev, dev2, d);
1543 if (ret < 0)
1544 pci_dev_put(dev2);
1545 return ret;
1546 }
1547 init_single:
1548 return ide_setup_pci_device(dev, d);
1549 }
1550
1551 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1552 { /* 0 */
1553 .name = "HPT366",
1554 .init_setup = init_setup_hpt366,
1555 .init_chipset = init_chipset_hpt366,
1556 .init_hwif = init_hwif_hpt366,
1557 .init_dma = init_dma_hpt366,
1558 .autodma = AUTODMA,
1559 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1560 .bootable = OFF_BOARD,
1561 .extra = 240,
1562 .pio_mask = ATA_PIO4,
1563 },{ /* 1 */
1564 .name = "HPT372A",
1565 .init_setup = init_setup_hpt372a,
1566 .init_chipset = init_chipset_hpt366,
1567 .init_hwif = init_hwif_hpt366,
1568 .init_dma = init_dma_hpt366,
1569 .autodma = AUTODMA,
1570 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1571 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1572 .bootable = OFF_BOARD,
1573 .extra = 240,
1574 .pio_mask = ATA_PIO4,
1575 },{ /* 2 */
1576 .name = "HPT302",
1577 .init_setup = init_setup_hpt302,
1578 .init_chipset = init_chipset_hpt366,
1579 .init_hwif = init_hwif_hpt366,
1580 .init_dma = init_dma_hpt366,
1581 .autodma = AUTODMA,
1582 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1583 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1584 .bootable = OFF_BOARD,
1585 .extra = 240,
1586 .pio_mask = ATA_PIO4,
1587 },{ /* 3 */
1588 .name = "HPT371",
1589 .init_setup = init_setup_hpt371,
1590 .init_chipset = init_chipset_hpt366,
1591 .init_hwif = init_hwif_hpt366,
1592 .init_dma = init_dma_hpt366,
1593 .autodma = AUTODMA,
1594 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1595 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1596 .bootable = OFF_BOARD,
1597 .extra = 240,
1598 .pio_mask = ATA_PIO4,
1599 },{ /* 4 */
1600 .name = "HPT374",
1601 .init_setup = init_setup_hpt374,
1602 .init_chipset = init_chipset_hpt366,
1603 .init_hwif = init_hwif_hpt366,
1604 .init_dma = init_dma_hpt366,
1605 .autodma = AUTODMA,
1606 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1607 .udma_mask = ATA_UDMA5,
1608 .bootable = OFF_BOARD,
1609 .extra = 240,
1610 .pio_mask = ATA_PIO4,
1611 },{ /* 5 */
1612 .name = "HPT372N",
1613 .init_setup = init_setup_hpt372n,
1614 .init_chipset = init_chipset_hpt366,
1615 .init_hwif = init_hwif_hpt366,
1616 .init_dma = init_dma_hpt366,
1617 .autodma = AUTODMA,
1618 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1619 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1620 .bootable = OFF_BOARD,
1621 .extra = 240,
1622 .pio_mask = ATA_PIO4,
1623 }
1624 };
1625
1626 /**
1627 * hpt366_init_one - called when an HPT366 is found
1628 * @dev: the hpt366 device
1629 * @id: the matching pci id
1630 *
1631 * Called when the PCI registration layer (or the IDE initialization)
1632 * finds a device matching our IDE device tables.
1633 *
1634 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1635 * structure depending on the chip's revision, we'd better pass a local
1636 * copy down the call chain...
1637 */
1638 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1639 {
1640 ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1641
1642 return d.init_setup(dev, &d);
1643 }
1644
1645 static const struct pci_device_id hpt366_pci_tbl[] = {
1646 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1647 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1648 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1649 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1650 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1651 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
1652 { 0, },
1653 };
1654 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1655
1656 static struct pci_driver driver = {
1657 .name = "HPT366_IDE",
1658 .id_table = hpt366_pci_tbl,
1659 .probe = hpt366_init_one,
1660 };
1661
1662 static int __init hpt366_ide_init(void)
1663 {
1664 return ide_pci_register_driver(&driver);
1665 }
1666
1667 module_init(hpt366_ide_init);
1668
1669 MODULE_AUTHOR("Andre Hedrick");
1670 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1671 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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