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ide: move ide_config_drive_speed() calls to upper layers (take 2)
[deliverable/linux.git] / drivers / ide / pci / hpt366.c
1 /*
2 * linux/drivers/ide/pci/hpt366.c Version 1.13 Sep 29, 2007
3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
8 *
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
13 *
14 *
15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
20 *
21 * Note that final HPT370 support was done by force extraction of GPL.
22 *
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
37 *
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
43 *
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
46 *
47 * On hpt366:
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
51 *
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
55 * keeping me sane.
56 * Alan Cox <alan@redhat.com>
57 *
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
64 * does not allow for this speed anyway
65 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
66 * their primary channel is kind of virtual, it isn't tied to any pins)
67 * - fix/remove bad/unused timing tables and use one set of tables for the whole
68 * HPT37x chip family; save space by introducing the separate transfer mode
69 * table in which the mode lookup is done
70 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
71 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
72 * read it only from the function 0 of HPT374 chips
73 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
74 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
75 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
76 * they tamper with its fields
77 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
78 * since they may tamper with its fields
79 * - prefix the driver startup messages with the real chip name
80 * - claim the extra 240 bytes of I/O space for all chips
81 * - optimize the UltraDMA filtering and the drive list lookup code
82 * - use pci_get_slot() to get to the function 1 of HPT36x/374
83 * - cache offset of the channel's misc. control registers (MCRs) being used
84 * throughout the driver
85 * - only touch the relevant MCR when detecting the cable type on HPT374's
86 * function 1
87 * - rename all the register related variables consistently
88 * - move all the interrupt twiddling code from the speedproc handlers into
89 * init_hwif_hpt366(), also grouping all the DMA related code together there
90 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
91 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
92 * when setting an UltraDMA mode
93 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
94 * the best possible one
95 * - clean up DMA timeout handling for HPT370
96 * - switch to using the enumeration type to differ between the numerous chip
97 * variants, matching PCI device/revision ID with the chip type early, at the
98 * init_setup stage
99 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
100 * stop duplicating it for each channel by storing the pointer in the pci_dev
101 * structure: first, at the init_setup stage, point it to a static "template"
102 * with only the chip type and its specific base DPLL frequency, the highest
103 * UltraDMA mode, and the chip settings table pointer filled, then, at the
104 * init_chipset stage, allocate per-chip instance and fill it with the rest
105 * of the necessary information
106 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
107 * switch to calculating PCI clock frequency based on the chip's base DPLL
108 * frequency
109 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
110 * anything newer than HPT370/A (except HPT374 that is not capable of this
111 * mode according to the manual)
112 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
113 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
114 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
115 * the register setting lists into the table indexed by the clock selected
116 * - set the correct hwif->ultra_mask for each individual chip
117 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
118 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
119 */
120
121 #include <linux/types.h>
122 #include <linux/module.h>
123 #include <linux/kernel.h>
124 #include <linux/delay.h>
125 #include <linux/timer.h>
126 #include <linux/mm.h>
127 #include <linux/ioport.h>
128 #include <linux/blkdev.h>
129 #include <linux/hdreg.h>
130
131 #include <linux/interrupt.h>
132 #include <linux/pci.h>
133 #include <linux/init.h>
134 #include <linux/ide.h>
135
136 #include <asm/uaccess.h>
137 #include <asm/io.h>
138 #include <asm/irq.h>
139
140 /* various tuning parameters */
141 #define HPT_RESET_STATE_ENGINE
142 #undef HPT_DELAY_INTERRUPT
143 #define HPT_SERIALIZE_IO 0
144
145 static const char *quirk_drives[] = {
146 "QUANTUM FIREBALLlct08 08",
147 "QUANTUM FIREBALLP KA6.4",
148 "QUANTUM FIREBALLP LM20.4",
149 "QUANTUM FIREBALLP LM20.5",
150 NULL
151 };
152
153 static const char *bad_ata100_5[] = {
154 "IBM-DTLA-307075",
155 "IBM-DTLA-307060",
156 "IBM-DTLA-307045",
157 "IBM-DTLA-307030",
158 "IBM-DTLA-307020",
159 "IBM-DTLA-307015",
160 "IBM-DTLA-305040",
161 "IBM-DTLA-305030",
162 "IBM-DTLA-305020",
163 "IC35L010AVER07-0",
164 "IC35L020AVER07-0",
165 "IC35L030AVER07-0",
166 "IC35L040AVER07-0",
167 "IC35L060AVER07-0",
168 "WDC AC310200R",
169 NULL
170 };
171
172 static const char *bad_ata66_4[] = {
173 "IBM-DTLA-307075",
174 "IBM-DTLA-307060",
175 "IBM-DTLA-307045",
176 "IBM-DTLA-307030",
177 "IBM-DTLA-307020",
178 "IBM-DTLA-307015",
179 "IBM-DTLA-305040",
180 "IBM-DTLA-305030",
181 "IBM-DTLA-305020",
182 "IC35L010AVER07-0",
183 "IC35L020AVER07-0",
184 "IC35L030AVER07-0",
185 "IC35L040AVER07-0",
186 "IC35L060AVER07-0",
187 "WDC AC310200R",
188 "MAXTOR STM3320620A",
189 NULL
190 };
191
192 static const char *bad_ata66_3[] = {
193 "WDC AC310200R",
194 NULL
195 };
196
197 static const char *bad_ata33[] = {
198 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
199 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
200 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
201 "Maxtor 90510D4",
202 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
203 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
204 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
205 NULL
206 };
207
208 static u8 xfer_speeds[] = {
209 XFER_UDMA_6,
210 XFER_UDMA_5,
211 XFER_UDMA_4,
212 XFER_UDMA_3,
213 XFER_UDMA_2,
214 XFER_UDMA_1,
215 XFER_UDMA_0,
216
217 XFER_MW_DMA_2,
218 XFER_MW_DMA_1,
219 XFER_MW_DMA_0,
220
221 XFER_PIO_4,
222 XFER_PIO_3,
223 XFER_PIO_2,
224 XFER_PIO_1,
225 XFER_PIO_0
226 };
227
228 /* Key for bus clock timings
229 * 36x 37x
230 * bits bits
231 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
232 * cycles = value + 1
233 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
234 * cycles = value + 1
235 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
236 * register access.
237 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
238 * register access.
239 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
240 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
241 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
242 * MW DMA xfer.
243 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
244 * task file register access.
245 * 28 28 UDMA enable.
246 * 29 29 DMA enable.
247 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
248 * PIO xfer.
249 * 31 31 FIFO enable.
250 */
251
252 static u32 forty_base_hpt36x[] = {
253 /* XFER_UDMA_6 */ 0x900fd943,
254 /* XFER_UDMA_5 */ 0x900fd943,
255 /* XFER_UDMA_4 */ 0x900fd943,
256 /* XFER_UDMA_3 */ 0x900ad943,
257 /* XFER_UDMA_2 */ 0x900bd943,
258 /* XFER_UDMA_1 */ 0x9008d943,
259 /* XFER_UDMA_0 */ 0x9008d943,
260
261 /* XFER_MW_DMA_2 */ 0xa008d943,
262 /* XFER_MW_DMA_1 */ 0xa010d955,
263 /* XFER_MW_DMA_0 */ 0xa010d9fc,
264
265 /* XFER_PIO_4 */ 0xc008d963,
266 /* XFER_PIO_3 */ 0xc010d974,
267 /* XFER_PIO_2 */ 0xc010d997,
268 /* XFER_PIO_1 */ 0xc010d9c7,
269 /* XFER_PIO_0 */ 0xc018d9d9
270 };
271
272 static u32 thirty_three_base_hpt36x[] = {
273 /* XFER_UDMA_6 */ 0x90c9a731,
274 /* XFER_UDMA_5 */ 0x90c9a731,
275 /* XFER_UDMA_4 */ 0x90c9a731,
276 /* XFER_UDMA_3 */ 0x90cfa731,
277 /* XFER_UDMA_2 */ 0x90caa731,
278 /* XFER_UDMA_1 */ 0x90cba731,
279 /* XFER_UDMA_0 */ 0x90c8a731,
280
281 /* XFER_MW_DMA_2 */ 0xa0c8a731,
282 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
283 /* XFER_MW_DMA_0 */ 0xa0c8a797,
284
285 /* XFER_PIO_4 */ 0xc0c8a731,
286 /* XFER_PIO_3 */ 0xc0c8a742,
287 /* XFER_PIO_2 */ 0xc0d0a753,
288 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
289 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
290 };
291
292 static u32 twenty_five_base_hpt36x[] = {
293 /* XFER_UDMA_6 */ 0x90c98521,
294 /* XFER_UDMA_5 */ 0x90c98521,
295 /* XFER_UDMA_4 */ 0x90c98521,
296 /* XFER_UDMA_3 */ 0x90cf8521,
297 /* XFER_UDMA_2 */ 0x90cf8521,
298 /* XFER_UDMA_1 */ 0x90cb8521,
299 /* XFER_UDMA_0 */ 0x90cb8521,
300
301 /* XFER_MW_DMA_2 */ 0xa0ca8521,
302 /* XFER_MW_DMA_1 */ 0xa0ca8532,
303 /* XFER_MW_DMA_0 */ 0xa0ca8575,
304
305 /* XFER_PIO_4 */ 0xc0ca8521,
306 /* XFER_PIO_3 */ 0xc0ca8532,
307 /* XFER_PIO_2 */ 0xc0ca8542,
308 /* XFER_PIO_1 */ 0xc0d08572,
309 /* XFER_PIO_0 */ 0xc0d08585
310 };
311
312 static u32 thirty_three_base_hpt37x[] = {
313 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
314 /* XFER_UDMA_5 */ 0x12446231,
315 /* XFER_UDMA_4 */ 0x12446231,
316 /* XFER_UDMA_3 */ 0x126c6231,
317 /* XFER_UDMA_2 */ 0x12486231,
318 /* XFER_UDMA_1 */ 0x124c6233,
319 /* XFER_UDMA_0 */ 0x12506297,
320
321 /* XFER_MW_DMA_2 */ 0x22406c31,
322 /* XFER_MW_DMA_1 */ 0x22406c33,
323 /* XFER_MW_DMA_0 */ 0x22406c97,
324
325 /* XFER_PIO_4 */ 0x06414e31,
326 /* XFER_PIO_3 */ 0x06414e42,
327 /* XFER_PIO_2 */ 0x06414e53,
328 /* XFER_PIO_1 */ 0x06814e93,
329 /* XFER_PIO_0 */ 0x06814ea7
330 };
331
332 static u32 fifty_base_hpt37x[] = {
333 /* XFER_UDMA_6 */ 0x12848242,
334 /* XFER_UDMA_5 */ 0x12848242,
335 /* XFER_UDMA_4 */ 0x12ac8242,
336 /* XFER_UDMA_3 */ 0x128c8242,
337 /* XFER_UDMA_2 */ 0x120c8242,
338 /* XFER_UDMA_1 */ 0x12148254,
339 /* XFER_UDMA_0 */ 0x121882ea,
340
341 /* XFER_MW_DMA_2 */ 0x22808242,
342 /* XFER_MW_DMA_1 */ 0x22808254,
343 /* XFER_MW_DMA_0 */ 0x228082ea,
344
345 /* XFER_PIO_4 */ 0x0a81f442,
346 /* XFER_PIO_3 */ 0x0a81f443,
347 /* XFER_PIO_2 */ 0x0a81f454,
348 /* XFER_PIO_1 */ 0x0ac1f465,
349 /* XFER_PIO_0 */ 0x0ac1f48a
350 };
351
352 static u32 sixty_six_base_hpt37x[] = {
353 /* XFER_UDMA_6 */ 0x1c869c62,
354 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
355 /* XFER_UDMA_4 */ 0x1c8a9c62,
356 /* XFER_UDMA_3 */ 0x1c8e9c62,
357 /* XFER_UDMA_2 */ 0x1c929c62,
358 /* XFER_UDMA_1 */ 0x1c9a9c62,
359 /* XFER_UDMA_0 */ 0x1c829c62,
360
361 /* XFER_MW_DMA_2 */ 0x2c829c62,
362 /* XFER_MW_DMA_1 */ 0x2c829c66,
363 /* XFER_MW_DMA_0 */ 0x2c829d2e,
364
365 /* XFER_PIO_4 */ 0x0c829c62,
366 /* XFER_PIO_3 */ 0x0c829c84,
367 /* XFER_PIO_2 */ 0x0c829ca6,
368 /* XFER_PIO_1 */ 0x0d029d26,
369 /* XFER_PIO_0 */ 0x0d029d5e
370 };
371
372 #define HPT366_DEBUG_DRIVE_INFO 0
373 #define HPT371_ALLOW_ATA133_6 1
374 #define HPT302_ALLOW_ATA133_6 1
375 #define HPT372_ALLOW_ATA133_6 1
376 #define HPT370_ALLOW_ATA100_5 0
377 #define HPT366_ALLOW_ATA66_4 1
378 #define HPT366_ALLOW_ATA66_3 1
379 #define HPT366_MAX_DEVS 8
380
381 /* Supported ATA clock frequencies */
382 enum ata_clock {
383 ATA_CLOCK_25MHZ,
384 ATA_CLOCK_33MHZ,
385 ATA_CLOCK_40MHZ,
386 ATA_CLOCK_50MHZ,
387 ATA_CLOCK_66MHZ,
388 NUM_ATA_CLOCKS
389 };
390
391 /*
392 * Hold all the HighPoint chip information in one place.
393 */
394
395 struct hpt_info {
396 u8 chip_type; /* Chip type */
397 u8 max_ultra; /* Max. UltraDMA mode allowed */
398 u8 dpll_clk; /* DPLL clock in MHz */
399 u8 pci_clk; /* PCI clock in MHz */
400 u32 **settings; /* Chipset settings table */
401 };
402
403 /* Supported HighPoint chips */
404 enum {
405 HPT36x,
406 HPT370,
407 HPT370A,
408 HPT374,
409 HPT372,
410 HPT372A,
411 HPT302,
412 HPT371,
413 HPT372N,
414 HPT302N,
415 HPT371N
416 };
417
418 static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
419 twenty_five_base_hpt36x,
420 thirty_three_base_hpt36x,
421 forty_base_hpt36x,
422 NULL,
423 NULL
424 };
425
426 static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
427 NULL,
428 thirty_three_base_hpt37x,
429 NULL,
430 fifty_base_hpt37x,
431 sixty_six_base_hpt37x
432 };
433
434 static struct hpt_info hpt36x __devinitdata = {
435 .chip_type = HPT36x,
436 .max_ultra = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? 4 : 3) : 2,
437 .dpll_clk = 0, /* no DPLL */
438 .settings = hpt36x_settings
439 };
440
441 static struct hpt_info hpt370 __devinitdata = {
442 .chip_type = HPT370,
443 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
444 .dpll_clk = 48,
445 .settings = hpt37x_settings
446 };
447
448 static struct hpt_info hpt370a __devinitdata = {
449 .chip_type = HPT370A,
450 .max_ultra = HPT370_ALLOW_ATA100_5 ? 5 : 4,
451 .dpll_clk = 48,
452 .settings = hpt37x_settings
453 };
454
455 static struct hpt_info hpt374 __devinitdata = {
456 .chip_type = HPT374,
457 .max_ultra = 5,
458 .dpll_clk = 48,
459 .settings = hpt37x_settings
460 };
461
462 static struct hpt_info hpt372 __devinitdata = {
463 .chip_type = HPT372,
464 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
465 .dpll_clk = 55,
466 .settings = hpt37x_settings
467 };
468
469 static struct hpt_info hpt372a __devinitdata = {
470 .chip_type = HPT372A,
471 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
472 .dpll_clk = 66,
473 .settings = hpt37x_settings
474 };
475
476 static struct hpt_info hpt302 __devinitdata = {
477 .chip_type = HPT302,
478 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
479 .dpll_clk = 66,
480 .settings = hpt37x_settings
481 };
482
483 static struct hpt_info hpt371 __devinitdata = {
484 .chip_type = HPT371,
485 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
486 .dpll_clk = 66,
487 .settings = hpt37x_settings
488 };
489
490 static struct hpt_info hpt372n __devinitdata = {
491 .chip_type = HPT372N,
492 .max_ultra = HPT372_ALLOW_ATA133_6 ? 6 : 5,
493 .dpll_clk = 77,
494 .settings = hpt37x_settings
495 };
496
497 static struct hpt_info hpt302n __devinitdata = {
498 .chip_type = HPT302N,
499 .max_ultra = HPT302_ALLOW_ATA133_6 ? 6 : 5,
500 .dpll_clk = 77,
501 .settings = hpt37x_settings
502 };
503
504 static struct hpt_info hpt371n __devinitdata = {
505 .chip_type = HPT371N,
506 .max_ultra = HPT371_ALLOW_ATA133_6 ? 6 : 5,
507 .dpll_clk = 77,
508 .settings = hpt37x_settings
509 };
510
511 static int check_in_drive_list(ide_drive_t *drive, const char **list)
512 {
513 struct hd_driveid *id = drive->id;
514
515 while (*list)
516 if (!strcmp(*list++,id->model))
517 return 1;
518 return 0;
519 }
520
521 /*
522 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
523 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
524 */
525
526 static u8 hpt3xx_udma_filter(ide_drive_t *drive)
527 {
528 ide_hwif_t *hwif = HWIF(drive);
529 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
530 u8 mask = hwif->ultra_mask;
531
532 switch (info->chip_type) {
533 case HPT36x:
534 if (!HPT366_ALLOW_ATA66_4 ||
535 check_in_drive_list(drive, bad_ata66_4))
536 mask = ATA_UDMA3;
537
538 if (!HPT366_ALLOW_ATA66_3 ||
539 check_in_drive_list(drive, bad_ata66_3))
540 mask = ATA_UDMA2;
541 break;
542 case HPT370:
543 if (!HPT370_ALLOW_ATA100_5 ||
544 check_in_drive_list(drive, bad_ata100_5))
545 mask = ATA_UDMA4;
546 break;
547 case HPT370A:
548 if (!HPT370_ALLOW_ATA100_5 ||
549 check_in_drive_list(drive, bad_ata100_5))
550 return ATA_UDMA4;
551 case HPT372 :
552 case HPT372A:
553 case HPT372N:
554 case HPT374 :
555 if (ide_dev_is_sata(drive->id))
556 mask &= ~0x0e;
557 /* Fall thru */
558 default:
559 return mask;
560 }
561
562 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
563 }
564
565 static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
566 {
567 ide_hwif_t *hwif = HWIF(drive);
568 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
569
570 switch (info->chip_type) {
571 case HPT372 :
572 case HPT372A:
573 case HPT372N:
574 case HPT374 :
575 if (ide_dev_is_sata(drive->id))
576 return 0x00;
577 /* Fall thru */
578 default:
579 return 0x07;
580 }
581 }
582
583 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
584 {
585 int i;
586
587 /*
588 * Lookup the transfer mode table to get the index into
589 * the timing table.
590 *
591 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
592 */
593 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
594 if (xfer_speeds[i] == speed)
595 break;
596 /*
597 * NOTE: info->settings only points to the pointer
598 * to the list of the actual register values
599 */
600 return (*info->settings)[i];
601 }
602
603 static void hpt36x_set_mode(ide_drive_t *drive, const u8 speed)
604 {
605 ide_hwif_t *hwif = HWIF(drive);
606 struct pci_dev *dev = hwif->pci_dev;
607 struct hpt_info *info = pci_get_drvdata(dev);
608 u8 itr_addr = drive->dn ? 0x44 : 0x40;
609 u32 old_itr = 0;
610 u32 itr_mask, new_itr;
611
612 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
613 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff);
614
615 new_itr = get_speed_setting(speed, info);
616
617 /*
618 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
619 * to avoid problems handling I/O errors later
620 */
621 pci_read_config_dword(dev, itr_addr, &old_itr);
622 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
623 new_itr &= ~0xc0000000;
624
625 pci_write_config_dword(dev, itr_addr, new_itr);
626 }
627
628 static void hpt37x_set_mode(ide_drive_t *drive, const u8 speed)
629 {
630 ide_hwif_t *hwif = HWIF(drive);
631 struct pci_dev *dev = hwif->pci_dev;
632 struct hpt_info *info = pci_get_drvdata(dev);
633 u8 itr_addr = 0x40 + (drive->dn * 4);
634 u32 old_itr = 0;
635 u32 itr_mask, new_itr;
636
637 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
638 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
639
640 new_itr = get_speed_setting(speed, info);
641
642 pci_read_config_dword(dev, itr_addr, &old_itr);
643 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
644
645 if (speed < XFER_MW_DMA_0)
646 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
647 pci_write_config_dword(dev, itr_addr, new_itr);
648 }
649
650 static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
651 {
652 ide_hwif_t *hwif = HWIF(drive);
653 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
654
655 if (info->chip_type >= HPT370)
656 hpt37x_set_mode(drive, speed);
657 else /* hpt368: hpt_minimum_revision(dev, 2) */
658 hpt36x_set_mode(drive, speed);
659 }
660
661 static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
662 {
663 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
664 }
665
666 static int hpt3xx_quirkproc(ide_drive_t *drive)
667 {
668 struct hd_driveid *id = drive->id;
669 const char **list = quirk_drives;
670
671 while (*list)
672 if (strstr(id->model, *list++))
673 return 1;
674 return 0;
675 }
676
677 static void hpt3xx_intrproc(ide_drive_t *drive)
678 {
679 ide_hwif_t *hwif = HWIF(drive);
680
681 if (drive->quirk_list)
682 return;
683 /* drives in the quirk_list may not like intr setups/cleanups */
684 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
685 }
686
687 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
688 {
689 ide_hwif_t *hwif = HWIF(drive);
690 struct pci_dev *dev = hwif->pci_dev;
691 struct hpt_info *info = pci_get_drvdata(dev);
692
693 if (drive->quirk_list) {
694 if (info->chip_type >= HPT370) {
695 u8 scr1 = 0;
696
697 pci_read_config_byte(dev, 0x5a, &scr1);
698 if (((scr1 & 0x10) >> 4) != mask) {
699 if (mask)
700 scr1 |= 0x10;
701 else
702 scr1 &= ~0x10;
703 pci_write_config_byte(dev, 0x5a, scr1);
704 }
705 } else {
706 if (mask)
707 disable_irq(hwif->irq);
708 else
709 enable_irq (hwif->irq);
710 }
711 } else
712 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
713 IDE_CONTROL_REG);
714 }
715
716 static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
717 {
718 drive->init_speed = 0;
719
720 if (ide_tune_dma(drive))
721 return 0;
722
723 if (ide_use_fast_pio(drive))
724 ide_set_max_pio(drive);
725
726 return -1;
727 }
728
729 /*
730 * This is specific to the HPT366 UDMA chipset
731 * by HighPoint|Triones Technologies, Inc.
732 */
733 static void hpt366_dma_lost_irq(ide_drive_t *drive)
734 {
735 struct pci_dev *dev = HWIF(drive)->pci_dev;
736 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
737
738 pci_read_config_byte(dev, 0x50, &mcr1);
739 pci_read_config_byte(dev, 0x52, &mcr3);
740 pci_read_config_byte(dev, 0x5a, &scr1);
741 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
742 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
743 if (scr1 & 0x10)
744 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
745 ide_dma_lost_irq(drive);
746 }
747
748 static void hpt370_clear_engine(ide_drive_t *drive)
749 {
750 ide_hwif_t *hwif = HWIF(drive);
751
752 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
753 udelay(10);
754 }
755
756 static void hpt370_irq_timeout(ide_drive_t *drive)
757 {
758 ide_hwif_t *hwif = HWIF(drive);
759 u16 bfifo = 0;
760 u8 dma_cmd;
761
762 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
763 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
764
765 /* get DMA command mode */
766 dma_cmd = hwif->INB(hwif->dma_command);
767 /* stop DMA */
768 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
769 hpt370_clear_engine(drive);
770 }
771
772 static void hpt370_ide_dma_start(ide_drive_t *drive)
773 {
774 #ifdef HPT_RESET_STATE_ENGINE
775 hpt370_clear_engine(drive);
776 #endif
777 ide_dma_start(drive);
778 }
779
780 static int hpt370_ide_dma_end(ide_drive_t *drive)
781 {
782 ide_hwif_t *hwif = HWIF(drive);
783 u8 dma_stat = hwif->INB(hwif->dma_status);
784
785 if (dma_stat & 0x01) {
786 /* wait a little */
787 udelay(20);
788 dma_stat = hwif->INB(hwif->dma_status);
789 if (dma_stat & 0x01)
790 hpt370_irq_timeout(drive);
791 }
792 return __ide_dma_end(drive);
793 }
794
795 static void hpt370_dma_timeout(ide_drive_t *drive)
796 {
797 hpt370_irq_timeout(drive);
798 ide_dma_timeout(drive);
799 }
800
801 /* returns 1 if DMA IRQ issued, 0 otherwise */
802 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
803 {
804 ide_hwif_t *hwif = HWIF(drive);
805 u16 bfifo = 0;
806 u8 dma_stat;
807
808 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
809 if (bfifo & 0x1FF) {
810 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
811 return 0;
812 }
813
814 dma_stat = inb(hwif->dma_status);
815 /* return 1 if INTR asserted */
816 if (dma_stat & 4)
817 return 1;
818
819 if (!drive->waiting_for_dma)
820 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
821 drive->name, __FUNCTION__);
822 return 0;
823 }
824
825 static int hpt374_ide_dma_end(ide_drive_t *drive)
826 {
827 ide_hwif_t *hwif = HWIF(drive);
828 struct pci_dev *dev = hwif->pci_dev;
829 u8 mcr = 0, mcr_addr = hwif->select_data;
830 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
831
832 pci_read_config_byte(dev, 0x6a, &bwsr);
833 pci_read_config_byte(dev, mcr_addr, &mcr);
834 if (bwsr & mask)
835 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
836 return __ide_dma_end(drive);
837 }
838
839 /**
840 * hpt3xxn_set_clock - perform clock switching dance
841 * @hwif: hwif to switch
842 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
843 *
844 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
845 */
846
847 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
848 {
849 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
850
851 if ((scr2 & 0x7f) == mode)
852 return;
853
854 /* Tristate the bus */
855 hwif->OUTB(0x80, hwif->dma_master + 0x73);
856 hwif->OUTB(0x80, hwif->dma_master + 0x77);
857
858 /* Switch clock and reset channels */
859 hwif->OUTB(mode, hwif->dma_master + 0x7b);
860 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
861
862 /*
863 * Reset the state machines.
864 * NOTE: avoid accidentally enabling the disabled channels.
865 */
866 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
867 hwif->dma_master + 0x70);
868 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
869 hwif->dma_master + 0x74);
870
871 /* Complete reset */
872 hwif->OUTB(0x00, hwif->dma_master + 0x79);
873
874 /* Reconnect channels to bus */
875 hwif->OUTB(0x00, hwif->dma_master + 0x73);
876 hwif->OUTB(0x00, hwif->dma_master + 0x77);
877 }
878
879 /**
880 * hpt3xxn_rw_disk - prepare for I/O
881 * @drive: drive for command
882 * @rq: block request structure
883 *
884 * This is called when a disk I/O is issued to HPT3xxN.
885 * We need it because of the clock switching.
886 */
887
888 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
889 {
890 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
891 }
892
893 /*
894 * Set/get power state for a drive.
895 * NOTE: affects both drives on each channel.
896 *
897 * When we turn the power back on, we need to re-initialize things.
898 */
899 #define TRISTATE_BIT 0x8000
900
901 static int hpt3xx_busproc(ide_drive_t *drive, int state)
902 {
903 ide_hwif_t *hwif = HWIF(drive);
904 struct pci_dev *dev = hwif->pci_dev;
905 u8 mcr_addr = hwif->select_data + 2;
906 u8 resetmask = hwif->channel ? 0x80 : 0x40;
907 u8 bsr2 = 0;
908 u16 mcr = 0;
909
910 hwif->bus_state = state;
911
912 /* Grab the status. */
913 pci_read_config_word(dev, mcr_addr, &mcr);
914 pci_read_config_byte(dev, 0x59, &bsr2);
915
916 /*
917 * Set the state. We don't set it if we don't need to do so.
918 * Make sure that the drive knows that it has failed if it's off.
919 */
920 switch (state) {
921 case BUSSTATE_ON:
922 if (!(bsr2 & resetmask))
923 return 0;
924 hwif->drives[0].failures = hwif->drives[1].failures = 0;
925
926 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
927 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
928 return 0;
929 case BUSSTATE_OFF:
930 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
931 return 0;
932 mcr &= ~TRISTATE_BIT;
933 break;
934 case BUSSTATE_TRISTATE:
935 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
936 return 0;
937 mcr |= TRISTATE_BIT;
938 break;
939 default:
940 return -EINVAL;
941 }
942
943 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
944 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
945
946 pci_write_config_word(dev, mcr_addr, mcr);
947 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
948 return 0;
949 }
950
951 /**
952 * hpt37x_calibrate_dpll - calibrate the DPLL
953 * @dev: PCI device
954 *
955 * Perform a calibration cycle on the DPLL.
956 * Returns 1 if this succeeds
957 */
958 static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
959 {
960 u32 dpll = (f_high << 16) | f_low | 0x100;
961 u8 scr2;
962 int i;
963
964 pci_write_config_dword(dev, 0x5c, dpll);
965
966 /* Wait for oscillator ready */
967 for(i = 0; i < 0x5000; ++i) {
968 udelay(50);
969 pci_read_config_byte(dev, 0x5b, &scr2);
970 if (scr2 & 0x80)
971 break;
972 }
973 /* See if it stays ready (we'll just bail out if it's not yet) */
974 for(i = 0; i < 0x1000; ++i) {
975 pci_read_config_byte(dev, 0x5b, &scr2);
976 /* DPLL destabilized? */
977 if(!(scr2 & 0x80))
978 return 0;
979 }
980 /* Turn off tuning, we have the DPLL set */
981 pci_read_config_dword (dev, 0x5c, &dpll);
982 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
983 return 1;
984 }
985
986 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
987 {
988 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
989 unsigned long io_base = pci_resource_start(dev, 4);
990 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
991 u8 chip_type;
992 enum ata_clock clock;
993
994 if (info == NULL) {
995 printk(KERN_ERR "%s: out of memory!\n", name);
996 return -ENOMEM;
997 }
998
999 /*
1000 * Copy everything from a static "template" structure
1001 * to just allocated per-chip hpt_info structure.
1002 */
1003 memcpy(info, pci_get_drvdata(dev), sizeof(struct hpt_info));
1004 chip_type = info->chip_type;
1005
1006 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1007 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1008 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1009 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1010
1011 /*
1012 * First, try to estimate the PCI clock frequency...
1013 */
1014 if (chip_type >= HPT370) {
1015 u8 scr1 = 0;
1016 u16 f_cnt = 0;
1017 u32 temp = 0;
1018
1019 /* Interrupt force enable. */
1020 pci_read_config_byte(dev, 0x5a, &scr1);
1021 if (scr1 & 0x10)
1022 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1023
1024 /*
1025 * HighPoint does this for HPT372A.
1026 * NOTE: This register is only writeable via I/O space.
1027 */
1028 if (chip_type == HPT372A)
1029 outb(0x0e, io_base + 0x9c);
1030
1031 /*
1032 * Default to PCI clock. Make sure MA15/16 are set to output
1033 * to prevent drives having problems with 40-pin cables.
1034 */
1035 pci_write_config_byte(dev, 0x5b, 0x23);
1036
1037 /*
1038 * We'll have to read f_CNT value in order to determine
1039 * the PCI clock frequency according to the following ratio:
1040 *
1041 * f_CNT = Fpci * 192 / Fdpll
1042 *
1043 * First try reading the register in which the HighPoint BIOS
1044 * saves f_CNT value before reprogramming the DPLL from its
1045 * default setting (which differs for the various chips).
1046 *
1047 * NOTE: This register is only accessible via I/O space;
1048 * HPT374 BIOS only saves it for the function 0, so we have to
1049 * always read it from there -- no need to check the result of
1050 * pci_get_slot() for the function 0 as the whole device has
1051 * been already "pinned" (via function 1) in init_setup_hpt374()
1052 */
1053 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1054 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1055 dev->devfn - 1);
1056 unsigned long io_base = pci_resource_start(dev1, 4);
1057
1058 temp = inl(io_base + 0x90);
1059 pci_dev_put(dev1);
1060 } else
1061 temp = inl(io_base + 0x90);
1062
1063 /*
1064 * In case the signature check fails, we'll have to
1065 * resort to reading the f_CNT register itself in hopes
1066 * that nobody has touched the DPLL yet...
1067 */
1068 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1069 int i;
1070
1071 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1072 name);
1073
1074 /* Calculate the average value of f_CNT. */
1075 for (temp = i = 0; i < 128; i++) {
1076 pci_read_config_word(dev, 0x78, &f_cnt);
1077 temp += f_cnt & 0x1ff;
1078 mdelay(1);
1079 }
1080 f_cnt = temp / 128;
1081 } else
1082 f_cnt = temp & 0x1ff;
1083
1084 dpll_clk = info->dpll_clk;
1085 pci_clk = (f_cnt * dpll_clk) / 192;
1086
1087 /* Clamp PCI clock to bands. */
1088 if (pci_clk < 40)
1089 pci_clk = 33;
1090 else if(pci_clk < 45)
1091 pci_clk = 40;
1092 else if(pci_clk < 55)
1093 pci_clk = 50;
1094 else
1095 pci_clk = 66;
1096
1097 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1098 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1099 } else {
1100 u32 itr1 = 0;
1101
1102 pci_read_config_dword(dev, 0x40, &itr1);
1103
1104 /* Detect PCI clock by looking at cmd_high_time. */
1105 switch((itr1 >> 8) & 0x07) {
1106 case 0x09:
1107 pci_clk = 40;
1108 break;
1109 case 0x05:
1110 pci_clk = 25;
1111 break;
1112 case 0x07:
1113 default:
1114 pci_clk = 33;
1115 break;
1116 }
1117 }
1118
1119 /* Let's assume we'll use PCI clock for the ATA clock... */
1120 switch (pci_clk) {
1121 case 25:
1122 clock = ATA_CLOCK_25MHZ;
1123 break;
1124 case 33:
1125 default:
1126 clock = ATA_CLOCK_33MHZ;
1127 break;
1128 case 40:
1129 clock = ATA_CLOCK_40MHZ;
1130 break;
1131 case 50:
1132 clock = ATA_CLOCK_50MHZ;
1133 break;
1134 case 66:
1135 clock = ATA_CLOCK_66MHZ;
1136 break;
1137 }
1138
1139 /*
1140 * Only try the DPLL if we don't have a table for the PCI clock that
1141 * we are running at for HPT370/A, always use it for anything newer...
1142 *
1143 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1144 * We also don't like using the DPLL because this causes glitches
1145 * on PRST-/SRST- when the state engine gets reset...
1146 */
1147 if (chip_type >= HPT374 || info->settings[clock] == NULL) {
1148 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1149 int adjust;
1150
1151 /*
1152 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1153 * supported/enabled, use 50 MHz DPLL clock otherwise...
1154 */
1155 if (info->max_ultra == 6) {
1156 dpll_clk = 66;
1157 clock = ATA_CLOCK_66MHZ;
1158 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1159 dpll_clk = 50;
1160 clock = ATA_CLOCK_50MHZ;
1161 }
1162
1163 if (info->settings[clock] == NULL) {
1164 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1165 kfree(info);
1166 return -EIO;
1167 }
1168
1169 /* Select the DPLL clock. */
1170 pci_write_config_byte(dev, 0x5b, 0x21);
1171
1172 /*
1173 * Adjust the DPLL based upon PCI clock, enable it,
1174 * and wait for stabilization...
1175 */
1176 f_low = (pci_clk * 48) / dpll_clk;
1177
1178 for (adjust = 0; adjust < 8; adjust++) {
1179 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1180 break;
1181
1182 /*
1183 * See if it'll settle at a fractionally different clock
1184 */
1185 if (adjust & 1)
1186 f_low -= adjust >> 1;
1187 else
1188 f_low += adjust >> 1;
1189 }
1190 if (adjust == 8) {
1191 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1192 kfree(info);
1193 return -EIO;
1194 }
1195
1196 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1197 } else {
1198 /* Mark the fact that we're not using the DPLL. */
1199 dpll_clk = 0;
1200
1201 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1202 }
1203
1204 /*
1205 * Advance the table pointer to a slot which points to the list
1206 * of the register values settings matching the clock being used.
1207 */
1208 info->settings += clock;
1209
1210 /* Store the clock frequencies. */
1211 info->dpll_clk = dpll_clk;
1212 info->pci_clk = pci_clk;
1213
1214 /* Point to this chip's own instance of the hpt_info structure. */
1215 pci_set_drvdata(dev, info);
1216
1217 if (chip_type >= HPT370) {
1218 u8 mcr1, mcr4;
1219
1220 /*
1221 * Reset the state engines.
1222 * NOTE: Avoid accidentally enabling the disabled channels.
1223 */
1224 pci_read_config_byte (dev, 0x50, &mcr1);
1225 pci_read_config_byte (dev, 0x54, &mcr4);
1226 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1227 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1228 udelay(100);
1229 }
1230
1231 /*
1232 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1233 * the MISC. register to stretch the UltraDMA Tss timing.
1234 * NOTE: This register is only writeable via I/O space.
1235 */
1236 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1237
1238 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1239
1240 return dev->irq;
1241 }
1242
1243 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1244 {
1245 struct pci_dev *dev = hwif->pci_dev;
1246 struct hpt_info *info = pci_get_drvdata(dev);
1247 int serialize = HPT_SERIALIZE_IO;
1248 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1249 u8 chip_type = info->chip_type;
1250 u8 new_mcr, old_mcr = 0;
1251
1252 /* Cache the channel's MISC. control registers' offset */
1253 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1254
1255 hwif->set_pio_mode = &hpt3xx_set_pio_mode;
1256 hwif->set_dma_mode = &hpt3xx_set_mode;
1257 hwif->quirkproc = &hpt3xx_quirkproc;
1258 hwif->intrproc = &hpt3xx_intrproc;
1259 hwif->maskproc = &hpt3xx_maskproc;
1260 hwif->busproc = &hpt3xx_busproc;
1261
1262 hwif->udma_filter = &hpt3xx_udma_filter;
1263 hwif->mdma_filter = &hpt3xx_mdma_filter;
1264
1265 /*
1266 * HPT3xxN chips have some complications:
1267 *
1268 * - on 33 MHz PCI we must clock switch
1269 * - on 66 MHz PCI we must NOT use the PCI clock
1270 */
1271 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1272 /*
1273 * Clock is shared between the channels,
1274 * so we'll have to serialize them... :-(
1275 */
1276 serialize = 1;
1277 hwif->rw_disk = &hpt3xxn_rw_disk;
1278 }
1279
1280 /* Serialize access to this device if needed */
1281 if (serialize && hwif->mate)
1282 hwif->serialized = hwif->mate->serialized = 1;
1283
1284 /*
1285 * Disable the "fast interrupt" prediction. Don't hold off
1286 * on interrupts. (== 0x01 despite what the docs say)
1287 */
1288 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1289
1290 if (info->chip_type >= HPT374)
1291 new_mcr = old_mcr & ~0x07;
1292 else if (info->chip_type >= HPT370) {
1293 new_mcr = old_mcr;
1294 new_mcr &= ~0x02;
1295
1296 #ifdef HPT_DELAY_INTERRUPT
1297 new_mcr &= ~0x01;
1298 #else
1299 new_mcr |= 0x01;
1300 #endif
1301 } else /* HPT366 and HPT368 */
1302 new_mcr = old_mcr & ~0x80;
1303
1304 if (new_mcr != old_mcr)
1305 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1306
1307 if (!hwif->dma_base) {
1308 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1309 return;
1310 }
1311
1312 hwif->ultra_mask = hwif->cds->udma_mask;
1313 hwif->mwdma_mask = 0x07;
1314
1315 /*
1316 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1317 * address lines to access an external EEPROM. To read valid
1318 * cable detect state the pins must be enabled as inputs.
1319 */
1320 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1321 /*
1322 * HPT374 PCI function 1
1323 * - set bit 15 of reg 0x52 to enable TCBLID as input
1324 * - set bit 15 of reg 0x56 to enable FCBLID as input
1325 */
1326 u8 mcr_addr = hwif->select_data + 2;
1327 u16 mcr;
1328
1329 pci_read_config_word (dev, mcr_addr, &mcr);
1330 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1331 /* now read cable id register */
1332 pci_read_config_byte (dev, 0x5a, &scr1);
1333 pci_write_config_word(dev, mcr_addr, mcr);
1334 } else if (chip_type >= HPT370) {
1335 /*
1336 * HPT370/372 and 374 pcifn 0
1337 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1338 */
1339 u8 scr2 = 0;
1340
1341 pci_read_config_byte (dev, 0x5b, &scr2);
1342 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1343 /* now read cable id register */
1344 pci_read_config_byte (dev, 0x5a, &scr1);
1345 pci_write_config_byte(dev, 0x5b, scr2);
1346 } else
1347 pci_read_config_byte (dev, 0x5a, &scr1);
1348
1349 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
1350 hwif->cbl = (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1351
1352 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1353
1354 if (chip_type >= HPT374) {
1355 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1356 hwif->ide_dma_end = &hpt374_ide_dma_end;
1357 } else if (chip_type >= HPT370) {
1358 hwif->dma_start = &hpt370_ide_dma_start;
1359 hwif->ide_dma_end = &hpt370_ide_dma_end;
1360 hwif->dma_timeout = &hpt370_dma_timeout;
1361 } else
1362 hwif->dma_lost_irq = &hpt366_dma_lost_irq;
1363
1364 if (!noautodma)
1365 hwif->autodma = 1;
1366 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1367 }
1368
1369 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1370 {
1371 struct pci_dev *dev = hwif->pci_dev;
1372 u8 masterdma = 0, slavedma = 0;
1373 u8 dma_new = 0, dma_old = 0;
1374 unsigned long flags;
1375
1376 dma_old = hwif->INB(dmabase + 2);
1377
1378 local_irq_save(flags);
1379
1380 dma_new = dma_old;
1381 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1382 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1383
1384 if (masterdma & 0x30) dma_new |= 0x20;
1385 if ( slavedma & 0x30) dma_new |= 0x40;
1386 if (dma_new != dma_old)
1387 hwif->OUTB(dma_new, dmabase + 2);
1388
1389 local_irq_restore(flags);
1390
1391 ide_setup_dma(hwif, dmabase, 8);
1392 }
1393
1394 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1395 {
1396 struct pci_dev *dev2;
1397
1398 if (PCI_FUNC(dev->devfn) & 1)
1399 return -ENODEV;
1400
1401 pci_set_drvdata(dev, &hpt374);
1402
1403 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1404 int ret;
1405
1406 pci_set_drvdata(dev2, &hpt374);
1407
1408 if (dev2->irq != dev->irq) {
1409 /* FIXME: we need a core pci_set_interrupt() */
1410 dev2->irq = dev->irq;
1411 printk(KERN_WARNING "%s: PCI config space interrupt "
1412 "fixed.\n", d->name);
1413 }
1414 ret = ide_setup_pci_devices(dev, dev2, d);
1415 if (ret < 0)
1416 pci_dev_put(dev2);
1417 return ret;
1418 }
1419 return ide_setup_pci_device(dev, d);
1420 }
1421
1422 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1423 {
1424 pci_set_drvdata(dev, &hpt372n);
1425
1426 return ide_setup_pci_device(dev, d);
1427 }
1428
1429 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1430 {
1431 struct hpt_info *info;
1432 u8 mcr1 = 0;
1433
1434 if (dev->revision > 1) {
1435 d->name = "HPT371N";
1436
1437 info = &hpt371n;
1438 } else
1439 info = &hpt371;
1440
1441 /*
1442 * HPT371 chips physically have only one channel, the secondary one,
1443 * but the primary channel registers do exist! Go figure...
1444 * So, we manually disable the non-existing channel here
1445 * (if the BIOS hasn't done this already).
1446 */
1447 pci_read_config_byte(dev, 0x50, &mcr1);
1448 if (mcr1 & 0x04)
1449 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1450
1451 pci_set_drvdata(dev, info);
1452
1453 return ide_setup_pci_device(dev, d);
1454 }
1455
1456 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1457 {
1458 struct hpt_info *info;
1459
1460 if (dev->revision > 1) {
1461 d->name = "HPT372N";
1462
1463 info = &hpt372n;
1464 } else
1465 info = &hpt372a;
1466 pci_set_drvdata(dev, info);
1467
1468 return ide_setup_pci_device(dev, d);
1469 }
1470
1471 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1472 {
1473 struct hpt_info *info;
1474
1475 if (dev->revision > 1) {
1476 d->name = "HPT302N";
1477
1478 info = &hpt302n;
1479 } else
1480 info = &hpt302;
1481 pci_set_drvdata(dev, info);
1482
1483 return ide_setup_pci_device(dev, d);
1484 }
1485
1486 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1487 {
1488 struct pci_dev *dev2;
1489 u8 rev = dev->revision;
1490 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
1491 "HPT370", "HPT370A", "HPT372",
1492 "HPT372N" };
1493 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
1494 &hpt370, &hpt370a, &hpt372,
1495 &hpt372n };
1496
1497 if (PCI_FUNC(dev->devfn) & 1)
1498 return -ENODEV;
1499
1500 switch (rev) {
1501 case 0:
1502 case 1:
1503 case 2:
1504 /*
1505 * HPT36x chips have one channel per function and have
1506 * both channel enable bits located differently and visible
1507 * to both functions -- really stupid design decision... :-(
1508 * Bit 4 is for the primary channel, bit 5 for the secondary.
1509 */
1510 d->host_flags |= IDE_HFLAG_SINGLE;
1511 d->enablebits[0].mask = d->enablebits[0].val = 0x10;
1512
1513 d->udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ?
1514 ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2;
1515 break;
1516 case 3:
1517 case 4:
1518 d->udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4;
1519 break;
1520 default:
1521 rev = 6;
1522 /* fall thru */
1523 case 5:
1524 case 6:
1525 d->udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5;
1526 break;
1527 }
1528
1529 d->name = chipset_names[rev];
1530
1531 pci_set_drvdata(dev, info[rev]);
1532
1533 if (rev > 2)
1534 goto init_single;
1535
1536 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1537 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1538 int ret;
1539
1540 pci_set_drvdata(dev2, info[rev]);
1541
1542 /*
1543 * Now we'll have to force both channels enabled if
1544 * at least one of them has been enabled by BIOS...
1545 */
1546 pci_read_config_byte(dev, 0x50, &mcr1);
1547 if (mcr1 & 0x30)
1548 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1549
1550 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1551 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1552 if (pin1 != pin2 && dev->irq == dev2->irq) {
1553 d->bootable = ON_BOARD;
1554 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1555 d->name, pin1, pin2);
1556 }
1557 ret = ide_setup_pci_devices(dev, dev2, d);
1558 if (ret < 0)
1559 pci_dev_put(dev2);
1560 return ret;
1561 }
1562 init_single:
1563 return ide_setup_pci_device(dev, d);
1564 }
1565
1566 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1567 { /* 0 */
1568 .name = "HPT366",
1569 .init_setup = init_setup_hpt366,
1570 .init_chipset = init_chipset_hpt366,
1571 .init_hwif = init_hwif_hpt366,
1572 .init_dma = init_dma_hpt366,
1573 .autodma = AUTODMA,
1574 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1575 .bootable = OFF_BOARD,
1576 .extra = 240,
1577 .pio_mask = ATA_PIO4,
1578 },{ /* 1 */
1579 .name = "HPT372A",
1580 .init_setup = init_setup_hpt372a,
1581 .init_chipset = init_chipset_hpt366,
1582 .init_hwif = init_hwif_hpt366,
1583 .init_dma = init_dma_hpt366,
1584 .autodma = AUTODMA,
1585 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1586 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1587 .bootable = OFF_BOARD,
1588 .extra = 240,
1589 .pio_mask = ATA_PIO4,
1590 },{ /* 2 */
1591 .name = "HPT302",
1592 .init_setup = init_setup_hpt302,
1593 .init_chipset = init_chipset_hpt366,
1594 .init_hwif = init_hwif_hpt366,
1595 .init_dma = init_dma_hpt366,
1596 .autodma = AUTODMA,
1597 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1598 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1599 .bootable = OFF_BOARD,
1600 .extra = 240,
1601 .pio_mask = ATA_PIO4,
1602 },{ /* 3 */
1603 .name = "HPT371",
1604 .init_setup = init_setup_hpt371,
1605 .init_chipset = init_chipset_hpt366,
1606 .init_hwif = init_hwif_hpt366,
1607 .init_dma = init_dma_hpt366,
1608 .autodma = AUTODMA,
1609 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1610 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1611 .bootable = OFF_BOARD,
1612 .extra = 240,
1613 .pio_mask = ATA_PIO4,
1614 },{ /* 4 */
1615 .name = "HPT374",
1616 .init_setup = init_setup_hpt374,
1617 .init_chipset = init_chipset_hpt366,
1618 .init_hwif = init_hwif_hpt366,
1619 .init_dma = init_dma_hpt366,
1620 .autodma = AUTODMA,
1621 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1622 .udma_mask = ATA_UDMA5,
1623 .bootable = OFF_BOARD,
1624 .extra = 240,
1625 .pio_mask = ATA_PIO4,
1626 },{ /* 5 */
1627 .name = "HPT372N",
1628 .init_setup = init_setup_hpt372n,
1629 .init_chipset = init_chipset_hpt366,
1630 .init_hwif = init_hwif_hpt366,
1631 .init_dma = init_dma_hpt366,
1632 .autodma = AUTODMA,
1633 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1634 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
1635 .bootable = OFF_BOARD,
1636 .extra = 240,
1637 .pio_mask = ATA_PIO4,
1638 }
1639 };
1640
1641 /**
1642 * hpt366_init_one - called when an HPT366 is found
1643 * @dev: the hpt366 device
1644 * @id: the matching pci id
1645 *
1646 * Called when the PCI registration layer (or the IDE initialization)
1647 * finds a device matching our IDE device tables.
1648 *
1649 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1650 * structure depending on the chip's revision, we'd better pass a local
1651 * copy down the call chain...
1652 */
1653 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1654 {
1655 ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1656
1657 return d.init_setup(dev, &d);
1658 }
1659
1660 static struct pci_device_id hpt366_pci_tbl[] = {
1661 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1662 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1663 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1664 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1665 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1666 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1667 { 0, },
1668 };
1669 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1670
1671 static struct pci_driver driver = {
1672 .name = "HPT366_IDE",
1673 .id_table = hpt366_pci_tbl,
1674 .probe = hpt366_init_one,
1675 };
1676
1677 static int __init hpt366_ide_init(void)
1678 {
1679 return ide_pci_register_driver(&driver);
1680 }
1681
1682 module_init(hpt366_ide_init);
1683
1684 MODULE_AUTHOR("Andre Hedrick");
1685 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1686 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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