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Merge git://git.infradead.org/mtd-2.6
[deliverable/linux.git] / drivers / ide / pci / hpt366.c
1 /*
2 * linux/drivers/ide/pci/hpt366.c Version 1.03 May 4, 2007
3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2007 MontaVista Software, Inc.
8 *
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
13 *
14 *
15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
20 *
21 * Note that final HPT370 support was done by force extraction of GPL.
22 *
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
37 *
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
43 *
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
46 *
47 * On hpt366:
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
51 *
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
55 * keeping me sane.
56 * Alan Cox <alan@redhat.com>
57 *
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
64 * does not allow for this speed anyway
65 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
66 * their primary channel is kind of virtual, it isn't tied to any pins)
67 * - fix/remove bad/unused timing tables and use one set of tables for the whole
68 * HPT37x chip family; save space by introducing the separate transfer mode
69 * table in which the mode lookup is done
70 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
71 * the wrong PCI frequency since DPLL has already been calibrated by BIOS
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the rate masking/filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
85 * function 1
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
97 * init_setup stage
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * supported DMA mode, and the chip settings table pointer filled, then, at
103 * the init_chipset stage, allocate per-chip instance and fill it with the
104 * rest of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A
110 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
111 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
112 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
113 * the register setting lists into the table indexed by the clock selected
114 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
115 */
116
117 #include <linux/types.h>
118 #include <linux/module.h>
119 #include <linux/kernel.h>
120 #include <linux/delay.h>
121 #include <linux/timer.h>
122 #include <linux/mm.h>
123 #include <linux/ioport.h>
124 #include <linux/blkdev.h>
125 #include <linux/hdreg.h>
126
127 #include <linux/interrupt.h>
128 #include <linux/pci.h>
129 #include <linux/init.h>
130 #include <linux/ide.h>
131
132 #include <asm/uaccess.h>
133 #include <asm/io.h>
134 #include <asm/irq.h>
135
136 /* various tuning parameters */
137 #define HPT_RESET_STATE_ENGINE
138 #undef HPT_DELAY_INTERRUPT
139 #define HPT_SERIALIZE_IO 0
140
141 static const char *quirk_drives[] = {
142 "QUANTUM FIREBALLlct08 08",
143 "QUANTUM FIREBALLP KA6.4",
144 "QUANTUM FIREBALLP LM20.4",
145 "QUANTUM FIREBALLP LM20.5",
146 NULL
147 };
148
149 static const char *bad_ata100_5[] = {
150 "IBM-DTLA-307075",
151 "IBM-DTLA-307060",
152 "IBM-DTLA-307045",
153 "IBM-DTLA-307030",
154 "IBM-DTLA-307020",
155 "IBM-DTLA-307015",
156 "IBM-DTLA-305040",
157 "IBM-DTLA-305030",
158 "IBM-DTLA-305020",
159 "IC35L010AVER07-0",
160 "IC35L020AVER07-0",
161 "IC35L030AVER07-0",
162 "IC35L040AVER07-0",
163 "IC35L060AVER07-0",
164 "WDC AC310200R",
165 NULL
166 };
167
168 static const char *bad_ata66_4[] = {
169 "IBM-DTLA-307075",
170 "IBM-DTLA-307060",
171 "IBM-DTLA-307045",
172 "IBM-DTLA-307030",
173 "IBM-DTLA-307020",
174 "IBM-DTLA-307015",
175 "IBM-DTLA-305040",
176 "IBM-DTLA-305030",
177 "IBM-DTLA-305020",
178 "IC35L010AVER07-0",
179 "IC35L020AVER07-0",
180 "IC35L030AVER07-0",
181 "IC35L040AVER07-0",
182 "IC35L060AVER07-0",
183 "WDC AC310200R",
184 NULL
185 };
186
187 static const char *bad_ata66_3[] = {
188 "WDC AC310200R",
189 NULL
190 };
191
192 static const char *bad_ata33[] = {
193 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
194 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
195 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
196 "Maxtor 90510D4",
197 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
198 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
199 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
200 NULL
201 };
202
203 static u8 xfer_speeds[] = {
204 XFER_UDMA_6,
205 XFER_UDMA_5,
206 XFER_UDMA_4,
207 XFER_UDMA_3,
208 XFER_UDMA_2,
209 XFER_UDMA_1,
210 XFER_UDMA_0,
211
212 XFER_MW_DMA_2,
213 XFER_MW_DMA_1,
214 XFER_MW_DMA_0,
215
216 XFER_PIO_4,
217 XFER_PIO_3,
218 XFER_PIO_2,
219 XFER_PIO_1,
220 XFER_PIO_0
221 };
222
223 /* Key for bus clock timings
224 * 36x 37x
225 * bits bits
226 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
227 * cycles = value + 1
228 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
229 * cycles = value + 1
230 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
231 * register access.
232 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
233 * register access.
234 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
235 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
236 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
237 * MW DMA xfer.
238 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
239 * task file register access.
240 * 28 28 UDMA enable.
241 * 29 29 DMA enable.
242 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
243 * PIO xfer.
244 * 31 31 FIFO enable.
245 */
246
247 static u32 forty_base_hpt36x[] = {
248 /* XFER_UDMA_6 */ 0x900fd943,
249 /* XFER_UDMA_5 */ 0x900fd943,
250 /* XFER_UDMA_4 */ 0x900fd943,
251 /* XFER_UDMA_3 */ 0x900ad943,
252 /* XFER_UDMA_2 */ 0x900bd943,
253 /* XFER_UDMA_1 */ 0x9008d943,
254 /* XFER_UDMA_0 */ 0x9008d943,
255
256 /* XFER_MW_DMA_2 */ 0xa008d943,
257 /* XFER_MW_DMA_1 */ 0xa010d955,
258 /* XFER_MW_DMA_0 */ 0xa010d9fc,
259
260 /* XFER_PIO_4 */ 0xc008d963,
261 /* XFER_PIO_3 */ 0xc010d974,
262 /* XFER_PIO_2 */ 0xc010d997,
263 /* XFER_PIO_1 */ 0xc010d9c7,
264 /* XFER_PIO_0 */ 0xc018d9d9
265 };
266
267 static u32 thirty_three_base_hpt36x[] = {
268 /* XFER_UDMA_6 */ 0x90c9a731,
269 /* XFER_UDMA_5 */ 0x90c9a731,
270 /* XFER_UDMA_4 */ 0x90c9a731,
271 /* XFER_UDMA_3 */ 0x90cfa731,
272 /* XFER_UDMA_2 */ 0x90caa731,
273 /* XFER_UDMA_1 */ 0x90cba731,
274 /* XFER_UDMA_0 */ 0x90c8a731,
275
276 /* XFER_MW_DMA_2 */ 0xa0c8a731,
277 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
278 /* XFER_MW_DMA_0 */ 0xa0c8a797,
279
280 /* XFER_PIO_4 */ 0xc0c8a731,
281 /* XFER_PIO_3 */ 0xc0c8a742,
282 /* XFER_PIO_2 */ 0xc0d0a753,
283 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
284 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
285 };
286
287 static u32 twenty_five_base_hpt36x[] = {
288 /* XFER_UDMA_6 */ 0x90c98521,
289 /* XFER_UDMA_5 */ 0x90c98521,
290 /* XFER_UDMA_4 */ 0x90c98521,
291 /* XFER_UDMA_3 */ 0x90cf8521,
292 /* XFER_UDMA_2 */ 0x90cf8521,
293 /* XFER_UDMA_1 */ 0x90cb8521,
294 /* XFER_UDMA_0 */ 0x90cb8521,
295
296 /* XFER_MW_DMA_2 */ 0xa0ca8521,
297 /* XFER_MW_DMA_1 */ 0xa0ca8532,
298 /* XFER_MW_DMA_0 */ 0xa0ca8575,
299
300 /* XFER_PIO_4 */ 0xc0ca8521,
301 /* XFER_PIO_3 */ 0xc0ca8532,
302 /* XFER_PIO_2 */ 0xc0ca8542,
303 /* XFER_PIO_1 */ 0xc0d08572,
304 /* XFER_PIO_0 */ 0xc0d08585
305 };
306
307 static u32 thirty_three_base_hpt37x[] = {
308 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
309 /* XFER_UDMA_5 */ 0x12446231,
310 /* XFER_UDMA_4 */ 0x12446231,
311 /* XFER_UDMA_3 */ 0x126c6231,
312 /* XFER_UDMA_2 */ 0x12486231,
313 /* XFER_UDMA_1 */ 0x124c6233,
314 /* XFER_UDMA_0 */ 0x12506297,
315
316 /* XFER_MW_DMA_2 */ 0x22406c31,
317 /* XFER_MW_DMA_1 */ 0x22406c33,
318 /* XFER_MW_DMA_0 */ 0x22406c97,
319
320 /* XFER_PIO_4 */ 0x06414e31,
321 /* XFER_PIO_3 */ 0x06414e42,
322 /* XFER_PIO_2 */ 0x06414e53,
323 /* XFER_PIO_1 */ 0x06814e93,
324 /* XFER_PIO_0 */ 0x06814ea7
325 };
326
327 static u32 fifty_base_hpt37x[] = {
328 /* XFER_UDMA_6 */ 0x12848242,
329 /* XFER_UDMA_5 */ 0x12848242,
330 /* XFER_UDMA_4 */ 0x12ac8242,
331 /* XFER_UDMA_3 */ 0x128c8242,
332 /* XFER_UDMA_2 */ 0x120c8242,
333 /* XFER_UDMA_1 */ 0x12148254,
334 /* XFER_UDMA_0 */ 0x121882ea,
335
336 /* XFER_MW_DMA_2 */ 0x22808242,
337 /* XFER_MW_DMA_1 */ 0x22808254,
338 /* XFER_MW_DMA_0 */ 0x228082ea,
339
340 /* XFER_PIO_4 */ 0x0a81f442,
341 /* XFER_PIO_3 */ 0x0a81f443,
342 /* XFER_PIO_2 */ 0x0a81f454,
343 /* XFER_PIO_1 */ 0x0ac1f465,
344 /* XFER_PIO_0 */ 0x0ac1f48a
345 };
346
347 static u32 sixty_six_base_hpt37x[] = {
348 /* XFER_UDMA_6 */ 0x1c869c62,
349 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
350 /* XFER_UDMA_4 */ 0x1c8a9c62,
351 /* XFER_UDMA_3 */ 0x1c8e9c62,
352 /* XFER_UDMA_2 */ 0x1c929c62,
353 /* XFER_UDMA_1 */ 0x1c9a9c62,
354 /* XFER_UDMA_0 */ 0x1c829c62,
355
356 /* XFER_MW_DMA_2 */ 0x2c829c62,
357 /* XFER_MW_DMA_1 */ 0x2c829c66,
358 /* XFER_MW_DMA_0 */ 0x2c829d2e,
359
360 /* XFER_PIO_4 */ 0x0c829c62,
361 /* XFER_PIO_3 */ 0x0c829c84,
362 /* XFER_PIO_2 */ 0x0c829ca6,
363 /* XFER_PIO_1 */ 0x0d029d26,
364 /* XFER_PIO_0 */ 0x0d029d5e
365 };
366
367 #define HPT366_DEBUG_DRIVE_INFO 0
368 #define HPT374_ALLOW_ATA133_6 1
369 #define HPT371_ALLOW_ATA133_6 1
370 #define HPT302_ALLOW_ATA133_6 1
371 #define HPT372_ALLOW_ATA133_6 1
372 #define HPT370_ALLOW_ATA100_5 0
373 #define HPT366_ALLOW_ATA66_4 1
374 #define HPT366_ALLOW_ATA66_3 1
375 #define HPT366_MAX_DEVS 8
376
377 /* Supported ATA clock frequencies */
378 enum ata_clock {
379 ATA_CLOCK_25MHZ,
380 ATA_CLOCK_33MHZ,
381 ATA_CLOCK_40MHZ,
382 ATA_CLOCK_50MHZ,
383 ATA_CLOCK_66MHZ,
384 NUM_ATA_CLOCKS
385 };
386
387 /*
388 * Hold all the HighPoint chip information in one place.
389 */
390
391 struct hpt_info {
392 u8 chip_type; /* Chip type */
393 u8 max_mode; /* Speeds allowed */
394 u8 dpll_clk; /* DPLL clock in MHz */
395 u8 pci_clk; /* PCI clock in MHz */
396 u32 **settings; /* Chipset settings table */
397 };
398
399 /* Supported HighPoint chips */
400 enum {
401 HPT36x,
402 HPT370,
403 HPT370A,
404 HPT374,
405 HPT372,
406 HPT372A,
407 HPT302,
408 HPT371,
409 HPT372N,
410 HPT302N,
411 HPT371N
412 };
413
414 static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
415 twenty_five_base_hpt36x,
416 thirty_three_base_hpt36x,
417 forty_base_hpt36x,
418 NULL,
419 NULL
420 };
421
422 static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
423 NULL,
424 thirty_three_base_hpt37x,
425 NULL,
426 fifty_base_hpt37x,
427 sixty_six_base_hpt37x
428 };
429
430 static struct hpt_info hpt36x __devinitdata = {
431 .chip_type = HPT36x,
432 .max_mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1,
433 .dpll_clk = 0, /* no DPLL */
434 .settings = hpt36x_settings
435 };
436
437 static struct hpt_info hpt370 __devinitdata = {
438 .chip_type = HPT370,
439 .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2,
440 .dpll_clk = 48,
441 .settings = hpt37x_settings
442 };
443
444 static struct hpt_info hpt370a __devinitdata = {
445 .chip_type = HPT370A,
446 .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2,
447 .dpll_clk = 48,
448 .settings = hpt37x_settings
449 };
450
451 static struct hpt_info hpt374 __devinitdata = {
452 .chip_type = HPT374,
453 .max_mode = HPT374_ALLOW_ATA133_6 ? 4 : 3,
454 .dpll_clk = 48,
455 .settings = hpt37x_settings
456 };
457
458 static struct hpt_info hpt372 __devinitdata = {
459 .chip_type = HPT372,
460 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
461 .dpll_clk = 55,
462 .settings = hpt37x_settings
463 };
464
465 static struct hpt_info hpt372a __devinitdata = {
466 .chip_type = HPT372A,
467 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
468 .dpll_clk = 66,
469 .settings = hpt37x_settings
470 };
471
472 static struct hpt_info hpt302 __devinitdata = {
473 .chip_type = HPT302,
474 .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3,
475 .dpll_clk = 66,
476 .settings = hpt37x_settings
477 };
478
479 static struct hpt_info hpt371 __devinitdata = {
480 .chip_type = HPT371,
481 .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3,
482 .dpll_clk = 66,
483 .settings = hpt37x_settings
484 };
485
486 static struct hpt_info hpt372n __devinitdata = {
487 .chip_type = HPT372N,
488 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3,
489 .dpll_clk = 77,
490 .settings = hpt37x_settings
491 };
492
493 static struct hpt_info hpt302n __devinitdata = {
494 .chip_type = HPT302N,
495 .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3,
496 .dpll_clk = 77,
497 .settings = hpt37x_settings
498 };
499
500 static struct hpt_info hpt371n __devinitdata = {
501 .chip_type = HPT371N,
502 .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3,
503 .dpll_clk = 77,
504 .settings = hpt37x_settings
505 };
506
507 static int check_in_drive_list(ide_drive_t *drive, const char **list)
508 {
509 struct hd_driveid *id = drive->id;
510
511 while (*list)
512 if (!strcmp(*list++,id->model))
513 return 1;
514 return 0;
515 }
516
517 /*
518 * Note for the future; the SATA hpt37x we must set
519 * either PIO or UDMA modes 0,4,5
520 */
521
522 static u8 hpt3xx_udma_filter(ide_drive_t *drive)
523 {
524 struct hpt_info *info = pci_get_drvdata(HWIF(drive)->pci_dev);
525 u8 chip_type = info->chip_type;
526 u8 mode = info->max_mode;
527 u8 mask;
528
529 switch (mode) {
530 case 0x04:
531 mask = 0x7f;
532 break;
533 case 0x03:
534 mask = 0x3f;
535 if (chip_type >= HPT374)
536 break;
537 if (!check_in_drive_list(drive, bad_ata100_5))
538 goto check_bad_ata33;
539 /* fall thru */
540 case 0x02:
541 mask = 0x1f;
542
543 /*
544 * CHECK ME, Does this need to be changed to HPT374 ??
545 */
546 if (chip_type >= HPT370)
547 goto check_bad_ata33;
548 if (HPT366_ALLOW_ATA66_4 &&
549 !check_in_drive_list(drive, bad_ata66_4))
550 goto check_bad_ata33;
551
552 mask = 0x0f;
553 if (HPT366_ALLOW_ATA66_3 &&
554 !check_in_drive_list(drive, bad_ata66_3))
555 goto check_bad_ata33;
556 /* fall thru */
557 case 0x01:
558 mask = 0x07;
559
560 check_bad_ata33:
561 if (chip_type >= HPT370A)
562 break;
563 if (!check_in_drive_list(drive, bad_ata33))
564 break;
565 /* fall thru */
566 case 0x00:
567 default:
568 mask = 0x00;
569 break;
570 }
571 return mask;
572 }
573
574 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
575 {
576 int i;
577
578 /*
579 * Lookup the transfer mode table to get the index into
580 * the timing table.
581 *
582 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
583 */
584 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
585 if (xfer_speeds[i] == speed)
586 break;
587 /*
588 * NOTE: info->settings only points to the pointer
589 * to the list of the actual register values
590 */
591 return (*info->settings)[i];
592 }
593
594 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
595 {
596 ide_hwif_t *hwif = HWIF(drive);
597 struct pci_dev *dev = hwif->pci_dev;
598 struct hpt_info *info = pci_get_drvdata(dev);
599 u8 speed = ide_rate_filter(drive, xferspeed);
600 u8 itr_addr = drive->dn ? 0x44 : 0x40;
601 u32 old_itr = 0;
602 u32 itr_mask, new_itr;
603
604 /* TODO: move this to ide_rate_filter() [ check ->atapi_dma ] */
605 if (drive->media != ide_disk)
606 speed = min_t(u8, speed, XFER_PIO_4);
607
608 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 :
609 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff);
610
611 new_itr = get_speed_setting(speed, info);
612
613 /*
614 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
615 * to avoid problems handling I/O errors later
616 */
617 pci_read_config_dword(dev, itr_addr, &old_itr);
618 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
619 new_itr &= ~0xc0000000;
620
621 pci_write_config_dword(dev, itr_addr, new_itr);
622
623 return ide_config_drive_speed(drive, speed);
624 }
625
626 static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
627 {
628 ide_hwif_t *hwif = HWIF(drive);
629 struct pci_dev *dev = hwif->pci_dev;
630 struct hpt_info *info = pci_get_drvdata(dev);
631 u8 speed = ide_rate_filter(drive, xferspeed);
632 u8 itr_addr = 0x40 + (drive->dn * 4);
633 u32 old_itr = 0;
634 u32 itr_mask, new_itr;
635
636 /* TODO: move this to ide_rate_filter() [ check ->atapi_dma ] */
637 if (drive->media != ide_disk)
638 speed = min_t(u8, speed, XFER_PIO_4);
639
640 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 :
641 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff);
642
643 new_itr = get_speed_setting(speed, info);
644
645 pci_read_config_dword(dev, itr_addr, &old_itr);
646 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
647
648 if (speed < XFER_MW_DMA_0)
649 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
650 pci_write_config_dword(dev, itr_addr, new_itr);
651
652 return ide_config_drive_speed(drive, speed);
653 }
654
655 static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
656 {
657 ide_hwif_t *hwif = HWIF(drive);
658 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev);
659
660 if (info->chip_type >= HPT370)
661 return hpt37x_tune_chipset(drive, speed);
662 else /* hpt368: hpt_minimum_revision(dev, 2) */
663 return hpt36x_tune_chipset(drive, speed);
664 }
665
666 static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
667 {
668 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
669 (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
670 }
671
672 static int hpt3xx_quirkproc(ide_drive_t *drive)
673 {
674 struct hd_driveid *id = drive->id;
675 const char **list = quirk_drives;
676
677 while (*list)
678 if (strstr(id->model, *list++))
679 return 1;
680 return 0;
681 }
682
683 static void hpt3xx_intrproc(ide_drive_t *drive)
684 {
685 ide_hwif_t *hwif = HWIF(drive);
686
687 if (drive->quirk_list)
688 return;
689 /* drives in the quirk_list may not like intr setups/cleanups */
690 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
691 }
692
693 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
694 {
695 ide_hwif_t *hwif = HWIF(drive);
696 struct pci_dev *dev = hwif->pci_dev;
697 struct hpt_info *info = pci_get_drvdata(dev);
698
699 if (drive->quirk_list) {
700 if (info->chip_type >= HPT370) {
701 u8 scr1 = 0;
702
703 pci_read_config_byte(dev, 0x5a, &scr1);
704 if (((scr1 & 0x10) >> 4) != mask) {
705 if (mask)
706 scr1 |= 0x10;
707 else
708 scr1 &= ~0x10;
709 pci_write_config_byte(dev, 0x5a, scr1);
710 }
711 } else {
712 if (mask)
713 disable_irq(hwif->irq);
714 else
715 enable_irq (hwif->irq);
716 }
717 } else
718 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
719 IDE_CONTROL_REG);
720 }
721
722 static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
723 {
724 drive->init_speed = 0;
725
726 if (ide_tune_dma(drive))
727 return 0;
728
729 if (ide_use_fast_pio(drive))
730 hpt3xx_tune_drive(drive, 255);
731
732 return -1;
733 }
734
735 /*
736 * This is specific to the HPT366 UDMA chipset
737 * by HighPoint|Triones Technologies, Inc.
738 */
739 static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
740 {
741 struct pci_dev *dev = HWIF(drive)->pci_dev;
742 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
743
744 pci_read_config_byte(dev, 0x50, &mcr1);
745 pci_read_config_byte(dev, 0x52, &mcr3);
746 pci_read_config_byte(dev, 0x5a, &scr1);
747 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
748 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
749 if (scr1 & 0x10)
750 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
751 return __ide_dma_lostirq(drive);
752 }
753
754 static void hpt370_clear_engine(ide_drive_t *drive)
755 {
756 ide_hwif_t *hwif = HWIF(drive);
757
758 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
759 udelay(10);
760 }
761
762 static void hpt370_irq_timeout(ide_drive_t *drive)
763 {
764 ide_hwif_t *hwif = HWIF(drive);
765 u16 bfifo = 0;
766 u8 dma_cmd;
767
768 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
769 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
770
771 /* get DMA command mode */
772 dma_cmd = hwif->INB(hwif->dma_command);
773 /* stop DMA */
774 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
775 hpt370_clear_engine(drive);
776 }
777
778 static void hpt370_ide_dma_start(ide_drive_t *drive)
779 {
780 #ifdef HPT_RESET_STATE_ENGINE
781 hpt370_clear_engine(drive);
782 #endif
783 ide_dma_start(drive);
784 }
785
786 static int hpt370_ide_dma_end(ide_drive_t *drive)
787 {
788 ide_hwif_t *hwif = HWIF(drive);
789 u8 dma_stat = hwif->INB(hwif->dma_status);
790
791 if (dma_stat & 0x01) {
792 /* wait a little */
793 udelay(20);
794 dma_stat = hwif->INB(hwif->dma_status);
795 if (dma_stat & 0x01)
796 hpt370_irq_timeout(drive);
797 }
798 return __ide_dma_end(drive);
799 }
800
801 static int hpt370_ide_dma_timeout(ide_drive_t *drive)
802 {
803 hpt370_irq_timeout(drive);
804 return __ide_dma_timeout(drive);
805 }
806
807 /* returns 1 if DMA IRQ issued, 0 otherwise */
808 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
809 {
810 ide_hwif_t *hwif = HWIF(drive);
811 u16 bfifo = 0;
812 u8 dma_stat;
813
814 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
815 if (bfifo & 0x1FF) {
816 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
817 return 0;
818 }
819
820 dma_stat = inb(hwif->dma_status);
821 /* return 1 if INTR asserted */
822 if (dma_stat & 4)
823 return 1;
824
825 if (!drive->waiting_for_dma)
826 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
827 drive->name, __FUNCTION__);
828 return 0;
829 }
830
831 static int hpt374_ide_dma_end(ide_drive_t *drive)
832 {
833 ide_hwif_t *hwif = HWIF(drive);
834 struct pci_dev *dev = hwif->pci_dev;
835 u8 mcr = 0, mcr_addr = hwif->select_data;
836 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
837
838 pci_read_config_byte(dev, 0x6a, &bwsr);
839 pci_read_config_byte(dev, mcr_addr, &mcr);
840 if (bwsr & mask)
841 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
842 return __ide_dma_end(drive);
843 }
844
845 /**
846 * hpt3xxn_set_clock - perform clock switching dance
847 * @hwif: hwif to switch
848 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
849 *
850 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
851 */
852
853 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
854 {
855 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
856
857 if ((scr2 & 0x7f) == mode)
858 return;
859
860 /* Tristate the bus */
861 hwif->OUTB(0x80, hwif->dma_master + 0x73);
862 hwif->OUTB(0x80, hwif->dma_master + 0x77);
863
864 /* Switch clock and reset channels */
865 hwif->OUTB(mode, hwif->dma_master + 0x7b);
866 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
867
868 /*
869 * Reset the state machines.
870 * NOTE: avoid accidentally enabling the disabled channels.
871 */
872 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
873 hwif->dma_master + 0x70);
874 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
875 hwif->dma_master + 0x74);
876
877 /* Complete reset */
878 hwif->OUTB(0x00, hwif->dma_master + 0x79);
879
880 /* Reconnect channels to bus */
881 hwif->OUTB(0x00, hwif->dma_master + 0x73);
882 hwif->OUTB(0x00, hwif->dma_master + 0x77);
883 }
884
885 /**
886 * hpt3xxn_rw_disk - prepare for I/O
887 * @drive: drive for command
888 * @rq: block request structure
889 *
890 * This is called when a disk I/O is issued to HPT3xxN.
891 * We need it because of the clock switching.
892 */
893
894 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
895 {
896 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
897 }
898
899 /*
900 * Set/get power state for a drive.
901 * NOTE: affects both drives on each channel.
902 *
903 * When we turn the power back on, we need to re-initialize things.
904 */
905 #define TRISTATE_BIT 0x8000
906
907 static int hpt3xx_busproc(ide_drive_t *drive, int state)
908 {
909 ide_hwif_t *hwif = HWIF(drive);
910 struct pci_dev *dev = hwif->pci_dev;
911 u8 mcr_addr = hwif->select_data + 2;
912 u8 resetmask = hwif->channel ? 0x80 : 0x40;
913 u8 bsr2 = 0;
914 u16 mcr = 0;
915
916 hwif->bus_state = state;
917
918 /* Grab the status. */
919 pci_read_config_word(dev, mcr_addr, &mcr);
920 pci_read_config_byte(dev, 0x59, &bsr2);
921
922 /*
923 * Set the state. We don't set it if we don't need to do so.
924 * Make sure that the drive knows that it has failed if it's off.
925 */
926 switch (state) {
927 case BUSSTATE_ON:
928 if (!(bsr2 & resetmask))
929 return 0;
930 hwif->drives[0].failures = hwif->drives[1].failures = 0;
931
932 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
933 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
934 return 0;
935 case BUSSTATE_OFF:
936 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
937 return 0;
938 mcr &= ~TRISTATE_BIT;
939 break;
940 case BUSSTATE_TRISTATE:
941 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT))
942 return 0;
943 mcr |= TRISTATE_BIT;
944 break;
945 default:
946 return -EINVAL;
947 }
948
949 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
950 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
951
952 pci_write_config_word(dev, mcr_addr, mcr);
953 pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
954 return 0;
955 }
956
957 /**
958 * hpt37x_calibrate_dpll - calibrate the DPLL
959 * @dev: PCI device
960 *
961 * Perform a calibration cycle on the DPLL.
962 * Returns 1 if this succeeds
963 */
964 static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
965 {
966 u32 dpll = (f_high << 16) | f_low | 0x100;
967 u8 scr2;
968 int i;
969
970 pci_write_config_dword(dev, 0x5c, dpll);
971
972 /* Wait for oscillator ready */
973 for(i = 0; i < 0x5000; ++i) {
974 udelay(50);
975 pci_read_config_byte(dev, 0x5b, &scr2);
976 if (scr2 & 0x80)
977 break;
978 }
979 /* See if it stays ready (we'll just bail out if it's not yet) */
980 for(i = 0; i < 0x1000; ++i) {
981 pci_read_config_byte(dev, 0x5b, &scr2);
982 /* DPLL destabilized? */
983 if(!(scr2 & 0x80))
984 return 0;
985 }
986 /* Turn off tuning, we have the DPLL set */
987 pci_read_config_dword (dev, 0x5c, &dpll);
988 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
989 return 1;
990 }
991
992 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
993 {
994 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
995 unsigned long io_base = pci_resource_start(dev, 4);
996 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
997 enum ata_clock clock;
998
999 if (info == NULL) {
1000 printk(KERN_ERR "%s: out of memory!\n", name);
1001 return -ENOMEM;
1002 }
1003
1004 /*
1005 * Copy everything from a static "template" structure
1006 * to just allocated per-chip hpt_info structure.
1007 */
1008 *info = *(struct hpt_info *)pci_get_drvdata(dev);
1009
1010 /*
1011 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1012 * We don't seem to be using it.
1013 */
1014 if (dev->resource[PCI_ROM_RESOURCE].start)
1015 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1016 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1017
1018 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1019 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1020 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1021 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1022
1023 /*
1024 * First, try to estimate the PCI clock frequency...
1025 */
1026 if (info->chip_type >= HPT370) {
1027 u8 scr1 = 0;
1028 u16 f_cnt = 0;
1029 u32 temp = 0;
1030
1031 /* Interrupt force enable. */
1032 pci_read_config_byte(dev, 0x5a, &scr1);
1033 if (scr1 & 0x10)
1034 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1035
1036 /*
1037 * HighPoint does this for HPT372A.
1038 * NOTE: This register is only writeable via I/O space.
1039 */
1040 if (info->chip_type == HPT372A)
1041 outb(0x0e, io_base + 0x9c);
1042
1043 /*
1044 * Default to PCI clock. Make sure MA15/16 are set to output
1045 * to prevent drives having problems with 40-pin cables.
1046 */
1047 pci_write_config_byte(dev, 0x5b, 0x23);
1048
1049 /*
1050 * We'll have to read f_CNT value in order to determine
1051 * the PCI clock frequency according to the following ratio:
1052 *
1053 * f_CNT = Fpci * 192 / Fdpll
1054 *
1055 * First try reading the register in which the HighPoint BIOS
1056 * saves f_CNT value before reprogramming the DPLL from its
1057 * default setting (which differs for the various chips).
1058 * NOTE: This register is only accessible via I/O space.
1059 *
1060 * In case the signature check fails, we'll have to resort to
1061 * reading the f_CNT register itself in hopes that nobody has
1062 * touched the DPLL yet...
1063 */
1064 temp = inl(io_base + 0x90);
1065 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1066 int i;
1067
1068 printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1069 name);
1070
1071 /* Calculate the average value of f_CNT. */
1072 for (temp = i = 0; i < 128; i++) {
1073 pci_read_config_word(dev, 0x78, &f_cnt);
1074 temp += f_cnt & 0x1ff;
1075 mdelay(1);
1076 }
1077 f_cnt = temp / 128;
1078 } else
1079 f_cnt = temp & 0x1ff;
1080
1081 dpll_clk = info->dpll_clk;
1082 pci_clk = (f_cnt * dpll_clk) / 192;
1083
1084 /* Clamp PCI clock to bands. */
1085 if (pci_clk < 40)
1086 pci_clk = 33;
1087 else if(pci_clk < 45)
1088 pci_clk = 40;
1089 else if(pci_clk < 55)
1090 pci_clk = 50;
1091 else
1092 pci_clk = 66;
1093
1094 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1095 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1096 } else {
1097 u32 itr1 = 0;
1098
1099 pci_read_config_dword(dev, 0x40, &itr1);
1100
1101 /* Detect PCI clock by looking at cmd_high_time. */
1102 switch((itr1 >> 8) & 0x07) {
1103 case 0x09:
1104 pci_clk = 40;
1105 break;
1106 case 0x05:
1107 pci_clk = 25;
1108 break;
1109 case 0x07:
1110 default:
1111 pci_clk = 33;
1112 break;
1113 }
1114 }
1115
1116 /* Let's assume we'll use PCI clock for the ATA clock... */
1117 switch (pci_clk) {
1118 case 25:
1119 clock = ATA_CLOCK_25MHZ;
1120 break;
1121 case 33:
1122 default:
1123 clock = ATA_CLOCK_33MHZ;
1124 break;
1125 case 40:
1126 clock = ATA_CLOCK_40MHZ;
1127 break;
1128 case 50:
1129 clock = ATA_CLOCK_50MHZ;
1130 break;
1131 case 66:
1132 clock = ATA_CLOCK_66MHZ;
1133 break;
1134 }
1135
1136 /*
1137 * Only try the DPLL if we don't have a table for the PCI clock that
1138 * we are running at for HPT370/A, always use it for anything newer...
1139 *
1140 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1141 * We also don't like using the DPLL because this causes glitches
1142 * on PRST-/SRST- when the state engine gets reset...
1143 */
1144 if (info->chip_type >= HPT374 || info->settings[clock] == NULL) {
1145 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1146 int adjust;
1147
1148 /*
1149 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1150 * supported/enabled, use 50 MHz DPLL clock otherwise...
1151 */
1152 if (info->max_mode == 0x04) {
1153 dpll_clk = 66;
1154 clock = ATA_CLOCK_66MHZ;
1155 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1156 dpll_clk = 50;
1157 clock = ATA_CLOCK_50MHZ;
1158 }
1159
1160 if (info->settings[clock] == NULL) {
1161 printk(KERN_ERR "%s: unknown bus timing!\n", name);
1162 kfree(info);
1163 return -EIO;
1164 }
1165
1166 /* Select the DPLL clock. */
1167 pci_write_config_byte(dev, 0x5b, 0x21);
1168
1169 /*
1170 * Adjust the DPLL based upon PCI clock, enable it,
1171 * and wait for stabilization...
1172 */
1173 f_low = (pci_clk * 48) / dpll_clk;
1174
1175 for (adjust = 0; adjust < 8; adjust++) {
1176 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1177 break;
1178
1179 /*
1180 * See if it'll settle at a fractionally different clock
1181 */
1182 if (adjust & 1)
1183 f_low -= adjust >> 1;
1184 else
1185 f_low += adjust >> 1;
1186 }
1187 if (adjust == 8) {
1188 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1189 kfree(info);
1190 return -EIO;
1191 }
1192
1193 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1194 } else {
1195 /* Mark the fact that we're not using the DPLL. */
1196 dpll_clk = 0;
1197
1198 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1199 }
1200
1201 /*
1202 * Advance the table pointer to a slot which points to the list
1203 * of the register values settings matching the clock being used.
1204 */
1205 info->settings += clock;
1206
1207 /* Store the clock frequencies. */
1208 info->dpll_clk = dpll_clk;
1209 info->pci_clk = pci_clk;
1210
1211 /* Point to this chip's own instance of the hpt_info structure. */
1212 pci_set_drvdata(dev, info);
1213
1214 if (info->chip_type >= HPT370) {
1215 u8 mcr1, mcr4;
1216
1217 /*
1218 * Reset the state engines.
1219 * NOTE: Avoid accidentally enabling the disabled channels.
1220 */
1221 pci_read_config_byte (dev, 0x50, &mcr1);
1222 pci_read_config_byte (dev, 0x54, &mcr4);
1223 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1224 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1225 udelay(100);
1226 }
1227
1228 /*
1229 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1230 * the MISC. register to stretch the UltraDMA Tss timing.
1231 * NOTE: This register is only writeable via I/O space.
1232 */
1233 if (info->chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1234
1235 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1236
1237 return dev->irq;
1238 }
1239
1240 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1241 {
1242 struct pci_dev *dev = hwif->pci_dev;
1243 struct hpt_info *info = pci_get_drvdata(dev);
1244 int serialize = HPT_SERIALIZE_IO;
1245 u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02;
1246 u8 chip_type = info->chip_type;
1247 u8 new_mcr, old_mcr = 0;
1248
1249 /* Cache the channel's MISC. control registers' offset */
1250 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1251
1252 hwif->tuneproc = &hpt3xx_tune_drive;
1253 hwif->speedproc = &hpt3xx_tune_chipset;
1254 hwif->quirkproc = &hpt3xx_quirkproc;
1255 hwif->intrproc = &hpt3xx_intrproc;
1256 hwif->maskproc = &hpt3xx_maskproc;
1257 hwif->busproc = &hpt3xx_busproc;
1258 hwif->udma_filter = &hpt3xx_udma_filter;
1259
1260 /*
1261 * HPT3xxN chips have some complications:
1262 *
1263 * - on 33 MHz PCI we must clock switch
1264 * - on 66 MHz PCI we must NOT use the PCI clock
1265 */
1266 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1267 /*
1268 * Clock is shared between the channels,
1269 * so we'll have to serialize them... :-(
1270 */
1271 serialize = 1;
1272 hwif->rw_disk = &hpt3xxn_rw_disk;
1273 }
1274
1275 /* Serialize access to this device if needed */
1276 if (serialize && hwif->mate)
1277 hwif->serialized = hwif->mate->serialized = 1;
1278
1279 /*
1280 * Disable the "fast interrupt" prediction. Don't hold off
1281 * on interrupts. (== 0x01 despite what the docs say)
1282 */
1283 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1284
1285 if (info->chip_type >= HPT374)
1286 new_mcr = old_mcr & ~0x07;
1287 else if (info->chip_type >= HPT370) {
1288 new_mcr = old_mcr;
1289 new_mcr &= ~0x02;
1290
1291 #ifdef HPT_DELAY_INTERRUPT
1292 new_mcr &= ~0x01;
1293 #else
1294 new_mcr |= 0x01;
1295 #endif
1296 } else /* HPT366 and HPT368 */
1297 new_mcr = old_mcr & ~0x80;
1298
1299 if (new_mcr != old_mcr)
1300 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1301
1302 if (!hwif->dma_base) {
1303 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1304 return;
1305 }
1306
1307 hwif->ultra_mask = 0x7f;
1308 hwif->mwdma_mask = 0x07;
1309
1310 /*
1311 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1312 * address lines to access an external EEPROM. To read valid
1313 * cable detect state the pins must be enabled as inputs.
1314 */
1315 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1316 /*
1317 * HPT374 PCI function 1
1318 * - set bit 15 of reg 0x52 to enable TCBLID as input
1319 * - set bit 15 of reg 0x56 to enable FCBLID as input
1320 */
1321 u8 mcr_addr = hwif->select_data + 2;
1322 u16 mcr;
1323
1324 pci_read_config_word (dev, mcr_addr, &mcr);
1325 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1326 /* now read cable id register */
1327 pci_read_config_byte (dev, 0x5a, &scr1);
1328 pci_write_config_word(dev, mcr_addr, mcr);
1329 } else if (chip_type >= HPT370) {
1330 /*
1331 * HPT370/372 and 374 pcifn 0
1332 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1333 */
1334 u8 scr2 = 0;
1335
1336 pci_read_config_byte (dev, 0x5b, &scr2);
1337 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1338 /* now read cable id register */
1339 pci_read_config_byte (dev, 0x5a, &scr1);
1340 pci_write_config_byte(dev, 0x5b, scr2);
1341 } else
1342 pci_read_config_byte (dev, 0x5a, &scr1);
1343
1344 if (!hwif->udma_four)
1345 hwif->udma_four = (scr1 & ata66) ? 0 : 1;
1346
1347 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1348
1349 if (chip_type >= HPT374) {
1350 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1351 hwif->ide_dma_end = &hpt374_ide_dma_end;
1352 } else if (chip_type >= HPT370) {
1353 hwif->dma_start = &hpt370_ide_dma_start;
1354 hwif->ide_dma_end = &hpt370_ide_dma_end;
1355 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1356 } else
1357 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1358
1359 if (!noautodma)
1360 hwif->autodma = 1;
1361 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1362 }
1363
1364 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1365 {
1366 struct pci_dev *dev = hwif->pci_dev;
1367 u8 masterdma = 0, slavedma = 0;
1368 u8 dma_new = 0, dma_old = 0;
1369 unsigned long flags;
1370
1371 dma_old = hwif->INB(dmabase + 2);
1372
1373 local_irq_save(flags);
1374
1375 dma_new = dma_old;
1376 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1377 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1378
1379 if (masterdma & 0x30) dma_new |= 0x20;
1380 if ( slavedma & 0x30) dma_new |= 0x40;
1381 if (dma_new != dma_old)
1382 hwif->OUTB(dma_new, dmabase + 2);
1383
1384 local_irq_restore(flags);
1385
1386 ide_setup_dma(hwif, dmabase, 8);
1387 }
1388
1389 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1390 {
1391 struct pci_dev *dev2;
1392
1393 if (PCI_FUNC(dev->devfn) & 1)
1394 return -ENODEV;
1395
1396 pci_set_drvdata(dev, &hpt374);
1397
1398 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1399 int ret;
1400
1401 pci_set_drvdata(dev2, &hpt374);
1402
1403 if (dev2->irq != dev->irq) {
1404 /* FIXME: we need a core pci_set_interrupt() */
1405 dev2->irq = dev->irq;
1406 printk(KERN_WARNING "%s: PCI config space interrupt "
1407 "fixed.\n", d->name);
1408 }
1409 ret = ide_setup_pci_devices(dev, dev2, d);
1410 if (ret < 0)
1411 pci_dev_put(dev2);
1412 return ret;
1413 }
1414 return ide_setup_pci_device(dev, d);
1415 }
1416
1417 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1418 {
1419 pci_set_drvdata(dev, &hpt372n);
1420
1421 return ide_setup_pci_device(dev, d);
1422 }
1423
1424 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1425 {
1426 struct hpt_info *info;
1427 u8 rev = 0, mcr1 = 0;
1428
1429 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1430
1431 if (rev > 1) {
1432 d->name = "HPT371N";
1433
1434 info = &hpt371n;
1435 } else
1436 info = &hpt371;
1437
1438 /*
1439 * HPT371 chips physically have only one channel, the secondary one,
1440 * but the primary channel registers do exist! Go figure...
1441 * So, we manually disable the non-existing channel here
1442 * (if the BIOS hasn't done this already).
1443 */
1444 pci_read_config_byte(dev, 0x50, &mcr1);
1445 if (mcr1 & 0x04)
1446 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1447
1448 pci_set_drvdata(dev, info);
1449
1450 return ide_setup_pci_device(dev, d);
1451 }
1452
1453 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1454 {
1455 struct hpt_info *info;
1456 u8 rev = 0;
1457
1458 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1459
1460 if (rev > 1) {
1461 d->name = "HPT372N";
1462
1463 info = &hpt372n;
1464 } else
1465 info = &hpt372a;
1466 pci_set_drvdata(dev, info);
1467
1468 return ide_setup_pci_device(dev, d);
1469 }
1470
1471 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1472 {
1473 struct hpt_info *info;
1474 u8 rev = 0;
1475
1476 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1477
1478 if (rev > 1) {
1479 d->name = "HPT302N";
1480
1481 info = &hpt302n;
1482 } else
1483 info = &hpt302;
1484 pci_set_drvdata(dev, info);
1485
1486 return ide_setup_pci_device(dev, d);
1487 }
1488
1489 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1490 {
1491 struct pci_dev *dev2;
1492 u8 rev = 0;
1493 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368",
1494 "HPT370", "HPT370A", "HPT372",
1495 "HPT372N" };
1496 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x,
1497 &hpt370, &hpt370a, &hpt372,
1498 &hpt372n };
1499
1500 if (PCI_FUNC(dev->devfn) & 1)
1501 return -ENODEV;
1502
1503 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1504
1505 if (rev > 6)
1506 rev = 6;
1507
1508 d->name = chipset_names[rev];
1509
1510 pci_set_drvdata(dev, info[rev]);
1511
1512 if (rev > 2)
1513 goto init_single;
1514
1515 /*
1516 * HPT36x chips are single channel and
1517 * do not seem to have the channel enable bit...
1518 */
1519 d->channels = 1;
1520 d->enablebits[0].reg = 0;
1521
1522 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1523 u8 pin1 = 0, pin2 = 0;
1524 int ret;
1525
1526 pci_set_drvdata(dev2, info[rev]);
1527
1528 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1529 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1530 if (pin1 != pin2 && dev->irq == dev2->irq) {
1531 d->bootable = ON_BOARD;
1532 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1533 d->name, pin1, pin2);
1534 }
1535 ret = ide_setup_pci_devices(dev, dev2, d);
1536 if (ret < 0)
1537 pci_dev_put(dev2);
1538 return ret;
1539 }
1540 init_single:
1541 return ide_setup_pci_device(dev, d);
1542 }
1543
1544 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1545 { /* 0 */
1546 .name = "HPT366",
1547 .init_setup = init_setup_hpt366,
1548 .init_chipset = init_chipset_hpt366,
1549 .init_hwif = init_hwif_hpt366,
1550 .init_dma = init_dma_hpt366,
1551 .channels = 2,
1552 .autodma = AUTODMA,
1553 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1554 .bootable = OFF_BOARD,
1555 .extra = 240
1556 },{ /* 1 */
1557 .name = "HPT372A",
1558 .init_setup = init_setup_hpt372a,
1559 .init_chipset = init_chipset_hpt366,
1560 .init_hwif = init_hwif_hpt366,
1561 .init_dma = init_dma_hpt366,
1562 .channels = 2,
1563 .autodma = AUTODMA,
1564 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1565 .bootable = OFF_BOARD,
1566 .extra = 240
1567 },{ /* 2 */
1568 .name = "HPT302",
1569 .init_setup = init_setup_hpt302,
1570 .init_chipset = init_chipset_hpt366,
1571 .init_hwif = init_hwif_hpt366,
1572 .init_dma = init_dma_hpt366,
1573 .channels = 2,
1574 .autodma = AUTODMA,
1575 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1576 .bootable = OFF_BOARD,
1577 .extra = 240
1578 },{ /* 3 */
1579 .name = "HPT371",
1580 .init_setup = init_setup_hpt371,
1581 .init_chipset = init_chipset_hpt366,
1582 .init_hwif = init_hwif_hpt366,
1583 .init_dma = init_dma_hpt366,
1584 .channels = 2,
1585 .autodma = AUTODMA,
1586 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1587 .bootable = OFF_BOARD,
1588 .extra = 240
1589 },{ /* 4 */
1590 .name = "HPT374",
1591 .init_setup = init_setup_hpt374,
1592 .init_chipset = init_chipset_hpt366,
1593 .init_hwif = init_hwif_hpt366,
1594 .init_dma = init_dma_hpt366,
1595 .channels = 2, /* 4 */
1596 .autodma = AUTODMA,
1597 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1598 .bootable = OFF_BOARD,
1599 .extra = 240
1600 },{ /* 5 */
1601 .name = "HPT372N",
1602 .init_setup = init_setup_hpt372n,
1603 .init_chipset = init_chipset_hpt366,
1604 .init_hwif = init_hwif_hpt366,
1605 .init_dma = init_dma_hpt366,
1606 .channels = 2, /* 4 */
1607 .autodma = AUTODMA,
1608 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1609 .bootable = OFF_BOARD,
1610 .extra = 240
1611 }
1612 };
1613
1614 /**
1615 * hpt366_init_one - called when an HPT366 is found
1616 * @dev: the hpt366 device
1617 * @id: the matching pci id
1618 *
1619 * Called when the PCI registration layer (or the IDE initialization)
1620 * finds a device matching our IDE device tables.
1621 *
1622 * NOTE: since we'll have to modify some fields of the ide_pci_device_t
1623 * structure depending on the chip's revision, we'd better pass a local
1624 * copy down the call chain...
1625 */
1626 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1627 {
1628 ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1629
1630 return d.init_setup(dev, &d);
1631 }
1632
1633 static struct pci_device_id hpt366_pci_tbl[] = {
1634 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1635 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1636 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1637 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1638 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1639 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1640 { 0, },
1641 };
1642 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1643
1644 static struct pci_driver driver = {
1645 .name = "HPT366_IDE",
1646 .id_table = hpt366_pci_tbl,
1647 .probe = hpt366_init_one,
1648 };
1649
1650 static int __init hpt366_ide_init(void)
1651 {
1652 return ide_pci_register_driver(&driver);
1653 }
1654
1655 module_init(hpt366_ide_init);
1656
1657 MODULE_AUTHOR("Andre Hedrick");
1658 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1659 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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