drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.51    Jul 27, 2007
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *  Copyright (C) 2006-2007             MontaVista Software, Inc.
   6  *  Copyright (C) 2007                  Bartlomiej Zolnierkiewicz
   7  *
   8  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   9  *  compiled into the kernel if you have more than one card installed.
  10  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
  11  *  safe chipset tuning, including this support is harmless
  12  *
  13  *  Promise Ultra66 cards with BIOS v1.11 this
  14  *  compiled into the kernel if you have more than one card installed.
  15  *
  16  *  Promise Ultra100 cards.
  17  *
  18  *  The latest chipset code will support the following ::
  19  *  Three Ultra33 controllers and 12 drives.
  20  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  21  *  The 8/4 ratio is a BIOS code limit by promise.
  22  *
  23  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  24  *
  25  */
  26
  27 /*
  28  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  29  *  Author: Frank Tiernan (frankt@promise.com)
  30  *  Released under terms of General Public License
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/delay.h>
  37 #include <linux/timer.h>
  38 #include <linux/mm.h>
  39 #include <linux/ioport.h>
  40 #include <linux/blkdev.h>
  41 #include <linux/hdreg.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/init.h>
  45 #include <linux/ide.h>
  46
  47 #include <asm/io.h>
  48 #include <asm/irq.h>
  49
  50 #define PDC202XX_DEBUG_DRIVE_INFO       0
  51
  52 static const char *pdc_quirk_drives[] = {
  53         "QUANTUM FIREBALLlct08 08",
  54         "QUANTUM FIREBALLP KA6.4",
  55         "QUANTUM FIREBALLP KA9.1",
  56         "QUANTUM FIREBALLP LM20.4",
  57         "QUANTUM FIREBALLP KX13.6",
  58         "QUANTUM FIREBALLP KX20.5",
  59         "QUANTUM FIREBALLP KX27.3",
  60         "QUANTUM FIREBALLP LM20.5",
  61         NULL
  62 };
  63
  64 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
  65
  66 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
  67 {
  68         ide_hwif_t *hwif        = HWIF(drive);
  69         struct pci_dev *dev     = hwif->pci_dev;
  70         u8 drive_pci            = 0x60 + (drive->dn << 2);
  71
  72         u8                      AP = 0, BP = 0, CP = 0;
  73         u8                      TA = 0, TB = 0, TC = 0;
  74
  75 #if PDC202XX_DEBUG_DRIVE_INFO
  76         u32                     drive_conf = 0;
  77         pci_read_config_dword(dev, drive_pci, &drive_conf);
  78 #endif
  79
  80         /*
  81          * TODO: do this once per channel
  82          */
  83         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
  84                 pdc_old_disable_66MHz_clock(hwif);
  85
  86         pci_read_config_byte(dev, drive_pci,     &AP);
  87         pci_read_config_byte(dev, drive_pci + 1, &BP);
  88         pci_read_config_byte(dev, drive_pci + 2, &CP);
  89
  90         switch(speed) {
  91                 case XFER_UDMA_5:
  92                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
  93                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
  94                 case XFER_UDMA_3:
  95                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
  96                 case XFER_UDMA_0:
  97                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
  98                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
  99                 case XFER_MW_DMA_0:     TB = 0xE0; TC = 0x0F; break;
 100                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 101                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 102                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 103                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 104                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 105                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 106                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 107                 case XFER_PIO_0:
 108                 default:                TA = 0x09; TB = 0x13; break;
 109         }
 110
 111         if (speed < XFER_SW_DMA_0) {
 112                 /*
 113                  * preserve SYNC_INT / ERDDY_EN bits while clearing
 114                  * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
 115                  */
 116                 AP &= ~0x3f;
 117                 if (drive->id->capability & 4)
 118                         AP |= 0x20;     /* set IORDY_EN bit */
 119                 if (drive->media == ide_disk)
 120                         AP |= 0x10;     /* set Prefetch_EN bit */
 121                 /* clear PB[4:0] bits of register B */
 122                 BP &= ~0x1f;
 123                 pci_write_config_byte(dev, drive_pci,     AP | TA);
 124                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 125         } else {
 126                 /* clear MB[2:0] bits of register B */
 127                 BP &= ~0xe0;
 128                 /* clear MC[3:0] bits of register C */
 129                 CP &= ~0x0f;
 130                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 131                 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
 132         }
 133
 134 #if PDC202XX_DEBUG_DRIVE_INFO
 135         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 136                 drive->name, ide_xfer_verbose(speed),
 137                 drive->dn, drive_conf);
 138         pci_read_config_dword(dev, drive_pci, &drive_conf);
 139         printk("0x%08x\n", drive_conf);
 140 #endif
 141 }
 142
 143 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
 144 {
 145         pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
 146 }
 147
 148 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 149 {
 150         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 151
 152         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 153
 154         return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 155 }
 156
 157 /*
 158  * Set the control register to use the 66MHz system
 159  * clock for UDMA 3/4/5 mode operation when necessary.
 160  *
 161  * FIXME: this register is shared by both channels, some locking is needed
 162  *
 163  * It may also be possible to leave the 66MHz clock on
 164  * and readjust the timing parameters.
 165  */
 166 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 167 {
 168         unsigned long clock_reg = hwif->dma_master + 0x11;
 169         u8 clock = inb(clock_reg);
 170
 171         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 172 }
 173
 174 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 175 {
 176         unsigned long clock_reg = hwif->dma_master + 0x11;
 177         u8 clock = inb(clock_reg);
 178
 179         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 180 }
 181
 182 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 183 {
 184         if (ide_tune_dma(drive))
 185                 return 0;
 186
 187         ide_set_max_pio(drive);
 188
 189         return -1;
 190 }
 191
 192 static int pdc202xx_quirkproc (ide_drive_t *drive)
 193 {
 194         const char **list, *model = drive->id->model;
 195
 196         for (list = pdc_quirk_drives; *list != NULL; list++)
 197                 if (strstr(model, *list) != NULL)
 198                         return 2;
 199         return 0;
 200 }
 201
 202 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 203 {
 204         if (drive->current_speed > XFER_UDMA_2)
 205                 pdc_old_enable_66MHz_clock(drive->hwif);
 206         if (drive->media != ide_disk || drive->addressing == 1) {
 207                 struct request *rq      = HWGROUP(drive)->rq;
 208                 ide_hwif_t *hwif        = HWIF(drive);
 209                 unsigned long high_16   = hwif->dma_master;
 210                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 211                 u32 word_count  = 0;
 212                 u8 clock = inb(high_16 + 0x11);
 213
 214                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 215                 word_count = (rq->nr_sectors << 8);
 216                 word_count = (rq_data_dir(rq) == READ) ?
 217                                         word_count | 0x05000000 :
 218                                         word_count | 0x06000000;
 219                 outl(word_count, atapi_reg);
 220         }
 221         ide_dma_start(drive);
 222 }
 223
 224 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 225 {
 226         if (drive->media != ide_disk || drive->addressing == 1) {
 227                 ide_hwif_t *hwif        = HWIF(drive);
 228                 unsigned long high_16   = hwif->dma_master;
 229                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 230                 u8 clock                = 0;
 231
 232                 outl(0, atapi_reg); /* zero out extra */
 233                 clock = inb(high_16 + 0x11);
 234                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 235         }
 236         if (drive->current_speed > XFER_UDMA_2)
 237                 pdc_old_disable_66MHz_clock(drive->hwif);
 238         return __ide_dma_end(drive);
 239 }
 240
 241 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 242 {
 243         ide_hwif_t *hwif        = HWIF(drive);
 244         unsigned long high_16   = hwif->dma_master;
 245         u8 dma_stat             = inb(hwif->dma_status);
 246         u8 sc1d                 = inb(high_16 + 0x001d);
 247
 248         if (hwif->channel) {
 249                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 250                 if ((sc1d & 0x50) == 0x50)
 251                         goto somebody_else;
 252                 else if ((sc1d & 0x40) == 0x40)
 253                         return (dma_stat & 4) == 4;
 254         } else {
 255                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 256                 if ((sc1d & 0x05) == 0x05)
 257                         goto somebody_else;
 258                 else if ((sc1d & 0x04) == 0x04)
 259                         return (dma_stat & 4) == 4;
 260         }
 261 somebody_else:
 262         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 263 }
 264
 265 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
 266 {
 267         ide_hwif_t *hwif = HWIF(drive);
 268
 269         if (hwif->resetproc != NULL)
 270                 hwif->resetproc(drive);
 271
 272         ide_dma_lost_irq(drive);
 273 }
 274
 275 static void pdc202xx_dma_timeout(ide_drive_t *drive)
 276 {
 277         ide_hwif_t *hwif = HWIF(drive);
 278
 279         if (hwif->resetproc != NULL)
 280                 hwif->resetproc(drive);
 281
 282         ide_dma_timeout(drive);
 283 }
 284
 285 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 286 {
 287         unsigned long high_16   = hwif->dma_master;
 288         u8 udma_speed_flag      = inb(high_16 | 0x001f);
 289
 290         outb(udma_speed_flag | 0x10, high_16 | 0x001f);
 291         mdelay(100);
 292         outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
 293         mdelay(2000);   /* 2 seconds ?! */
 294
 295         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 296                 hwif->channel ? "Secondary" : "Primary");
 297 }
 298
 299 static void pdc202xx_reset (ide_drive_t *drive)
 300 {
 301         ide_hwif_t *hwif        = HWIF(drive);
 302         ide_hwif_t *mate        = hwif->mate;
 303
 304         pdc202xx_reset_host(hwif);
 305         pdc202xx_reset_host(mate);
 306
 307         ide_set_max_pio(drive);
 308 }
 309
 310 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 311                                                         const char *name)
 312 {
 313         return dev->irq;
 314 }
 315
 316 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 317 {
 318         struct pci_dev *dev = hwif->pci_dev;
 319
 320         /* PDC20265 has problems with large LBA48 requests */
 321         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 322             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 323                 hwif->rqsize = 256;
 324
 325         hwif->autodma = 0;
 326
 327         hwif->set_pio_mode = &pdc202xx_set_pio_mode;
 328         hwif->set_dma_mode = &pdc202xx_set_mode;
 329
 330         hwif->quirkproc = &pdc202xx_quirkproc;
 331
 332         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
 333                 hwif->resetproc = &pdc202xx_reset;
 334
 335         hwif->err_stops_fifo = 1;
 336
 337         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 338
 339         if (hwif->dma_base == 0)
 340                 return;
 341
 342         hwif->ultra_mask = hwif->cds->udma_mask;
 343         hwif->mwdma_mask = 0x07;
 344         hwif->swdma_mask = 0x07;
 345         hwif->atapi_dma = 1;
 346
 347         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 348         hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
 349         hwif->dma_timeout = &pdc202xx_dma_timeout;
 350
 351         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 352                 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 353                         hwif->cbl = pdc202xx_old_cable_detect(hwif);
 354
 355                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 356                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 357         }
 358         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 359
 360         if (!noautodma)
 361                 hwif->autodma = 1;
 362         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 363 }
 364
 365 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 366 {
 367         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 368
 369         if (hwif->channel) {
 370                 ide_setup_dma(hwif, dmabase, 8);
 371                 return;
 372         }
 373
 374         udma_speed_flag = inb(dmabase | 0x1f);
 375         primary_mode    = inb(dmabase | 0x1a);
 376         secondary_mode  = inb(dmabase | 0x1b);
 377         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 378                 "Primary %s Mode " \
 379                 "Secondary %s Mode.\n", hwif->cds->name,
 380                 (udma_speed_flag & 1) ? "EN" : "DIS",
 381                 (primary_mode & 1) ? "MASTER" : "PCI",
 382                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 383
 384 #ifdef CONFIG_PDC202XX_BURST
 385         if (!(udma_speed_flag & 1)) {
 386                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 387                         hwif->cds->name, udma_speed_flag,
 388                         (udma_speed_flag|1));
 389                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 390                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 391         }
 392 #endif /* CONFIG_PDC202XX_BURST */
 393
 394         ide_setup_dma(hwif, dmabase, 8);
 395 }
 396
 397 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
 398                                            ide_pci_device_t *d)
 399 {
 400         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 401                 u8 irq = 0, irq2 = 0;
 402                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 403                 /* 0xbc */
 404                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 405                 if (irq != irq2) {
 406                         pci_write_config_byte(dev,
 407                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 408                         printk(KERN_INFO "%s: pci-config space interrupt "
 409                                 "mirror fixed.\n", d->name);
 410                 }
 411         }
 412         return ide_setup_pci_device(dev, d);
 413 }
 414
 415 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
 416                                          ide_pci_device_t *d)
 417 {
 418         if ((dev->bus->self) &&
 419             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 420             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 421              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 422                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 423                         "attached to I2O RAID controller.\n");
 424                 return -ENODEV;
 425         }
 426         return ide_setup_pci_device(dev, d);
 427 }
 428
 429 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
 430                                          ide_pci_device_t *d)
 431 {
 432         return ide_setup_pci_device(dev, d);
 433 }
 434
 435 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 436         {       /* 0 */
 437                 .name           = "PDC20246",
 438                 .init_setup     = init_setup_pdc202ata4,
 439                 .init_chipset   = init_chipset_pdc202xx,
 440                 .init_hwif      = init_hwif_pdc202xx,
 441                 .init_dma       = init_dma_pdc202xx,
 442                 .autodma        = AUTODMA,
 443                 .bootable       = OFF_BOARD,
 444                 .extra          = 16,
 445                 .pio_mask       = ATA_PIO4,
 446                 .udma_mask      = 0x07, /* udma0-2 */
 447         },{     /* 1 */
 448                 .name           = "PDC20262",
 449                 .init_setup     = init_setup_pdc202ata4,
 450                 .init_chipset   = init_chipset_pdc202xx,
 451                 .init_hwif      = init_hwif_pdc202xx,
 452                 .init_dma       = init_dma_pdc202xx,
 453                 .autodma        = AUTODMA,
 454                 .bootable       = OFF_BOARD,
 455                 .extra          = 48,
 456                 .pio_mask       = ATA_PIO4,
 457                 .udma_mask      = 0x1f, /* udma0-4 */
 458         },{     /* 2 */
 459                 .name           = "PDC20263",
 460                 .init_setup     = init_setup_pdc202ata4,
 461                 .init_chipset   = init_chipset_pdc202xx,
 462                 .init_hwif      = init_hwif_pdc202xx,
 463                 .init_dma       = init_dma_pdc202xx,
 464                 .autodma        = AUTODMA,
 465                 .bootable       = OFF_BOARD,
 466                 .extra          = 48,
 467                 .pio_mask       = ATA_PIO4,
 468                 .udma_mask      = 0x1f, /* udma0-4 */
 469         },{     /* 3 */
 470                 .name           = "PDC20265",
 471                 .init_setup     = init_setup_pdc20265,
 472                 .init_chipset   = init_chipset_pdc202xx,
 473                 .init_hwif      = init_hwif_pdc202xx,
 474                 .init_dma       = init_dma_pdc202xx,
 475                 .autodma        = AUTODMA,
 476                 .bootable       = OFF_BOARD,
 477                 .extra          = 48,
 478                 .pio_mask       = ATA_PIO4,
 479                 .udma_mask      = 0x3f, /* udma0-5 */
 480         },{     /* 4 */
 481                 .name           = "PDC20267",
 482                 .init_setup     = init_setup_pdc202xx,
 483                 .init_chipset   = init_chipset_pdc202xx,
 484                 .init_hwif      = init_hwif_pdc202xx,
 485                 .init_dma       = init_dma_pdc202xx,
 486                 .autodma        = AUTODMA,
 487                 .bootable       = OFF_BOARD,
 488                 .extra          = 48,
 489                 .pio_mask       = ATA_PIO4,
 490                 .udma_mask      = 0x3f, /* udma0-5 */
 491         }
 492 };
 493
 494 /**
 495  *      pdc202xx_init_one       -       called when a PDC202xx is found
 496  *      @dev: the pdc202xx device
 497  *      @id: the matching pci id
 498  *
 499  *      Called when the PCI registration layer (or the IDE initialization)
 500  *      finds a device matching our IDE device tables.
 501  */
 502
 503 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 504 {
 505         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 506
 507         return d->init_setup(dev, d);
 508 }
 509
 510 static struct pci_device_id pdc202xx_pci_tbl[] = {
 511         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 512         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 513         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 514         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 515         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 516         { 0, },
 517 };
 518 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 519
 520 static struct pci_driver driver = {
 521         .name           = "Promise_Old_IDE",
 522         .id_table       = pdc202xx_pci_tbl,
 523         .probe          = pdc202xx_init_one,
 524 };
 525
 526 static int __init pdc202xx_ide_init(void)
 527 {
 528         return ide_pci_register_driver(&driver);
 529 }
 530
 531 module_init(pdc202xx_ide_init);
 532
 533 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 534 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 535 MODULE_LICENSE("GPL");