drivers/ide/pci/piix.c

   1 /*
   2  *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
   3  *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   4  *  Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
   5  *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  *  May be copied or modified under the terms of the GNU General Public License
   8  *
   9  * Documentation:
  10  *
  11  *      Publically available from Intel web site. Errata documentation
  12  * is also publically available. As an aide to anyone hacking on this
  13  * driver the list of errata that are relevant is below.going back to
  14  * PIIX4. Older device documentation is now a bit tricky to find.
  15  *
  16  * Errata of note:
  17  *
  18  * Unfixable
  19  *      PIIX4    errata #9      - Only on ultra obscure hw
  20  *      ICH3     errata #13     - Not observed to affect real hw
  21  *                                by Intel
  22  *
  23  * Things we must deal with
  24  *      PIIX4   errata #10      - BM IDE hang with non UDMA
  25  *                                (must stop/start dma to recover)
  26  *      440MX   errata #15      - As PIIX4 errata #10
  27  *      PIIX4   errata #15      - Must not read control registers
  28  *                                during a PIO transfer
  29  *      440MX   errata #13      - As PIIX4 errata #15
  30  *      ICH2    errata #21      - DMA mode 0 doesn't work right
  31  *      ICH0/1  errata #55      - As ICH2 errata #21
  32  *      ICH2    spec c #9       - Extra operations needed to handle
  33  *                                drive hotswap [NOT YET SUPPORTED]
  34  *      ICH2    spec c #20      - IDE PRD must not cross a 64K boundary
  35  *                                and must be dword aligned
  36  *      ICH2    spec c #24      - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  37  *
  38  * Should have been BIOS fixed:
  39  *      450NX:  errata #19      - DMA hangs on old 450NX
  40  *      450NX:  errata #20      - DMA hangs on old 450NX
  41  *      450NX:  errata #25      - Corruption with DMA on old 450NX
  42  *      ICH3    errata #15      - IDE deadlock under high load
  43  *                                (BIOS must set dev 31 fn 0 bit 23)
  44  *      ICH3    errata #18      - Don't use native mode
  45  */
  46
  47 #include <linux/types.h>
  48 #include <linux/module.h>
  49 #include <linux/kernel.h>
  50 #include <linux/pci.h>
  51 #include <linux/hdreg.h>
  52 #include <linux/ide.h>
  53 #include <linux/init.h>
  54
  55 #include <asm/io.h>
  56
  57 static int no_piix_dma;
  58
  59 /**
  60  *      piix_set_pio_mode       -       set host controller for PIO mode
  61  *      @drive: drive
  62  *      @pio: PIO mode number
  63  *
  64  *      Set the interface PIO mode based upon the settings done by AMI BIOS.
  65  */
  66
  67 static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
  68 {
  69         ide_hwif_t *hwif        = HWIF(drive);
  70         struct pci_dev *dev     = to_pci_dev(hwif->dev);
  71         int is_slave            = drive->dn & 1;
  72         int master_port         = hwif->channel ? 0x42 : 0x40;
  73         int slave_port          = 0x44;
  74         unsigned long flags;
  75         u16 master_data;
  76         u8 slave_data;
  77         static DEFINE_SPINLOCK(tune_lock);
  78         int control = 0;
  79
  80                                      /* ISP  RTC */
  81         static const u8 timings[][2]= {
  82                                         { 0, 0 },
  83                                         { 0, 0 },
  84                                         { 1, 0 },
  85                                         { 2, 1 },
  86                                         { 2, 3 }, };
  87
  88         /*
  89          * Master vs slave is synchronized above us but the slave register is
  90          * shared by the two hwifs so the corner case of two slave timeouts in
  91          * parallel must be locked.
  92          */
  93         spin_lock_irqsave(&tune_lock, flags);
  94         pci_read_config_word(dev, master_port, &master_data);
  95
  96         if (pio > 1)
  97                 control |= 1;   /* Programmable timing on */
  98         if (drive->media == ide_disk)
  99                 control |= 4;   /* Prefetch, post write */
 100         if (pio > 2)
 101                 control |= 2;   /* IORDY */
 102         if (is_slave) {
 103                 master_data |=  0x4000;
 104                 master_data &= ~0x0070;
 105                 if (pio > 1) {
 106                         /* Set PPE, IE and TIME */
 107                         master_data |= control << 4;
 108                 }
 109                 pci_read_config_byte(dev, slave_port, &slave_data);
 110                 slave_data &= hwif->channel ? 0x0f : 0xf0;
 111                 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
 112                                (hwif->channel ? 4 : 0);
 113         } else {
 114                 master_data &= ~0x3307;
 115                 if (pio > 1) {
 116                         /* enable PPE, IE and TIME */
 117                         master_data |= control;
 118                 }
 119                 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
 120         }
 121         pci_write_config_word(dev, master_port, master_data);
 122         if (is_slave)
 123                 pci_write_config_byte(dev, slave_port, slave_data);
 124         spin_unlock_irqrestore(&tune_lock, flags);
 125 }
 126
 127 /**
 128  *      piix_set_dma_mode       -       set host controller for DMA mode
 129  *      @drive: drive
 130  *      @speed: DMA mode
 131  *
 132  *      Set a PIIX host controller to the desired DMA mode.  This involves
 133  *      programming the right timing data into the PCI configuration space.
 134  */
 135
 136 static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
 137 {
 138         ide_hwif_t *hwif        = HWIF(drive);
 139         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 140         u8 maslave              = hwif->channel ? 0x42 : 0x40;
 141         int a_speed             = 3 << (drive->dn * 4);
 142         int u_flag              = 1 << drive->dn;
 143         int v_flag              = 0x01 << drive->dn;
 144         int w_flag              = 0x10 << drive->dn;
 145         int u_speed             = 0;
 146         int                     sitre;
 147         u16                     reg4042, reg4a;
 148         u8                      reg48, reg54, reg55;
 149
 150         pci_read_config_word(dev, maslave, &reg4042);
 151         sitre = (reg4042 & 0x4000) ? 1 : 0;
 152         pci_read_config_byte(dev, 0x48, &reg48);
 153         pci_read_config_word(dev, 0x4a, &reg4a);
 154         pci_read_config_byte(dev, 0x54, &reg54);
 155         pci_read_config_byte(dev, 0x55, &reg55);
 156
 157         if (speed >= XFER_UDMA_0) {
 158                 u8 udma = speed - XFER_UDMA_0;
 159
 160                 u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
 161
 162                 if (!(reg48 & u_flag))
 163                         pci_write_config_byte(dev, 0x48, reg48 | u_flag);
 164                 if (speed == XFER_UDMA_5) {
 165                         pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
 166                 } else {
 167                         pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 168                 }
 169                 if ((reg4a & a_speed) != u_speed)
 170                         pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
 171                 if (speed > XFER_UDMA_2) {
 172                         if (!(reg54 & v_flag))
 173                                 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
 174                 } else
 175                         pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 176         } else {
 177                 const u8 mwdma_to_pio[] = { 0, 3, 4 };
 178                 u8 pio;
 179
 180                 if (reg48 & u_flag)
 181                         pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
 182                 if (reg4a & a_speed)
 183                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 184                 if (reg54 & v_flag)
 185                         pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 186                 if (reg55 & w_flag)
 187                         pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 188
 189                 if (speed >= XFER_MW_DMA_0)
 190                         pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
 191                 else
 192                         pio = 2; /* only SWDMA2 is allowed */
 193
 194                 piix_set_pio_mode(drive, pio);
 195         }
 196 }
 197
 198 /**
 199  *      init_chipset_ich        -       set up the ICH chipset
 200  *      @dev: PCI device to set up
 201  *      @name: Name of the device
 202  *
 203  *      Initialize the PCI device as required.  For the ICH this turns
 204  *      out to be nice and simple.
 205  */
 206
 207 static unsigned int __devinit init_chipset_ich(struct pci_dev *dev, const char *name)
 208 {
 209         u32 extra = 0;
 210
 211         pci_read_config_dword(dev, 0x54, &extra);
 212         pci_write_config_dword(dev, 0x54, extra | 0x400);
 213
 214         return 0;
 215 }
 216
 217 /**
 218  *      piix_dma_clear_irq      -       clear BMDMA status
 219  *      @drive: IDE drive to clear
 220  *
 221  *      Called from ide_intr() for PIO interrupts
 222  *      to clear BMDMA status as needed by ICHx
 223  */
 224 static void piix_dma_clear_irq(ide_drive_t *drive)
 225 {
 226         ide_hwif_t *hwif = HWIF(drive);
 227         u8 dma_stat;
 228
 229         /* clear the INTR & ERROR bits */
 230         dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
 231         /* Should we force the bit as well ? */
 232         outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
 233 }
 234
 235 struct ich_laptop {
 236         u16 device;
 237         u16 subvendor;
 238         u16 subdevice;
 239 };
 240
 241 /*
 242  *      List of laptops that use short cables rather than 80 wire
 243  */
 244
 245 static const struct ich_laptop ich_laptop[] = {
 246         /* devid, subvendor, subdev */
 247         { 0x27DF, 0x1025, 0x0102 },     /* ICH7 on Acer 5602aWLMi */
 248         { 0x27DF, 0x0005, 0x0280 },     /* ICH7 on Acer 5602WLMi */
 249         { 0x27DF, 0x1025, 0x0110 },     /* ICH7 on Acer 3682WLMi */
 250         { 0x27DF, 0x1043, 0x1267 },     /* ICH7 on Asus W5F */
 251         { 0x27DF, 0x103C, 0x30A1 },     /* ICH7 on HP Compaq nc2400 */
 252         { 0x24CA, 0x1025, 0x0061 },     /* ICH4 on Acer Aspire 2023WLMi */
 253         { 0x2653, 0x1043, 0x82D8 },     /* ICH6M on Asus Eee 701 */
 254         /* end marker */
 255         { 0, }
 256 };
 257
 258 static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
 259 {
 260         struct pci_dev *pdev = to_pci_dev(hwif->dev);
 261         const struct ich_laptop *lap = &ich_laptop[0];
 262         u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
 263
 264         /* check for specials */
 265         while (lap->device) {
 266                 if (lap->device == pdev->device &&
 267                     lap->subvendor == pdev->subsystem_vendor &&
 268                     lap->subdevice == pdev->subsystem_device) {
 269                         return ATA_CBL_PATA40_SHORT;
 270                 }
 271                 lap++;
 272         }
 273
 274         pci_read_config_byte(pdev, 0x54, &reg54h);
 275
 276         return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 277 }
 278
 279 /**
 280  *      init_hwif_piix          -       fill in the hwif for the PIIX
 281  *      @hwif: IDE interface
 282  *
 283  *      Set up the ide_hwif_t for the PIIX interface according to the
 284  *      capabilities of the hardware.
 285  */
 286
 287 static void __devinit init_hwif_piix(ide_hwif_t *hwif)
 288 {
 289         if (!hwif->dma_base)
 290                 return;
 291
 292         if (no_piix_dma)
 293                 hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
 294 }
 295
 296 static void __devinit init_hwif_ich(ide_hwif_t *hwif)
 297 {
 298         init_hwif_piix(hwif);
 299
 300         /* ICHx need to clear the BMDMA status for all interrupts */
 301         if (hwif->dma_base)
 302                 hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
 303 }
 304
 305 static const struct ide_port_ops piix_port_ops = {
 306         .set_pio_mode           = piix_set_pio_mode,
 307         .set_dma_mode           = piix_set_dma_mode,
 308         .cable_detect           = piix_cable_detect,
 309 };
 310
 311 #ifndef CONFIG_IA64
 312  #define IDE_HFLAGS_PIIX IDE_HFLAG_LEGACY_IRQS
 313 #else
 314  #define IDE_HFLAGS_PIIX 0
 315 #endif
 316
 317 #define DECLARE_PIIX_DEV(name_str, udma) \
 318         {                                               \
 319                 .name           = name_str,             \
 320                 .init_hwif      = init_hwif_piix,       \
 321                 .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
 322                 .port_ops       = &piix_port_ops,       \
 323                 .host_flags     = IDE_HFLAGS_PIIX,      \
 324                 .pio_mask       = ATA_PIO4,             \
 325                 .swdma_mask     = ATA_SWDMA2_ONLY,      \
 326                 .mwdma_mask     = ATA_MWDMA12_ONLY,     \
 327                 .udma_mask      = udma,                 \
 328         }
 329
 330 #define DECLARE_ICH_DEV(name_str, udma) \
 331         { \
 332                 .name           = name_str, \
 333                 .init_chipset   = init_chipset_ich, \
 334                 .init_hwif      = init_hwif_ich, \
 335                 .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
 336                 .port_ops       = &piix_port_ops, \
 337                 .host_flags     = IDE_HFLAGS_PIIX, \
 338                 .pio_mask       = ATA_PIO4, \
 339                 .swdma_mask     = ATA_SWDMA2_ONLY, \
 340                 .mwdma_mask     = ATA_MWDMA12_ONLY, \
 341                 .udma_mask      = udma, \
 342         }
 343
 344 static const struct ide_port_info piix_pci_info[] __devinitdata = {
 345         /*  0 */ DECLARE_PIIX_DEV("PIIXa",      0x00),  /* no udma */
 346         /*  1 */ DECLARE_PIIX_DEV("PIIXb",      0x00),  /* no udma */
 347
 348         /*  2 */
 349         {       /*
 350                  * MPIIX actually has only a single IDE channel mapped to
 351                  * the primary or secondary ports depending on the value
 352                  * of the bit 14 of the IDETIM register at offset 0x6c
 353                  */
 354                 .name           = "MPIIX",
 355                 .enablebits     = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
 356                 .host_flags     = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA |
 357                                   IDE_HFLAGS_PIIX,
 358                 .pio_mask       = ATA_PIO4,
 359                 /* This is a painful system best to let it self tune for now */
 360         },
 361
 362         /*  3 */ DECLARE_PIIX_DEV("PIIX3",      0x00),  /* no udma */
 363         /*  4 */ DECLARE_PIIX_DEV("PIIX4",      ATA_UDMA2),
 364         /*  5 */ DECLARE_ICH_DEV("ICH0",        ATA_UDMA2),
 365         /*  6 */ DECLARE_PIIX_DEV("PIIX4",      ATA_UDMA2),
 366         /*  7 */ DECLARE_ICH_DEV("ICH",         ATA_UDMA4),
 367         /*  8 */ DECLARE_PIIX_DEV("PIIX4",      ATA_UDMA4),
 368         /*  9 */ DECLARE_PIIX_DEV("PIIX4",      ATA_UDMA2),
 369         /* 10 */ DECLARE_ICH_DEV("ICH2",        ATA_UDMA5),
 370         /* 11 */ DECLARE_ICH_DEV("ICH2M",       ATA_UDMA5),
 371         /* 12 */ DECLARE_ICH_DEV("ICH3M",       ATA_UDMA5),
 372         /* 13 */ DECLARE_ICH_DEV("ICH3",        ATA_UDMA5),
 373         /* 14 */ DECLARE_ICH_DEV("ICH4",        ATA_UDMA5),
 374         /* 15 */ DECLARE_ICH_DEV("ICH5",        ATA_UDMA5),
 375         /* 16 */ DECLARE_ICH_DEV("C-ICH",       ATA_UDMA5),
 376         /* 17 */ DECLARE_ICH_DEV("ICH4",        ATA_UDMA5),
 377         /* 18 */ DECLARE_ICH_DEV("ICH5-SATA",   ATA_UDMA5),
 378         /* 19 */ DECLARE_ICH_DEV("ICH5",        ATA_UDMA5),
 379         /* 20 */ DECLARE_ICH_DEV("ICH6",        ATA_UDMA5),
 380         /* 21 */ DECLARE_ICH_DEV("ICH7",        ATA_UDMA5),
 381         /* 22 */ DECLARE_ICH_DEV("ICH4",        ATA_UDMA5),
 382         /* 23 */ DECLARE_ICH_DEV("ESB2",        ATA_UDMA5),
 383         /* 24 */ DECLARE_ICH_DEV("ICH8M",       ATA_UDMA5),
 384 };
 385
 386 /**
 387  *      piix_init_one   -       called when a PIIX is found
 388  *      @dev: the piix device
 389  *      @id: the matching pci id
 390  *
 391  *      Called when the PCI registration layer (or the IDE initialization)
 392  *      finds a device matching our IDE device tables.
 393  */
 394
 395 static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 396 {
 397         return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL);
 398 }
 399
 400 /**
 401  *      piix_check_450nx        -       Check for problem 450NX setup
 402  *
 403  *      Check for the present of 450NX errata #19 and errata #25. If
 404  *      they are found, disable use of DMA IDE
 405  */
 406
 407 static void __devinit piix_check_450nx(void)
 408 {
 409         struct pci_dev *pdev = NULL;
 410         u16 cfg;
 411         while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
 412         {
 413                 /* Look for 450NX PXB. Check for problem configurations
 414                    A PCI quirk checks bit 6 already */
 415                 pci_read_config_word(pdev, 0x41, &cfg);
 416                 /* Only on the original revision: IDE DMA can hang */
 417                 if (pdev->revision == 0x00)
 418                         no_piix_dma = 1;
 419                 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
 420                 else if (cfg & (1<<14) && pdev->revision < 5)
 421                         no_piix_dma = 2;
 422         }
 423         if(no_piix_dma)
 424                 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
 425         if(no_piix_dma == 2)
 426                 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
 427 }
 428
 429 static const struct pci_device_id piix_pci_tbl[] = {
 430         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0),   0 },
 431         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1),   1 },
 432         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX),     2 },
 433         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1),   3 },
 434         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB),     4 },
 435         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1),   5 },
 436         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1),   6 },
 437         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1),   7 },
 438         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1),   8 },
 439         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX),     9 },
 440         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9),  10 },
 441         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8),  11 },
 442         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 12 },
 443         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 13 },
 444         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 14 },
 445         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 15 },
 446         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11),  16 },
 447         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 17 },
 448 #ifdef CONFIG_BLK_DEV_IDE_SATA
 449         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1),  18 },
 450 #endif
 451         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2),      19 },
 452         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19),    20 },
 453         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21),    21 },
 454         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1),  22 },
 455         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18),    23 },
 456         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6),     24 },
 457         { 0, },
 458 };
 459 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
 460
 461 static struct pci_driver driver = {
 462         .name           = "PIIX_IDE",
 463         .id_table       = piix_pci_tbl,
 464         .probe          = piix_init_one,
 465 };
 466
 467 static int __init piix_ide_init(void)
 468 {
 469         piix_check_450nx();
 470         return ide_pci_register_driver(&driver);
 471 }
 472
 473 module_init(piix_ide_init);
 474
 475 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
 476 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
 477 MODULE_LICENSE("GPL");