drivers/ide/pci/piix.c

   1 /*
   2  *  linux/drivers/ide/pci/piix.c        Version 0.52    Jul 14, 2007
   3  *
   4  *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
   5  *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   6  *  Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
   7  *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
   8  *
   9  *  May be copied or modified under the terms of the GNU General Public License
  10  *
  11  *  PIO mode setting function for Intel chipsets.
  12  *  For use instead of BIOS settings.
  13  *
  14  * 40-41
  15  * 42-43
  16  *
  17  *                 41
  18  *                 43
  19  *
  20  * | PIO 0       | c0 | 80 | 0 |
  21  * | PIO 2 | SW2 | d0 | 90 | 4 |
  22  * | PIO 3 | MW1 | e1 | a1 | 9 |
  23  * | PIO 4 | MW2 | e3 | a3 | b |
  24  *
  25  * sitre = word40 & 0x4000; primary
  26  * sitre = word42 & 0x4000; secondary
  27  *
  28  * 44 8421|8421    hdd|hdb
  29  *
  30  * 48 8421         hdd|hdc|hdb|hda udma enabled
  31  *
  32  *    0001         hda
  33  *    0010         hdb
  34  *    0100         hdc
  35  *    1000         hdd
  36  *
  37  * 4a 84|21        hdb|hda
  38  * 4b 84|21        hdd|hdc
  39  *
  40  *    ata-33/82371AB
  41  *    ata-33/82371EB
  42  *    ata-33/82801AB            ata-66/82801AA
  43  *    00|00 udma 0              00|00 reserved
  44  *    01|01 udma 1              01|01 udma 3
  45  *    10|10 udma 2              10|10 udma 4
  46  *    11|11 reserved            11|11 reserved
  47  *
  48  * 54 8421|8421    ata66 drive|ata66 enable
  49  *
  50  * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
  51  * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
  52  * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
  53  * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, &reg48);
  54  * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
  55  * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, &reg54);
  56  *
  57  * Documentation
  58  *      Publically available from Intel web site. Errata documentation
  59  * is also publically available. As an aide to anyone hacking on this
  60  * driver the list of errata that are relevant is below.going back to
  61  * PIIX4. Older device documentation is now a bit tricky to find.
  62  *
  63  * Errata of note:
  64  *
  65  * Unfixable
  66  *      PIIX4    errata #9      - Only on ultra obscure hw
  67  *      ICH3     errata #13     - Not observed to affect real hw
  68  *                                by Intel
  69  *
  70  * Things we must deal with
  71  *      PIIX4   errata #10      - BM IDE hang with non UDMA
  72  *                                (must stop/start dma to recover)
  73  *      440MX   errata #15      - As PIIX4 errata #10
  74  *      PIIX4   errata #15      - Must not read control registers
  75  *                                during a PIO transfer
  76  *      440MX   errata #13      - As PIIX4 errata #15
  77  *      ICH2    errata #21      - DMA mode 0 doesn't work right
  78  *      ICH0/1  errata #55      - As ICH2 errata #21
  79  *      ICH2    spec c #9       - Extra operations needed to handle
  80  *                                drive hotswap [NOT YET SUPPORTED]
  81  *      ICH2    spec c #20      - IDE PRD must not cross a 64K boundary
  82  *                                and must be dword aligned
  83  *      ICH2    spec c #24      - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  84  *
  85  * Should have been BIOS fixed:
  86  *      450NX:  errata #19      - DMA hangs on old 450NX
  87  *      450NX:  errata #20      - DMA hangs on old 450NX
  88  *      450NX:  errata #25      - Corruption with DMA on old 450NX
  89  *      ICH3    errata #15      - IDE deadlock under high load
  90  *                                (BIOS must set dev 31 fn 0 bit 23)
  91  *      ICH3    errata #18      - Don't use native mode
  92  */
  93
  94 #include <linux/types.h>
  95 #include <linux/module.h>
  96 #include <linux/kernel.h>
  97 #include <linux/ioport.h>
  98 #include <linux/pci.h>
  99 #include <linux/hdreg.h>
 100 #include <linux/ide.h>
 101 #include <linux/delay.h>
 102 #include <linux/init.h>
 103
 104 #include <asm/io.h>
 105
 106 static int no_piix_dma;
 107
 108 /**
 109  *      piix_dma_2_pio          -       return the PIO mode matching DMA
 110  *      @xfer_rate: transfer speed
 111  *
 112  *      Returns the nearest equivalent PIO timing for the DMA
 113  *      mode requested by the controller.
 114  */
 115
 116 static u8 piix_dma_2_pio (u8 xfer_rate) {
 117         switch(xfer_rate) {
 118                 case XFER_UDMA_6:
 119                 case XFER_UDMA_5:
 120                 case XFER_UDMA_4:
 121                 case XFER_UDMA_3:
 122                 case XFER_UDMA_2:
 123                 case XFER_UDMA_1:
 124                 case XFER_UDMA_0:
 125                 case XFER_MW_DMA_2:
 126                         return 4;
 127                 case XFER_MW_DMA_1:
 128                         return 3;
 129                 case XFER_SW_DMA_2:
 130                         return 2;
 131                 case XFER_MW_DMA_0:
 132                 case XFER_SW_DMA_1:
 133                 case XFER_SW_DMA_0:
 134                 default:
 135                         return 0;
 136         }
 137 }
 138
 139 /**
 140  *      piix_set_pio_mode       -       set host controller for PIO mode
 141  *      @drive: drive
 142  *      @pio: PIO mode number
 143  *
 144  *      Set the interface PIO mode based upon the settings done by AMI BIOS.
 145  */
 146
 147 static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
 148 {
 149         ide_hwif_t *hwif        = HWIF(drive);
 150         struct pci_dev *dev     = hwif->pci_dev;
 151         int is_slave            = drive->dn & 1;
 152         int master_port         = hwif->channel ? 0x42 : 0x40;
 153         int slave_port          = 0x44;
 154         unsigned long flags;
 155         u16 master_data;
 156         u8 slave_data;
 157         static DEFINE_SPINLOCK(tune_lock);
 158         int control = 0;
 159
 160                                      /* ISP  RTC */
 161         static const u8 timings[][2]= {
 162                                         { 0, 0 },
 163                                         { 0, 0 },
 164                                         { 1, 0 },
 165                                         { 2, 1 },
 166                                         { 2, 3 }, };
 167
 168         /*
 169          * Master vs slave is synchronized above us but the slave register is
 170          * shared by the two hwifs so the corner case of two slave timeouts in
 171          * parallel must be locked.
 172          */
 173         spin_lock_irqsave(&tune_lock, flags);
 174         pci_read_config_word(dev, master_port, &master_data);
 175
 176         if (pio > 1)
 177                 control |= 1;   /* Programmable timing on */
 178         if (drive->media == ide_disk)
 179                 control |= 4;   /* Prefetch, post write */
 180         if (pio > 2)
 181                 control |= 2;   /* IORDY */
 182         if (is_slave) {
 183                 master_data |=  0x4000;
 184                 master_data &= ~0x0070;
 185                 if (pio > 1) {
 186                         /* Set PPE, IE and TIME */
 187                         master_data |= control << 4;
 188                 }
 189                 pci_read_config_byte(dev, slave_port, &slave_data);
 190                 slave_data &= hwif->channel ? 0x0f : 0xf0;
 191                 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
 192                                (hwif->channel ? 4 : 0);
 193         } else {
 194                 master_data &= ~0x3307;
 195                 if (pio > 1) {
 196                         /* enable PPE, IE and TIME */
 197                         master_data |= control;
 198                 }
 199                 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
 200         }
 201         pci_write_config_word(dev, master_port, master_data);
 202         if (is_slave)
 203                 pci_write_config_byte(dev, slave_port, slave_data);
 204         spin_unlock_irqrestore(&tune_lock, flags);
 205 }
 206
 207 /**
 208  *      piix_set_dma_mode       -       set host controller for DMA mode
 209  *      @drive: drive
 210  *      @speed: DMA mode
 211  *
 212  *      Set a PIIX host controller to the desired DMA mode.  This involves
 213  *      programming the right timing data into the PCI configuration space.
 214  */
 215
 216 static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
 217 {
 218         ide_hwif_t *hwif        = HWIF(drive);
 219         struct pci_dev *dev     = hwif->pci_dev;
 220         u8 maslave              = hwif->channel ? 0x42 : 0x40;
 221         int a_speed             = 3 << (drive->dn * 4);
 222         int u_flag              = 1 << drive->dn;
 223         int v_flag              = 0x01 << drive->dn;
 224         int w_flag              = 0x10 << drive->dn;
 225         int u_speed             = 0;
 226         int                     sitre;
 227         u16                     reg4042, reg4a;
 228         u8                      reg48, reg54, reg55;
 229
 230         pci_read_config_word(dev, maslave, &reg4042);
 231         sitre = (reg4042 & 0x4000) ? 1 : 0;
 232         pci_read_config_byte(dev, 0x48, &reg48);
 233         pci_read_config_word(dev, 0x4a, &reg4a);
 234         pci_read_config_byte(dev, 0x54, &reg54);
 235         pci_read_config_byte(dev, 0x55, &reg55);
 236
 237         switch(speed) {
 238                 case XFER_UDMA_4:
 239                 case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
 240                 case XFER_UDMA_5:
 241                 case XFER_UDMA_3:
 242                 case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
 243                 case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
 244                 case XFER_MW_DMA_2:
 245                 case XFER_MW_DMA_1:
 246                 case XFER_SW_DMA_2:     break;
 247                 default:                return;
 248         }
 249
 250         if (speed >= XFER_UDMA_0) {
 251                 if (!(reg48 & u_flag))
 252                         pci_write_config_byte(dev, 0x48, reg48 | u_flag);
 253                 if (speed == XFER_UDMA_5) {
 254                         pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
 255                 } else {
 256                         pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 257                 }
 258                 if ((reg4a & a_speed) != u_speed)
 259                         pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
 260                 if (speed > XFER_UDMA_2) {
 261                         if (!(reg54 & v_flag))
 262                                 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
 263                 } else
 264                         pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 265         } else {
 266                 if (reg48 & u_flag)
 267                         pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
 268                 if (reg4a & a_speed)
 269                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 270                 if (reg54 & v_flag)
 271                         pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 272                 if (reg55 & w_flag)
 273                         pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 274         }
 275
 276         piix_set_pio_mode(drive, piix_dma_2_pio(speed));
 277 }
 278
 279 /**
 280  *      piix_config_drive_xfer_rate     -       set up an IDE device
 281  *      @drive: IDE drive to configure
 282  *
 283  *      Set up the PIIX interface for the best available speed on this
 284  *      interface, preferring DMA to PIO.
 285  */
 286
 287 static int piix_config_drive_xfer_rate (ide_drive_t *drive)
 288 {
 289         drive->init_speed = 0;
 290
 291         if (ide_tune_dma(drive))
 292                 return 0;
 293
 294         if (ide_use_fast_pio(drive))
 295                 ide_set_max_pio(drive);
 296
 297         return -1;
 298 }
 299
 300 /**
 301  *      piix_is_ichx    -       check if ICHx
 302  *      @dev: PCI device to check
 303  *
 304  *      returns 1 if ICHx, 0 otherwise.
 305  */
 306 static int piix_is_ichx(struct pci_dev *dev)
 307 {
 308         switch (dev->device) {
 309                 case PCI_DEVICE_ID_INTEL_82801EB_1:
 310                 case PCI_DEVICE_ID_INTEL_82801AA_1:
 311                 case PCI_DEVICE_ID_INTEL_82801AB_1:
 312                 case PCI_DEVICE_ID_INTEL_82801BA_8:
 313                 case PCI_DEVICE_ID_INTEL_82801BA_9:
 314                 case PCI_DEVICE_ID_INTEL_82801CA_10:
 315                 case PCI_DEVICE_ID_INTEL_82801CA_11:
 316                 case PCI_DEVICE_ID_INTEL_82801DB_1:
 317                 case PCI_DEVICE_ID_INTEL_82801DB_10:
 318                 case PCI_DEVICE_ID_INTEL_82801DB_11:
 319                 case PCI_DEVICE_ID_INTEL_82801EB_11:
 320                 case PCI_DEVICE_ID_INTEL_82801E_11:
 321                 case PCI_DEVICE_ID_INTEL_ESB_2:
 322                 case PCI_DEVICE_ID_INTEL_ICH6_19:
 323                 case PCI_DEVICE_ID_INTEL_ICH7_21:
 324                 case PCI_DEVICE_ID_INTEL_ESB2_18:
 325                 case PCI_DEVICE_ID_INTEL_ICH8_6:
 326                         return 1;
 327         }
 328
 329         return 0;
 330 }
 331
 332 /**
 333  *      init_chipset_piix       -       set up the PIIX chipset
 334  *      @dev: PCI device to set up
 335  *      @name: Name of the device
 336  *
 337  *      Initialize the PCI device as required. For the PIIX this turns
 338  *      out to be nice and simple
 339  */
 340
 341 static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
 342 {
 343         if (piix_is_ichx(dev)) {
 344                 unsigned int extra = 0;
 345                 pci_read_config_dword(dev, 0x54, &extra);
 346                 pci_write_config_dword(dev, 0x54, extra|0x400);
 347         }
 348
 349         return 0;
 350 }
 351
 352 /**
 353  *      piix_dma_clear_irq      -       clear BMDMA status
 354  *      @drive: IDE drive to clear
 355  *
 356  *      Called from ide_intr() for PIO interrupts
 357  *      to clear BMDMA status as needed by ICHx
 358  */
 359 static void piix_dma_clear_irq(ide_drive_t *drive)
 360 {
 361         ide_hwif_t *hwif = HWIF(drive);
 362         u8 dma_stat;
 363
 364         /* clear the INTR & ERROR bits */
 365         dma_stat = hwif->INB(hwif->dma_status);
 366         /* Should we force the bit as well ? */
 367         hwif->OUTB(dma_stat, hwif->dma_status);
 368 }
 369
 370 struct ich_laptop {
 371         u16 device;
 372         u16 subvendor;
 373         u16 subdevice;
 374 };
 375
 376 /*
 377  *      List of laptops that use short cables rather than 80 wire
 378  */
 379
 380 static const struct ich_laptop ich_laptop[] = {
 381         /* devid, subvendor, subdev */
 382         { 0x27DF, 0x0005, 0x0280 },     /* ICH7 on Acer 5602WLMi */
 383         { 0x27DF, 0x1025, 0x0110 },     /* ICH7 on Acer 3682WLMi */
 384         { 0x27DF, 0x1043, 0x1267 },     /* ICH7 on Asus W5F */
 385         { 0x24CA, 0x1025, 0x0061 },     /* ICH4 on Acer Aspire 2023WLMi */
 386         /* end marker */
 387         { 0, }
 388 };
 389
 390 static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
 391 {
 392         struct pci_dev *pdev = hwif->pci_dev;
 393         const struct ich_laptop *lap = &ich_laptop[0];
 394         u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
 395
 396         /* check for specials */
 397         while (lap->device) {
 398                 if (lap->device == pdev->device &&
 399                     lap->subvendor == pdev->subsystem_vendor &&
 400                     lap->subdevice == pdev->subsystem_device) {
 401                         return ATA_CBL_PATA40_SHORT;
 402                 }
 403                 lap++;
 404         }
 405
 406         pci_read_config_byte(pdev, 0x54, &reg54h);
 407
 408         return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 409 }
 410
 411 /**
 412  *      init_hwif_piix          -       fill in the hwif for the PIIX
 413  *      @hwif: IDE interface
 414  *
 415  *      Set up the ide_hwif_t for the PIIX interface according to the
 416  *      capabilities of the hardware.
 417  */
 418
 419 static void __devinit init_hwif_piix(ide_hwif_t *hwif)
 420 {
 421 #ifndef CONFIG_IA64
 422         if (!hwif->irq)
 423                 hwif->irq = hwif->channel ? 15 : 14;
 424 #endif /* CONFIG_IA64 */
 425
 426         if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
 427                 /* This is a painful system best to let it self tune for now */
 428                 return;
 429         }
 430
 431         hwif->autodma = 0;
 432
 433         hwif->set_pio_mode = &piix_set_pio_mode;
 434         hwif->set_dma_mode = &piix_set_dma_mode;
 435
 436         hwif->drives[0].autotune = 1;
 437         hwif->drives[1].autotune = 1;
 438
 439         if (!hwif->dma_base)
 440                 return;
 441
 442         /* ICHx need to clear the bmdma status for all interrupts */
 443         if (piix_is_ichx(hwif->pci_dev))
 444                 hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
 445
 446         hwif->atapi_dma = 1;
 447
 448         hwif->ultra_mask = hwif->cds->udma_mask;
 449         hwif->mwdma_mask = 0x06;
 450         hwif->swdma_mask = 0x04;
 451
 452         if (hwif->ultra_mask & 0x78) {
 453                 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 454                         hwif->cbl = piix_cable_detect(hwif);
 455         }
 456
 457         if (no_piix_dma)
 458                 hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
 459
 460         hwif->ide_dma_check = &piix_config_drive_xfer_rate;
 461         if (!noautodma)
 462                 hwif->autodma = 1;
 463
 464         hwif->drives[1].autodma = hwif->autodma;
 465         hwif->drives[0].autodma = hwif->autodma;
 466 }
 467
 468 #define DECLARE_PIIX_DEV(name_str, udma) \
 469         {                                               \
 470                 .name           = name_str,             \
 471                 .init_chipset   = init_chipset_piix,    \
 472                 .init_hwif      = init_hwif_piix,       \
 473                 .autodma        = AUTODMA,              \
 474                 .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
 475                 .bootable       = ON_BOARD,             \
 476                 .pio_mask       = ATA_PIO4,             \
 477                 .udma_mask      = udma,                 \
 478         }
 479
 480 static ide_pci_device_t piix_pci_info[] __devinitdata = {
 481         /*  0 */ DECLARE_PIIX_DEV("PIIXa", 0x00),       /* no udma */
 482         /*  1 */ DECLARE_PIIX_DEV("PIIXb", 0x00),       /* no udma */
 483
 484         /*  2 */
 485         {       /*
 486                  * MPIIX actually has only a single IDE channel mapped to
 487                  * the primary or secondary ports depending on the value
 488                  * of the bit 14 of the IDETIM register at offset 0x6c
 489                  */
 490                 .name           = "MPIIX",
 491                 .init_hwif      = init_hwif_piix,
 492                 .autodma        = NODMA,
 493                 .enablebits     = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
 494                 .bootable       = ON_BOARD,
 495                 .host_flags     = IDE_HFLAG_ISA_PORTS,
 496                 .pio_mask       = ATA_PIO4,
 497         },
 498
 499         /*  3 */ DECLARE_PIIX_DEV("PIIX3", 0x00),       /* no udma */
 500         /*  4 */ DECLARE_PIIX_DEV("PIIX4", 0x07),       /* udma0-2 */
 501         /*  5 */ DECLARE_PIIX_DEV("ICH0",  0x07),       /* udma0-2 */
 502         /*  6 */ DECLARE_PIIX_DEV("PIIX4", 0x07),       /* udma0-2 */
 503         /*  7 */ DECLARE_PIIX_DEV("ICH",   0x1f),       /* udma0-4 */
 504         /*  8 */ DECLARE_PIIX_DEV("PIIX4", 0x1f),       /* udma0-4 */
 505         /*  9 */ DECLARE_PIIX_DEV("PIIX4", 0x07),       /* udma0-2 */
 506         /* 10 */ DECLARE_PIIX_DEV("ICH2",  0x3f),       /* udma0-5 */
 507         /* 11 */ DECLARE_PIIX_DEV("ICH2M", 0x3f),       /* udma0-5 */
 508         /* 12 */ DECLARE_PIIX_DEV("ICH3M", 0x3f),       /* udma0-5 */
 509         /* 13 */ DECLARE_PIIX_DEV("ICH3",  0x3f),       /* udma0-5 */
 510         /* 14 */ DECLARE_PIIX_DEV("ICH4",  0x3f),       /* udma0-5 */
 511         /* 15 */ DECLARE_PIIX_DEV("ICH5",  0x3f),       /* udma0-5 */
 512         /* 16 */ DECLARE_PIIX_DEV("C-ICH", 0x3f),       /* udma0-5 */
 513         /* 17 */ DECLARE_PIIX_DEV("ICH4",  0x3f),       /* udma0-5 */
 514         /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA", 0x3f),   /* udma0-5 */
 515         /* 19 */ DECLARE_PIIX_DEV("ICH5",  0x3f),       /* udma0-5 */
 516         /* 20 */ DECLARE_PIIX_DEV("ICH6",  0x3f),       /* udma0-5 */
 517         /* 21 */ DECLARE_PIIX_DEV("ICH7",  0x3f),       /* udma0-5 */
 518         /* 22 */ DECLARE_PIIX_DEV("ICH4",  0x3f),       /* udma0-5 */
 519         /* 23 */ DECLARE_PIIX_DEV("ESB2",  0x3f),       /* udma0-5 */
 520         /* 24 */ DECLARE_PIIX_DEV("ICH8M", 0x3f),       /* udma0-5 */
 521 };
 522
 523 /**
 524  *      piix_init_one   -       called when a PIIX is found
 525  *      @dev: the piix device
 526  *      @id: the matching pci id
 527  *
 528  *      Called when the PCI registration layer (or the IDE initialization)
 529  *      finds a device matching our IDE device tables.
 530  */
 531
 532 static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 533 {
 534         ide_pci_device_t *d = &piix_pci_info[id->driver_data];
 535
 536         return ide_setup_pci_device(dev, d);
 537 }
 538
 539 /**
 540  *      piix_check_450nx        -       Check for problem 450NX setup
 541  *
 542  *      Check for the present of 450NX errata #19 and errata #25. If
 543  *      they are found, disable use of DMA IDE
 544  */
 545
 546 static void __devinit piix_check_450nx(void)
 547 {
 548         struct pci_dev *pdev = NULL;
 549         u16 cfg;
 550         while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
 551         {
 552                 /* Look for 450NX PXB. Check for problem configurations
 553                    A PCI quirk checks bit 6 already */
 554                 pci_read_config_word(pdev, 0x41, &cfg);
 555                 /* Only on the original revision: IDE DMA can hang */
 556                 if (pdev->revision == 0x00)
 557                         no_piix_dma = 1;
 558                 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
 559                 else if (cfg & (1<<14) && pdev->revision < 5)
 560                         no_piix_dma = 2;
 561         }
 562         if(no_piix_dma)
 563                 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
 564         if(no_piix_dma == 2)
 565                 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
 566 }
 567
 568 static struct pci_device_id piix_pci_tbl[] = {
 569         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 570         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 571         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 572         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 573         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 574         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
 575         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
 576         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
 577         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
 578         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX,   PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
 579         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
 580         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
 581         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
 582         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
 583         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
 584         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
 585         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
 586         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
 587 #ifdef CONFIG_BLK_DEV_IDE_SATA
 588         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
 589 #endif
 590         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
 591         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
 592         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21},
 593         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22},
 594         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 23},
 595         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 24},
 596         { 0, },
 597 };
 598 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
 599
 600 static struct pci_driver driver = {
 601         .name           = "PIIX_IDE",
 602         .id_table       = piix_pci_tbl,
 603         .probe          = piix_init_one,
 604 };
 605
 606 static int __init piix_ide_init(void)
 607 {
 608         piix_check_450nx();
 609         return ide_pci_register_driver(&driver);
 610 }
 611
 612 module_init(piix_ide_init);
 613
 614 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
 615 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
 616 MODULE_LICENSE("GPL");