drivers/ide/pci/piix.c

   1 /*
   2  *  linux/drivers/ide/pci/piix.c        Version 0.54    Sep 5, 2007
   3  *
   4  *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
   5  *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   6  *  Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
   7  *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
   8  *
   9  *  May be copied or modified under the terms of the GNU General Public License
  10  *
  11  * Documentation:
  12  *
  13  *      Publically available from Intel web site. Errata documentation
  14  * is also publically available. As an aide to anyone hacking on this
  15  * driver the list of errata that are relevant is below.going back to
  16  * PIIX4. Older device documentation is now a bit tricky to find.
  17  *
  18  * Errata of note:
  19  *
  20  * Unfixable
  21  *      PIIX4    errata #9      - Only on ultra obscure hw
  22  *      ICH3     errata #13     - Not observed to affect real hw
  23  *                                by Intel
  24  *
  25  * Things we must deal with
  26  *      PIIX4   errata #10      - BM IDE hang with non UDMA
  27  *                                (must stop/start dma to recover)
  28  *      440MX   errata #15      - As PIIX4 errata #10
  29  *      PIIX4   errata #15      - Must not read control registers
  30  *                                during a PIO transfer
  31  *      440MX   errata #13      - As PIIX4 errata #15
  32  *      ICH2    errata #21      - DMA mode 0 doesn't work right
  33  *      ICH0/1  errata #55      - As ICH2 errata #21
  34  *      ICH2    spec c #9       - Extra operations needed to handle
  35  *                                drive hotswap [NOT YET SUPPORTED]
  36  *      ICH2    spec c #20      - IDE PRD must not cross a 64K boundary
  37  *                                and must be dword aligned
  38  *      ICH2    spec c #24      - UDMA mode 4,5 t85/86 should be 6ns not 3.3
  39  *
  40  * Should have been BIOS fixed:
  41  *      450NX:  errata #19      - DMA hangs on old 450NX
  42  *      450NX:  errata #20      - DMA hangs on old 450NX
  43  *      450NX:  errata #25      - Corruption with DMA on old 450NX
  44  *      ICH3    errata #15      - IDE deadlock under high load
  45  *                                (BIOS must set dev 31 fn 0 bit 23)
  46  *      ICH3    errata #18      - Don't use native mode
  47  */
  48
  49 #include <linux/types.h>
  50 #include <linux/module.h>
  51 #include <linux/kernel.h>
  52 #include <linux/ioport.h>
  53 #include <linux/pci.h>
  54 #include <linux/hdreg.h>
  55 #include <linux/ide.h>
  56 #include <linux/delay.h>
  57 #include <linux/init.h>
  58
  59 #include <asm/io.h>
  60
  61 static int no_piix_dma;
  62
  63 /**
  64  *      piix_set_pio_mode       -       set host controller for PIO mode
  65  *      @drive: drive
  66  *      @pio: PIO mode number
  67  *
  68  *      Set the interface PIO mode based upon the settings done by AMI BIOS.
  69  */
  70
  71 static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
  72 {
  73         ide_hwif_t *hwif        = HWIF(drive);
  74         struct pci_dev *dev     = to_pci_dev(hwif->dev);
  75         int is_slave            = drive->dn & 1;
  76         int master_port         = hwif->channel ? 0x42 : 0x40;
  77         int slave_port          = 0x44;
  78         unsigned long flags;
  79         u16 master_data;
  80         u8 slave_data;
  81         static DEFINE_SPINLOCK(tune_lock);
  82         int control = 0;
  83
  84                                      /* ISP  RTC */
  85         static const u8 timings[][2]= {
  86                                         { 0, 0 },
  87                                         { 0, 0 },
  88                                         { 1, 0 },
  89                                         { 2, 1 },
  90                                         { 2, 3 }, };
  91
  92         /*
  93          * Master vs slave is synchronized above us but the slave register is
  94          * shared by the two hwifs so the corner case of two slave timeouts in
  95          * parallel must be locked.
  96          */
  97         spin_lock_irqsave(&tune_lock, flags);
  98         pci_read_config_word(dev, master_port, &master_data);
  99
 100         if (pio > 1)
 101                 control |= 1;   /* Programmable timing on */
 102         if (drive->media == ide_disk)
 103                 control |= 4;   /* Prefetch, post write */
 104         if (pio > 2)
 105                 control |= 2;   /* IORDY */
 106         if (is_slave) {
 107                 master_data |=  0x4000;
 108                 master_data &= ~0x0070;
 109                 if (pio > 1) {
 110                         /* Set PPE, IE and TIME */
 111                         master_data |= control << 4;
 112                 }
 113                 pci_read_config_byte(dev, slave_port, &slave_data);
 114                 slave_data &= hwif->channel ? 0x0f : 0xf0;
 115                 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
 116                                (hwif->channel ? 4 : 0);
 117         } else {
 118                 master_data &= ~0x3307;
 119                 if (pio > 1) {
 120                         /* enable PPE, IE and TIME */
 121                         master_data |= control;
 122                 }
 123                 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
 124         }
 125         pci_write_config_word(dev, master_port, master_data);
 126         if (is_slave)
 127                 pci_write_config_byte(dev, slave_port, slave_data);
 128         spin_unlock_irqrestore(&tune_lock, flags);
 129 }
 130
 131 /**
 132  *      piix_set_dma_mode       -       set host controller for DMA mode
 133  *      @drive: drive
 134  *      @speed: DMA mode
 135  *
 136  *      Set a PIIX host controller to the desired DMA mode.  This involves
 137  *      programming the right timing data into the PCI configuration space.
 138  */
 139
 140 static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
 141 {
 142         ide_hwif_t *hwif        = HWIF(drive);
 143         struct pci_dev *dev     = to_pci_dev(hwif->dev);
 144         u8 maslave              = hwif->channel ? 0x42 : 0x40;
 145         int a_speed             = 3 << (drive->dn * 4);
 146         int u_flag              = 1 << drive->dn;
 147         int v_flag              = 0x01 << drive->dn;
 148         int w_flag              = 0x10 << drive->dn;
 149         int u_speed             = 0;
 150         int                     sitre;
 151         u16                     reg4042, reg4a;
 152         u8                      reg48, reg54, reg55;
 153
 154         pci_read_config_word(dev, maslave, &reg4042);
 155         sitre = (reg4042 & 0x4000) ? 1 : 0;
 156         pci_read_config_byte(dev, 0x48, &reg48);
 157         pci_read_config_word(dev, 0x4a, &reg4a);
 158         pci_read_config_byte(dev, 0x54, &reg54);
 159         pci_read_config_byte(dev, 0x55, &reg55);
 160
 161         if (speed >= XFER_UDMA_0) {
 162                 u8 udma = speed - XFER_UDMA_0;
 163
 164                 u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
 165
 166                 if (!(reg48 & u_flag))
 167                         pci_write_config_byte(dev, 0x48, reg48 | u_flag);
 168                 if (speed == XFER_UDMA_5) {
 169                         pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
 170                 } else {
 171                         pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 172                 }
 173                 if ((reg4a & a_speed) != u_speed)
 174                         pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
 175                 if (speed > XFER_UDMA_2) {
 176                         if (!(reg54 & v_flag))
 177                                 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
 178                 } else
 179                         pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 180         } else {
 181                 const u8 mwdma_to_pio[] = { 0, 3, 4 };
 182                 u8 pio;
 183
 184                 if (reg48 & u_flag)
 185                         pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
 186                 if (reg4a & a_speed)
 187                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 188                 if (reg54 & v_flag)
 189                         pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
 190                 if (reg55 & w_flag)
 191                         pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
 192
 193                 if (speed >= XFER_MW_DMA_0)
 194                         pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
 195                 else
 196                         pio = 2; /* only SWDMA2 is allowed */
 197
 198                 piix_set_pio_mode(drive, pio);
 199         }
 200 }
 201
 202 /**
 203  *      init_chipset_ich        -       set up the ICH chipset
 204  *      @dev: PCI device to set up
 205  *      @name: Name of the device
 206  *
 207  *      Initialize the PCI device as required.  For the ICH this turns
 208  *      out to be nice and simple.
 209  */
 210
 211 static unsigned int __devinit init_chipset_ich(struct pci_dev *dev, const char *name)
 212 {
 213         u32 extra = 0;
 214
 215         pci_read_config_dword(dev, 0x54, &extra);
 216         pci_write_config_dword(dev, 0x54, extra | 0x400);
 217
 218         return 0;
 219 }
 220
 221 /**
 222  *      piix_dma_clear_irq      -       clear BMDMA status
 223  *      @drive: IDE drive to clear
 224  *
 225  *      Called from ide_intr() for PIO interrupts
 226  *      to clear BMDMA status as needed by ICHx
 227  */
 228 static void piix_dma_clear_irq(ide_drive_t *drive)
 229 {
 230         ide_hwif_t *hwif = HWIF(drive);
 231         u8 dma_stat;
 232
 233         /* clear the INTR & ERROR bits */
 234         dma_stat = inb(hwif->dma_status);
 235         /* Should we force the bit as well ? */
 236         outb(dma_stat, hwif->dma_status);
 237 }
 238
 239 struct ich_laptop {
 240         u16 device;
 241         u16 subvendor;
 242         u16 subdevice;
 243 };
 244
 245 /*
 246  *      List of laptops that use short cables rather than 80 wire
 247  */
 248
 249 static const struct ich_laptop ich_laptop[] = {
 250         /* devid, subvendor, subdev */
 251         { 0x27DF, 0x1025, 0x0102 },     /* ICH7 on Acer 5602aWLMi */
 252         { 0x27DF, 0x0005, 0x0280 },     /* ICH7 on Acer 5602WLMi */
 253         { 0x27DF, 0x1025, 0x0110 },     /* ICH7 on Acer 3682WLMi */
 254         { 0x27DF, 0x1043, 0x1267 },     /* ICH7 on Asus W5F */
 255         { 0x27DF, 0x103C, 0x30A1 },     /* ICH7 on HP Compaq nc2400 */
 256         { 0x24CA, 0x1025, 0x0061 },     /* ICH4 on Acer Aspire 2023WLMi */
 257         /* end marker */
 258         { 0, }
 259 };
 260
 261 static u8 __devinit piix_cable_detect(ide_hwif_t *hwif)
 262 {
 263         struct pci_dev *pdev = to_pci_dev(hwif->dev);
 264         const struct ich_laptop *lap = &ich_laptop[0];
 265         u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
 266
 267         /* check for specials */
 268         while (lap->device) {
 269                 if (lap->device == pdev->device &&
 270                     lap->subvendor == pdev->subsystem_vendor &&
 271                     lap->subdevice == pdev->subsystem_device) {
 272                         return ATA_CBL_PATA40_SHORT;
 273                 }
 274                 lap++;
 275         }
 276
 277         pci_read_config_byte(pdev, 0x54, &reg54h);
 278
 279         return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 280 }
 281
 282 /**
 283  *      init_hwif_piix          -       fill in the hwif for the PIIX
 284  *      @hwif: IDE interface
 285  *
 286  *      Set up the ide_hwif_t for the PIIX interface according to the
 287  *      capabilities of the hardware.
 288  */
 289
 290 static void __devinit init_hwif_piix(ide_hwif_t *hwif)
 291 {
 292         hwif->set_pio_mode = &piix_set_pio_mode;
 293         hwif->set_dma_mode = &piix_set_dma_mode;
 294
 295         if (!hwif->dma_base)
 296                 return;
 297
 298         if (hwif->ultra_mask & 0x78) {
 299                 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 300                         hwif->cbl = piix_cable_detect(hwif);
 301         }
 302
 303         if (no_piix_dma)
 304                 hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
 305 }
 306
 307 static void __devinit init_hwif_ich(ide_hwif_t *hwif)
 308 {
 309         init_hwif_piix(hwif);
 310
 311         /* ICHx need to clear the BMDMA status for all interrupts */
 312         if (hwif->dma_base)
 313                 hwif->ide_dma_clear_irq = &piix_dma_clear_irq;
 314 }
 315
 316 #ifndef CONFIG_IA64
 317  #define IDE_HFLAGS_PIIX (IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_BOOTABLE)
 318 #else
 319  #define IDE_HFLAGS_PIIX IDE_HFLAG_BOOTABLE
 320 #endif
 321
 322 #define DECLARE_PIIX_DEV(name_str, udma) \
 323         {                                               \
 324                 .name           = name_str,             \
 325                 .init_hwif      = init_hwif_piix,       \
 326                 .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
 327                 .host_flags     = IDE_HFLAGS_PIIX,      \
 328                 .pio_mask       = ATA_PIO4,             \
 329                 .swdma_mask     = ATA_SWDMA2_ONLY,      \
 330                 .mwdma_mask     = ATA_MWDMA12_ONLY,     \
 331                 .udma_mask      = udma,                 \
 332         }
 333
 334 #define DECLARE_ICH_DEV(name_str, udma) \
 335         { \
 336                 .name           = name_str, \
 337                 .init_chipset   = init_chipset_ich, \
 338                 .init_hwif      = init_hwif_ich, \
 339                 .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
 340                 .host_flags     = IDE_HFLAGS_PIIX, \
 341                 .pio_mask       = ATA_PIO4, \
 342                 .swdma_mask     = ATA_SWDMA2_ONLY, \
 343                 .mwdma_mask     = ATA_MWDMA12_ONLY, \
 344                 .udma_mask      = udma, \
 345         }
 346
 347 static const struct ide_port_info piix_pci_info[] __devinitdata = {
 348         /*  0 */ DECLARE_PIIX_DEV("PIIXa",      0x00),  /* no udma */
 349         /*  1 */ DECLARE_PIIX_DEV("PIIXb",      0x00),  /* no udma */
 350
 351         /*  2 */
 352         {       /*
 353                  * MPIIX actually has only a single IDE channel mapped to
 354                  * the primary or secondary ports depending on the value
 355                  * of the bit 14 of the IDETIM register at offset 0x6c
 356                  */
 357                 .name           = "MPIIX",
 358                 .enablebits     = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
 359                 .host_flags     = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA |
 360                                   IDE_HFLAGS_PIIX,
 361                 .pio_mask       = ATA_PIO4,
 362                 /* This is a painful system best to let it self tune for now */
 363         },
 364
 365         /*  3 */ DECLARE_PIIX_DEV("PIIX3",      0x00),  /* no udma */
 366         /*  4 */ DECLARE_PIIX_DEV("PIIX4",      ATA_UDMA2),
 367         /*  5 */ DECLARE_ICH_DEV("ICH0",        ATA_UDMA2),
 368         /*  6 */ DECLARE_PIIX_DEV("PIIX4",      ATA_UDMA2),
 369         /*  7 */ DECLARE_ICH_DEV("ICH",         ATA_UDMA4),
 370         /*  8 */ DECLARE_PIIX_DEV("PIIX4",      ATA_UDMA4),
 371         /*  9 */ DECLARE_PIIX_DEV("PIIX4",      ATA_UDMA2),
 372         /* 10 */ DECLARE_ICH_DEV("ICH2",        ATA_UDMA5),
 373         /* 11 */ DECLARE_ICH_DEV("ICH2M",       ATA_UDMA5),
 374         /* 12 */ DECLARE_ICH_DEV("ICH3M",       ATA_UDMA5),
 375         /* 13 */ DECLARE_ICH_DEV("ICH3",        ATA_UDMA5),
 376         /* 14 */ DECLARE_ICH_DEV("ICH4",        ATA_UDMA5),
 377         /* 15 */ DECLARE_ICH_DEV("ICH5",        ATA_UDMA5),
 378         /* 16 */ DECLARE_ICH_DEV("C-ICH",       ATA_UDMA5),
 379         /* 17 */ DECLARE_ICH_DEV("ICH4",        ATA_UDMA5),
 380         /* 18 */ DECLARE_ICH_DEV("ICH5-SATA",   ATA_UDMA5),
 381         /* 19 */ DECLARE_ICH_DEV("ICH5",        ATA_UDMA5),
 382         /* 20 */ DECLARE_ICH_DEV("ICH6",        ATA_UDMA5),
 383         /* 21 */ DECLARE_ICH_DEV("ICH7",        ATA_UDMA5),
 384         /* 22 */ DECLARE_ICH_DEV("ICH4",        ATA_UDMA5),
 385         /* 23 */ DECLARE_ICH_DEV("ESB2",        ATA_UDMA5),
 386         /* 24 */ DECLARE_ICH_DEV("ICH8M",       ATA_UDMA5),
 387 };
 388
 389 /**
 390  *      piix_init_one   -       called when a PIIX is found
 391  *      @dev: the piix device
 392  *      @id: the matching pci id
 393  *
 394  *      Called when the PCI registration layer (or the IDE initialization)
 395  *      finds a device matching our IDE device tables.
 396  */
 397
 398 static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 399 {
 400         return ide_setup_pci_device(dev, &piix_pci_info[id->driver_data]);
 401 }
 402
 403 /**
 404  *      piix_check_450nx        -       Check for problem 450NX setup
 405  *
 406  *      Check for the present of 450NX errata #19 and errata #25. If
 407  *      they are found, disable use of DMA IDE
 408  */
 409
 410 static void __devinit piix_check_450nx(void)
 411 {
 412         struct pci_dev *pdev = NULL;
 413         u16 cfg;
 414         while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
 415         {
 416                 /* Look for 450NX PXB. Check for problem configurations
 417                    A PCI quirk checks bit 6 already */
 418                 pci_read_config_word(pdev, 0x41, &cfg);
 419                 /* Only on the original revision: IDE DMA can hang */
 420                 if (pdev->revision == 0x00)
 421                         no_piix_dma = 1;
 422                 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
 423                 else if (cfg & (1<<14) && pdev->revision < 5)
 424                         no_piix_dma = 2;
 425         }
 426         if(no_piix_dma)
 427                 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
 428         if(no_piix_dma == 2)
 429                 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
 430 }
 431
 432 static const struct pci_device_id piix_pci_tbl[] = {
 433         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0),   0 },
 434         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1),   1 },
 435         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX),     2 },
 436         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1),   3 },
 437         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB),     4 },
 438         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1),   5 },
 439         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1),   6 },
 440         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1),   7 },
 441         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1),   8 },
 442         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX),     9 },
 443         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9),  10 },
 444         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8),  11 },
 445         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 12 },
 446         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 13 },
 447         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 14 },
 448         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 15 },
 449         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11),  16 },
 450         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 17 },
 451 #ifdef CONFIG_BLK_DEV_IDE_SATA
 452         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1),  18 },
 453 #endif
 454         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2),      19 },
 455         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19),    20 },
 456         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21),    21 },
 457         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1),  22 },
 458         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18),    23 },
 459         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6),     24 },
 460         { 0, },
 461 };
 462 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
 463
 464 static struct pci_driver driver = {
 465         .name           = "PIIX_IDE",
 466         .id_table       = piix_pci_tbl,
 467         .probe          = piix_init_one,
 468 };
 469
 470 static int __init piix_ide_init(void)
 471 {
 472         piix_check_450nx();
 473         return ide_pci_register_driver(&driver);
 474 }
 475
 476 module_init(piix_ide_init);
 477
 478 MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
 479 MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
 480 MODULE_LICENSE("GPL");