drivers/ide/pci/scc_pata.c

   1 /*
   2  * Support for IDE interfaces on Celleb platform
   3  *
   4  * (C) Copyright 2006 TOSHIBA CORPORATION
   5  *
   6  * This code is based on drivers/ide/pci/siimage.c:
   7  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   8  * Copyright (C) 2003           Red Hat <alan@redhat.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, write to the Free Software Foundation, Inc.,
  22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23  */
  24
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/delay.h>
  29 #include <linux/hdreg.h>
  30 #include <linux/ide.h>
  31 #include <linux/init.h>
  32
  33 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA            0x01b4
  34
  35 #define SCC_PATA_NAME           "scc IDE"
  36
  37 #define TDVHSEL_MASTER          0x00000001
  38 #define TDVHSEL_SLAVE           0x00000004
  39
  40 #define MODE_JCUSFEN            0x00000080
  41
  42 #define CCKCTRL_ATARESET        0x00040000
  43 #define CCKCTRL_BUFCNT          0x00020000
  44 #define CCKCTRL_CRST            0x00010000
  45 #define CCKCTRL_OCLKEN          0x00000100
  46 #define CCKCTRL_ATACLKOEN       0x00000002
  47 #define CCKCTRL_LCLKEN          0x00000001
  48
  49 #define QCHCD_IOS_SS            0x00000001
  50
  51 #define QCHSD_STPDIAG           0x00020000
  52
  53 #define INTMASK_MSK             0xD1000012
  54 #define INTSTS_SERROR           0x80000000
  55 #define INTSTS_PRERR            0x40000000
  56 #define INTSTS_RERR             0x10000000
  57 #define INTSTS_ICERR            0x01000000
  58 #define INTSTS_BMSINT           0x00000010
  59 #define INTSTS_BMHE             0x00000008
  60 #define INTSTS_IOIRQS           0x00000004
  61 #define INTSTS_INTRQ            0x00000002
  62 #define INTSTS_ACTEINT          0x00000001
  63
  64 #define ECMODE_VALUE 0x01
  65
  66 static struct scc_ports {
  67         unsigned long ctl, dma;
  68         unsigned char hwif_id;  /* for removing hwif from system */
  69 } scc_ports[MAX_HWIFS];
  70
  71 /* PIO transfer mode  table */
  72 /* JCHST */
  73 static unsigned long JCHSTtbl[2][7] = {
  74         {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00},   /* 100MHz */
  75         {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00}    /* 133MHz */
  76 };
  77
  78 /* JCHHT */
  79 static unsigned long JCHHTtbl[2][7] = {
  80         {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00},   /* 100MHz */
  81         {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}    /* 133MHz */
  82 };
  83
  84 /* JCHCT */
  85 static unsigned long JCHCTtbl[2][7] = {
  86         {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00},   /* 100MHz */
  87         {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00}    /* 133MHz */
  88 };
  89
  90
  91 /* DMA transfer mode  table */
  92 /* JCHDCTM/JCHDCTS */
  93 static unsigned long JCHDCTxtbl[2][7] = {
  94         {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00},   /* 100MHz */
  95         {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00}    /* 133MHz */
  96 };
  97
  98 /* JCSTWTM/JCSTWTS  */
  99 static unsigned long JCSTWTxtbl[2][7] = {
 100         {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00},   /* 100MHz */
 101         {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 102 };
 103
 104 /* JCTSS */
 105 static unsigned long JCTSStbl[2][7] = {
 106         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00},   /* 100MHz */
 107         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05}    /* 133MHz */
 108 };
 109
 110 /* JCENVT */
 111 static unsigned long JCENVTtbl[2][7] = {
 112         {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},   /* 100MHz */
 113         {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 114 };
 115
 116 /* JCACTSELS/JCACTSELM */
 117 static unsigned long JCACTSELtbl[2][7] = {
 118         {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00},   /* 100MHz */
 119         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}    /* 133MHz */
 120 };
 121
 122
 123 static u8 scc_ide_inb(unsigned long port)
 124 {
 125         u32 data = in_be32((void*)port);
 126         return (u8)data;
 127 }
 128
 129 static u16 scc_ide_inw(unsigned long port)
 130 {
 131         u32 data = in_be32((void*)port);
 132         return (u16)data;
 133 }
 134
 135 static void scc_ide_insw(unsigned long port, void *addr, u32 count)
 136 {
 137         u16 *ptr = (u16 *)addr;
 138         while (count--) {
 139                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 140         }
 141 }
 142
 143 static void scc_ide_insl(unsigned long port, void *addr, u32 count)
 144 {
 145         u16 *ptr = (u16 *)addr;
 146         while (count--) {
 147                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 148                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 149         }
 150 }
 151
 152 static void scc_ide_outb(u8 addr, unsigned long port)
 153 {
 154         out_be32((void*)port, addr);
 155 }
 156
 157 static void scc_ide_outw(u16 addr, unsigned long port)
 158 {
 159         out_be32((void*)port, addr);
 160 }
 161
 162 static void
 163 scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
 164 {
 165         ide_hwif_t *hwif = HWIF(drive);
 166
 167         out_be32((void*)port, addr);
 168         eieio();
 169         in_be32((void*)(hwif->dma_base + 0x01c));
 170         eieio();
 171 }
 172
 173 static void
 174 scc_ide_outsw(unsigned long port, void *addr, u32 count)
 175 {
 176         u16 *ptr = (u16 *)addr;
 177         while (count--) {
 178                 out_be32((void*)port, cpu_to_le16(*ptr++));
 179         }
 180 }
 181
 182 static void
 183 scc_ide_outsl(unsigned long port, void *addr, u32 count)
 184 {
 185         u16 *ptr = (u16 *)addr;
 186         while (count--) {
 187                 out_be32((void*)port, cpu_to_le16(*ptr++));
 188                 out_be32((void*)port, cpu_to_le16(*ptr++));
 189         }
 190 }
 191
 192 /**
 193  *      scc_tune_pio    -       tune a drive PIO mode
 194  *      @drive: drive to tune
 195  *      @mode_wanted: the target operating mode
 196  *
 197  *      Load the timing settings for this device mode into the
 198  *      controller.
 199  */
 200
 201 static void scc_tune_pio(ide_drive_t *drive, const u8 pio)
 202 {
 203         ide_hwif_t *hwif = HWIF(drive);
 204         struct scc_ports *ports = ide_get_hwifdata(hwif);
 205         unsigned long ctl_base = ports->ctl;
 206         unsigned long cckctrl_port = ctl_base + 0xff0;
 207         unsigned long piosht_port = ctl_base + 0x000;
 208         unsigned long pioct_port = ctl_base + 0x004;
 209         unsigned long reg;
 210         int offset;
 211
 212         reg = in_be32((void __iomem *)cckctrl_port);
 213         if (reg & CCKCTRL_ATACLKOEN) {
 214                 offset = 1; /* 133MHz */
 215         } else {
 216                 offset = 0; /* 100MHz */
 217         }
 218         reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
 219         out_be32((void __iomem *)piosht_port, reg);
 220         reg = JCHCTtbl[offset][pio];
 221         out_be32((void __iomem *)pioct_port, reg);
 222 }
 223
 224 static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
 225 {
 226         scc_tune_pio(drive, pio);
 227         ide_config_drive_speed(drive, XFER_PIO_0 + pio);
 228 }
 229
 230 /**
 231  *      scc_tune_chipset        -       tune a drive DMA mode
 232  *      @drive: Drive to set up
 233  *      @speed: speed we want to achieve
 234  *
 235  *      Load the timing settings for this device mode into the
 236  *      controller.
 237  */
 238
 239 static int scc_tune_chipset(ide_drive_t *drive, const u8 speed)
 240 {
 241         ide_hwif_t *hwif = HWIF(drive);
 242         struct scc_ports *ports = ide_get_hwifdata(hwif);
 243         unsigned long ctl_base = ports->ctl;
 244         unsigned long cckctrl_port = ctl_base + 0xff0;
 245         unsigned long mdmact_port = ctl_base + 0x008;
 246         unsigned long mcrcst_port = ctl_base + 0x00c;
 247         unsigned long sdmact_port = ctl_base + 0x010;
 248         unsigned long scrcst_port = ctl_base + 0x014;
 249         unsigned long udenvt_port = ctl_base + 0x018;
 250         unsigned long tdvhsel_port   = ctl_base + 0x020;
 251         int is_slave = (&hwif->drives[1] == drive);
 252         int offset, idx;
 253         unsigned long reg;
 254         unsigned long jcactsel;
 255
 256         reg = in_be32((void __iomem *)cckctrl_port);
 257         if (reg & CCKCTRL_ATACLKOEN) {
 258                 offset = 1; /* 133MHz */
 259         } else {
 260                 offset = 0; /* 100MHz */
 261         }
 262
 263         switch (speed) {
 264         case XFER_UDMA_6:
 265         case XFER_UDMA_5:
 266         case XFER_UDMA_4:
 267         case XFER_UDMA_3:
 268         case XFER_UDMA_2:
 269         case XFER_UDMA_1:
 270         case XFER_UDMA_0:
 271                 idx = speed - XFER_UDMA_0;
 272                 break;
 273         default:
 274                 return 1;
 275         }
 276
 277         jcactsel = JCACTSELtbl[offset][idx];
 278         if (is_slave) {
 279                 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
 280                 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
 281                 jcactsel = jcactsel << 2;
 282                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
 283         } else {
 284                 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
 285                 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
 286                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
 287         }
 288         reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
 289         out_be32((void __iomem *)udenvt_port, reg);
 290
 291         return ide_config_drive_speed(drive, speed);
 292 }
 293
 294 /**
 295  *      scc_configure_drive_for_dma     -       set up for DMA transfers
 296  *      @drive: drive we are going to set up
 297  *
 298  *      Set up the drive for DMA, tune the controller and drive as
 299  *      required.
 300  *      If the drive isn't suitable for DMA or we hit other problems
 301  *      then we will drop down to PIO and set up PIO appropriately.
 302  *      (return -1)
 303  */
 304
 305 static int scc_config_drive_for_dma(ide_drive_t *drive)
 306 {
 307         if (ide_tune_dma(drive))
 308                 return 0;
 309
 310         if (ide_use_fast_pio(drive))
 311                 ide_set_max_pio(drive);
 312
 313         return -1;
 314 }
 315
 316 /**
 317  *      scc_ide_dma_setup       -       begin a DMA phase
 318  *      @drive: target device
 319  *
 320  *      Build an IDE DMA PRD (IDE speak for scatter gather table)
 321  *      and then set up the DMA transfer registers.
 322  *
 323  *      Returns 0 on success. If a PIO fallback is required then 1
 324  *      is returned.
 325  */
 326
 327 static int scc_dma_setup(ide_drive_t *drive)
 328 {
 329         ide_hwif_t *hwif = drive->hwif;
 330         struct request *rq = HWGROUP(drive)->rq;
 331         unsigned int reading;
 332         u8 dma_stat;
 333
 334         if (rq_data_dir(rq))
 335                 reading = 0;
 336         else
 337                 reading = 1 << 3;
 338
 339         /* fall back to pio! */
 340         if (!ide_build_dmatable(drive, rq)) {
 341                 ide_map_sg(drive, rq);
 342                 return 1;
 343         }
 344
 345         /* PRD table */
 346         out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
 347
 348         /* specify r/w */
 349         out_be32((void __iomem *)hwif->dma_command, reading);
 350
 351         /* read dma_status for INTR & ERROR flags */
 352         dma_stat = in_be32((void __iomem *)hwif->dma_status);
 353
 354         /* clear INTR & ERROR flags */
 355         out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
 356         drive->waiting_for_dma = 1;
 357         return 0;
 358 }
 359
 360
 361 /**
 362  *      scc_ide_dma_end -       Stop DMA
 363  *      @drive: IDE drive
 364  *
 365  *      Check and clear INT Status register.
 366  *      Then call __ide_dma_end().
 367  */
 368
 369 static int scc_ide_dma_end(ide_drive_t * drive)
 370 {
 371         ide_hwif_t *hwif = HWIF(drive);
 372         unsigned long intsts_port = hwif->dma_base + 0x014;
 373         u32 reg;
 374         int dma_stat, data_loss = 0;
 375         static int retry = 0;
 376
 377         /* errata A308 workaround: Step5 (check data loss) */
 378         /* We don't check non ide_disk because it is limited to UDMA4 */
 379         if (!(in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
 380             drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
 381                 reg = in_be32((void __iomem *)intsts_port);
 382                 if (!(reg & INTSTS_ACTEINT)) {
 383                         printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
 384                                drive->name);
 385                         data_loss = 1;
 386                         if (retry++) {
 387                                 struct request *rq = HWGROUP(drive)->rq;
 388                                 int unit;
 389                                 /* ERROR_RESET and drive->crc_count are needed
 390                                  * to reduce DMA transfer mode in retry process.
 391                                  */
 392                                 if (rq)
 393                                         rq->errors |= ERROR_RESET;
 394                                 for (unit = 0; unit < MAX_DRIVES; unit++) {
 395                                         ide_drive_t *drive = &hwif->drives[unit];
 396                                         drive->crc_count++;
 397                                 }
 398                         }
 399                 }
 400         }
 401
 402         while (1) {
 403                 reg = in_be32((void __iomem *)intsts_port);
 404
 405                 if (reg & INTSTS_SERROR) {
 406                         printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
 407                         out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
 408
 409                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 410                         continue;
 411                 }
 412
 413                 if (reg & INTSTS_PRERR) {
 414                         u32 maea0, maec0;
 415                         unsigned long ctl_base = hwif->config_data;
 416
 417                         maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
 418                         maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
 419
 420                         printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
 421
 422                         out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
 423
 424                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 425                         continue;
 426                 }
 427
 428                 if (reg & INTSTS_RERR) {
 429                         printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
 430                         out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
 431
 432                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 433                         continue;
 434                 }
 435
 436                 if (reg & INTSTS_ICERR) {
 437                         out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
 438
 439                         printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
 440                         out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
 441                         continue;
 442                 }
 443
 444                 if (reg & INTSTS_BMSINT) {
 445                         printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
 446                         out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
 447
 448                         ide_do_reset(drive);
 449                         continue;
 450                 }
 451
 452                 if (reg & INTSTS_BMHE) {
 453                         out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
 454                         continue;
 455                 }
 456
 457                 if (reg & INTSTS_ACTEINT) {
 458                         out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
 459                         continue;
 460                 }
 461
 462                 if (reg & INTSTS_IOIRQS) {
 463                         out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
 464                         continue;
 465                 }
 466                 break;
 467         }
 468
 469         dma_stat = __ide_dma_end(drive);
 470         if (data_loss)
 471                 dma_stat |= 2; /* emulate DMA error (to retry command) */
 472         return dma_stat;
 473 }
 474
 475 /* returns 1 if dma irq issued, 0 otherwise */
 476 static int scc_dma_test_irq(ide_drive_t *drive)
 477 {
 478         ide_hwif_t *hwif = HWIF(drive);
 479         u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
 480
 481         /* SCC errata A252,A308 workaround: Step4 */
 482         if ((in_be32((void __iomem *)IDE_ALTSTATUS_REG) & ERR_STAT) &&
 483             (int_stat & INTSTS_INTRQ))
 484                 return 1;
 485
 486         /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
 487         if (int_stat & INTSTS_IOIRQS)
 488                 return 1;
 489
 490         if (!drive->waiting_for_dma)
 491                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 492                         drive->name, __FUNCTION__);
 493         return 0;
 494 }
 495
 496 static u8 scc_udma_filter(ide_drive_t *drive)
 497 {
 498         ide_hwif_t *hwif = drive->hwif;
 499         u8 mask = hwif->ultra_mask;
 500
 501         /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
 502         if ((drive->media != ide_disk) && (mask & 0xE0)) {
 503                 printk(KERN_INFO "%s: limit %s to UDMA4\n",
 504                        SCC_PATA_NAME, drive->name);
 505                 mask = 0x1F;
 506         }
 507
 508         return mask;
 509 }
 510
 511 /**
 512  *      setup_mmio_scc  -       map CTRL/BMID region
 513  *      @dev: PCI device we are configuring
 514  *      @name: device name
 515  *
 516  */
 517
 518 static int setup_mmio_scc (struct pci_dev *dev, const char *name)
 519 {
 520         unsigned long ctl_base = pci_resource_start(dev, 0);
 521         unsigned long dma_base = pci_resource_start(dev, 1);
 522         unsigned long ctl_size = pci_resource_len(dev, 0);
 523         unsigned long dma_size = pci_resource_len(dev, 1);
 524         void __iomem *ctl_addr;
 525         void __iomem *dma_addr;
 526         int i;
 527
 528         for (i = 0; i < MAX_HWIFS; i++) {
 529                 if (scc_ports[i].ctl == 0)
 530                         break;
 531         }
 532         if (i >= MAX_HWIFS)
 533                 return -ENOMEM;
 534
 535         if (!request_mem_region(ctl_base, ctl_size, name)) {
 536                 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
 537                 goto fail_0;
 538         }
 539
 540         if (!request_mem_region(dma_base, dma_size, name)) {
 541                 printk(KERN_WARNING "%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME);
 542                 goto fail_1;
 543         }
 544
 545         if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
 546                 goto fail_2;
 547
 548         if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
 549                 goto fail_3;
 550
 551         pci_set_master(dev);
 552         scc_ports[i].ctl = (unsigned long)ctl_addr;
 553         scc_ports[i].dma = (unsigned long)dma_addr;
 554         pci_set_drvdata(dev, (void *) &scc_ports[i]);
 555
 556         return 1;
 557
 558  fail_3:
 559         iounmap(ctl_addr);
 560  fail_2:
 561         release_mem_region(dma_base, dma_size);
 562  fail_1:
 563         release_mem_region(ctl_base, ctl_size);
 564  fail_0:
 565         return -ENOMEM;
 566 }
 567
 568 /**
 569  *      init_setup_scc  -       set up an SCC PATA Controller
 570  *      @dev: PCI device
 571  *      @d: IDE PCI device
 572  *
 573  *      Perform the initial set up for this device.
 574  */
 575
 576 static int __devinit init_setup_scc(struct pci_dev *dev, ide_pci_device_t *d)
 577 {
 578         unsigned long ctl_base;
 579         unsigned long dma_base;
 580         unsigned long cckctrl_port;
 581         unsigned long intmask_port;
 582         unsigned long mode_port;
 583         unsigned long ecmode_port;
 584         unsigned long dma_status_port;
 585         u32 reg = 0;
 586         struct scc_ports *ports;
 587         int rc;
 588
 589         rc = setup_mmio_scc(dev, d->name);
 590         if (rc < 0) {
 591                 return rc;
 592         }
 593
 594         ports = pci_get_drvdata(dev);
 595         ctl_base = ports->ctl;
 596         dma_base = ports->dma;
 597         cckctrl_port = ctl_base + 0xff0;
 598         intmask_port = dma_base + 0x010;
 599         mode_port = ctl_base + 0x024;
 600         ecmode_port = ctl_base + 0xf00;
 601         dma_status_port = dma_base + 0x004;
 602
 603         /* controller initialization */
 604         reg = 0;
 605         out_be32((void*)cckctrl_port, reg);
 606         reg |= CCKCTRL_ATACLKOEN;
 607         out_be32((void*)cckctrl_port, reg);
 608         reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
 609         out_be32((void*)cckctrl_port, reg);
 610         reg |= CCKCTRL_CRST;
 611         out_be32((void*)cckctrl_port, reg);
 612
 613         for (;;) {
 614                 reg = in_be32((void*)cckctrl_port);
 615                 if (reg & CCKCTRL_CRST)
 616                         break;
 617                 udelay(5000);
 618         }
 619
 620         reg |= CCKCTRL_ATARESET;
 621         out_be32((void*)cckctrl_port, reg);
 622
 623         out_be32((void*)ecmode_port, ECMODE_VALUE);
 624         out_be32((void*)mode_port, MODE_JCUSFEN);
 625         out_be32((void*)intmask_port, INTMASK_MSK);
 626
 627         return ide_setup_pci_device(dev, d);
 628 }
 629
 630 /**
 631  *      init_mmio_iops_scc      -       set up the iops for MMIO
 632  *      @hwif: interface to set up
 633  *
 634  */
 635
 636 static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
 637 {
 638         struct pci_dev *dev = hwif->pci_dev;
 639         struct scc_ports *ports = pci_get_drvdata(dev);
 640         unsigned long dma_base = ports->dma;
 641
 642         ide_set_hwifdata(hwif, ports);
 643
 644         hwif->INB = scc_ide_inb;
 645         hwif->INW = scc_ide_inw;
 646         hwif->INSW = scc_ide_insw;
 647         hwif->INSL = scc_ide_insl;
 648         hwif->OUTB = scc_ide_outb;
 649         hwif->OUTBSYNC = scc_ide_outbsync;
 650         hwif->OUTW = scc_ide_outw;
 651         hwif->OUTSW = scc_ide_outsw;
 652         hwif->OUTSL = scc_ide_outsl;
 653
 654         hwif->io_ports[IDE_DATA_OFFSET] = dma_base + 0x20;
 655         hwif->io_ports[IDE_ERROR_OFFSET] = dma_base + 0x24;
 656         hwif->io_ports[IDE_NSECTOR_OFFSET] = dma_base + 0x28;
 657         hwif->io_ports[IDE_SECTOR_OFFSET] = dma_base + 0x2c;
 658         hwif->io_ports[IDE_LCYL_OFFSET] = dma_base + 0x30;
 659         hwif->io_ports[IDE_HCYL_OFFSET] = dma_base + 0x34;
 660         hwif->io_ports[IDE_SELECT_OFFSET] = dma_base + 0x38;
 661         hwif->io_ports[IDE_STATUS_OFFSET] = dma_base + 0x3c;
 662         hwif->io_ports[IDE_CONTROL_OFFSET] = dma_base + 0x40;
 663
 664         hwif->irq = hwif->pci_dev->irq;
 665         hwif->dma_base = dma_base;
 666         hwif->config_data = ports->ctl;
 667         hwif->mmio = 1;
 668 }
 669
 670 /**
 671  *      init_iops_scc   -       set up iops
 672  *      @hwif: interface to set up
 673  *
 674  *      Do the basic setup for the SCC hardware interface
 675  *      and then do the MMIO setup.
 676  */
 677
 678 static void __devinit init_iops_scc(ide_hwif_t *hwif)
 679 {
 680         struct pci_dev *dev =  hwif->pci_dev;
 681         hwif->hwif_data = NULL;
 682         if (pci_get_drvdata(dev) == NULL)
 683                 return;
 684         init_mmio_iops_scc(hwif);
 685 }
 686
 687 /**
 688  *      init_hwif_scc   -       set up hwif
 689  *      @hwif: interface to set up
 690  *
 691  *      We do the basic set up of the interface structure. The SCC
 692  *      requires several custom handlers so we override the default
 693  *      ide DMA handlers appropriately.
 694  */
 695
 696 static void __devinit init_hwif_scc(ide_hwif_t *hwif)
 697 {
 698         struct scc_ports *ports = ide_get_hwifdata(hwif);
 699
 700         ports->hwif_id = hwif->index;
 701
 702         hwif->dma_command = hwif->dma_base;
 703         hwif->dma_status = hwif->dma_base + 0x04;
 704         hwif->dma_prdtable = hwif->dma_base + 0x08;
 705
 706         /* PTERADD */
 707         out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
 708
 709         hwif->dma_setup = scc_dma_setup;
 710         hwif->ide_dma_end = scc_ide_dma_end;
 711         hwif->speedproc = scc_tune_chipset;
 712         hwif->set_pio_mode = scc_set_pio_mode;
 713         hwif->ide_dma_check = scc_config_drive_for_dma;
 714         hwif->ide_dma_test_irq = scc_dma_test_irq;
 715         hwif->udma_filter = scc_udma_filter;
 716
 717         hwif->drives[0].autotune = IDE_TUNE_AUTO;
 718         hwif->drives[1].autotune = IDE_TUNE_AUTO;
 719
 720         if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN) {
 721                 hwif->ultra_mask = 0x7f; /* 133MHz */
 722         } else {
 723                 hwif->ultra_mask = 0x3f; /* 100MHz */
 724         }
 725         hwif->mwdma_mask = 0x00;
 726         hwif->swdma_mask = 0x00;
 727         hwif->atapi_dma = 1;
 728
 729         /* we support 80c cable only. */
 730         hwif->cbl = ATA_CBL_PATA80;
 731
 732         hwif->autodma = 0;
 733         if (!noautodma)
 734                 hwif->autodma = 1;
 735         hwif->drives[0].autodma = hwif->autodma;
 736         hwif->drives[1].autodma = hwif->autodma;
 737 }
 738
 739 #define DECLARE_SCC_DEV(name_str)                       \
 740   {                                                     \
 741       .name             = name_str,                     \
 742       .init_setup       = init_setup_scc,               \
 743       .init_iops        = init_iops_scc,                \
 744       .init_hwif        = init_hwif_scc,                \
 745       .autodma  = AUTODMA,                              \
 746       .bootable = ON_BOARD,                             \
 747       .host_flags       = IDE_HFLAG_SINGLE,             \
 748       .pio_mask         = ATA_PIO4,                     \
 749   }
 750
 751 static ide_pci_device_t scc_chipsets[] __devinitdata = {
 752         /* 0 */ DECLARE_SCC_DEV("sccIDE"),
 753 };
 754
 755 /**
 756  *      scc_init_one    -       pci layer discovery entry
 757  *      @dev: PCI device
 758  *      @id: ident table entry
 759  *
 760  *      Called by the PCI code when it finds an SCC PATA controller.
 761  *      We then use the IDE PCI generic helper to do most of the work.
 762  */
 763
 764 static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 765 {
 766         ide_pci_device_t *d = &scc_chipsets[id->driver_data];
 767         return d->init_setup(dev, d);
 768 }
 769
 770 /**
 771  *      scc_remove      -       pci layer remove entry
 772  *      @dev: PCI device
 773  *
 774  *      Called by the PCI code when it removes an SCC PATA controller.
 775  */
 776
 777 static void __devexit scc_remove(struct pci_dev *dev)
 778 {
 779         struct scc_ports *ports = pci_get_drvdata(dev);
 780         ide_hwif_t *hwif = &ide_hwifs[ports->hwif_id];
 781         unsigned long ctl_base = pci_resource_start(dev, 0);
 782         unsigned long dma_base = pci_resource_start(dev, 1);
 783         unsigned long ctl_size = pci_resource_len(dev, 0);
 784         unsigned long dma_size = pci_resource_len(dev, 1);
 785
 786         if (hwif->dmatable_cpu) {
 787                 pci_free_consistent(hwif->pci_dev,
 788                                     PRD_ENTRIES * PRD_BYTES,
 789                                     hwif->dmatable_cpu,
 790                                     hwif->dmatable_dma);
 791                 hwif->dmatable_cpu = NULL;
 792         }
 793
 794         ide_unregister(hwif->index);
 795
 796         hwif->chipset = ide_unknown;
 797         iounmap((void*)ports->dma);
 798         iounmap((void*)ports->ctl);
 799         release_mem_region(dma_base, dma_size);
 800         release_mem_region(ctl_base, ctl_size);
 801         memset(ports, 0, sizeof(*ports));
 802 }
 803
 804 static struct pci_device_id scc_pci_tbl[] = {
 805         { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 806         { 0, },
 807 };
 808 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
 809
 810 static struct pci_driver driver = {
 811         .name = "SCC IDE",
 812         .id_table = scc_pci_tbl,
 813         .probe = scc_init_one,
 814         .remove = scc_remove,
 815 };
 816
 817 static int scc_ide_init(void)
 818 {
 819         return ide_pci_register_driver(&driver);
 820 }
 821
 822 module_init(scc_ide_init);
 823 /* -- No exit code?
 824 static void scc_ide_exit(void)
 825 {
 826         ide_pci_unregister_driver(&driver);
 827 }
 828 module_exit(scc_ide_exit);
 829  */
 830
 831
 832 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
 833 MODULE_LICENSE("GPL");