2 * Support for IDE interfaces on Celleb platform
4 * (C) Copyright 2006 TOSHIBA CORPORATION
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat <alan@redhat.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29 #include <linux/hdreg.h>
30 #include <linux/ide.h>
31 #include <linux/init.h>
33 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
35 #define SCC_PATA_NAME "scc IDE"
37 #define TDVHSEL_MASTER 0x00000001
38 #define TDVHSEL_SLAVE 0x00000004
40 #define MODE_JCUSFEN 0x00000080
42 #define CCKCTRL_ATARESET 0x00040000
43 #define CCKCTRL_BUFCNT 0x00020000
44 #define CCKCTRL_CRST 0x00010000
45 #define CCKCTRL_OCLKEN 0x00000100
46 #define CCKCTRL_ATACLKOEN 0x00000002
47 #define CCKCTRL_LCLKEN 0x00000001
49 #define QCHCD_IOS_SS 0x00000001
51 #define QCHSD_STPDIAG 0x00020000
53 #define INTMASK_MSK 0xD1000012
54 #define INTSTS_SERROR 0x80000000
55 #define INTSTS_PRERR 0x40000000
56 #define INTSTS_RERR 0x10000000
57 #define INTSTS_ICERR 0x01000000
58 #define INTSTS_BMSINT 0x00000010
59 #define INTSTS_BMHE 0x00000008
60 #define INTSTS_IOIRQS 0x00000004
61 #define INTSTS_INTRQ 0x00000002
62 #define INTSTS_ACTEINT 0x00000001
64 #define ECMODE_VALUE 0x01
66 static struct scc_ports
{
67 unsigned long ctl
, dma
;
68 unsigned char hwif_id
; /* for removing hwif from system */
69 } scc_ports
[MAX_HWIFS
];
71 /* PIO transfer mode table */
73 static unsigned long JCHSTtbl
[2][7] = {
74 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
75 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
79 static unsigned long JCHHTtbl
[2][7] = {
80 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
81 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
85 static unsigned long JCHCTtbl
[2][7] = {
86 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
87 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
91 /* DMA transfer mode table */
93 static unsigned long JCHDCTxtbl
[2][7] = {
94 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
95 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
99 static unsigned long JCSTWTxtbl
[2][7] = {
100 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
101 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
105 static unsigned long JCTSStbl
[2][7] = {
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
107 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
111 static unsigned long JCENVTtbl
[2][7] = {
112 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
113 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
116 /* JCACTSELS/JCACTSELM */
117 static unsigned long JCACTSELtbl
[2][7] = {
118 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
119 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
123 static u8
scc_ide_inb(unsigned long port
)
125 u32 data
= in_be32((void*)port
);
129 static u16
scc_ide_inw(unsigned long port
)
131 u32 data
= in_be32((void*)port
);
135 static void scc_ide_insw(unsigned long port
, void *addr
, u32 count
)
137 u16
*ptr
= (u16
*)addr
;
139 *ptr
++ = le16_to_cpu(in_be32((void*)port
));
143 static void scc_ide_insl(unsigned long port
, void *addr
, u32 count
)
145 u16
*ptr
= (u16
*)addr
;
147 *ptr
++ = le16_to_cpu(in_be32((void*)port
));
148 *ptr
++ = le16_to_cpu(in_be32((void*)port
));
152 static void scc_ide_outb(u8 addr
, unsigned long port
)
154 out_be32((void*)port
, addr
);
157 static void scc_ide_outw(u16 addr
, unsigned long port
)
159 out_be32((void*)port
, addr
);
163 scc_ide_outbsync(ide_drive_t
* drive
, u8 addr
, unsigned long port
)
165 ide_hwif_t
*hwif
= HWIF(drive
);
167 out_be32((void*)port
, addr
);
169 in_be32((void*)(hwif
->dma_base
+ 0x01c));
174 scc_ide_outsw(unsigned long port
, void *addr
, u32 count
)
176 u16
*ptr
= (u16
*)addr
;
178 out_be32((void*)port
, cpu_to_le16(*ptr
++));
183 scc_ide_outsl(unsigned long port
, void *addr
, u32 count
)
185 u16
*ptr
= (u16
*)addr
;
187 out_be32((void*)port
, cpu_to_le16(*ptr
++));
188 out_be32((void*)port
, cpu_to_le16(*ptr
++));
193 * scc_set_pio_mode - set host controller for PIO mode
195 * @pio: PIO mode number
197 * Load the timing settings for this device mode into the
201 static void scc_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
203 ide_hwif_t
*hwif
= HWIF(drive
);
204 struct scc_ports
*ports
= ide_get_hwifdata(hwif
);
205 unsigned long ctl_base
= ports
->ctl
;
206 unsigned long cckctrl_port
= ctl_base
+ 0xff0;
207 unsigned long piosht_port
= ctl_base
+ 0x000;
208 unsigned long pioct_port
= ctl_base
+ 0x004;
212 reg
= in_be32((void __iomem
*)cckctrl_port
);
213 if (reg
& CCKCTRL_ATACLKOEN
) {
214 offset
= 1; /* 133MHz */
216 offset
= 0; /* 100MHz */
218 reg
= JCHSTtbl
[offset
][pio
] << 16 | JCHHTtbl
[offset
][pio
];
219 out_be32((void __iomem
*)piosht_port
, reg
);
220 reg
= JCHCTtbl
[offset
][pio
];
221 out_be32((void __iomem
*)pioct_port
, reg
);
225 * scc_set_dma_mode - set host controller for DMA mode
229 * Load the timing settings for this device mode into the
233 static void scc_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
235 ide_hwif_t
*hwif
= HWIF(drive
);
236 struct scc_ports
*ports
= ide_get_hwifdata(hwif
);
237 unsigned long ctl_base
= ports
->ctl
;
238 unsigned long cckctrl_port
= ctl_base
+ 0xff0;
239 unsigned long mdmact_port
= ctl_base
+ 0x008;
240 unsigned long mcrcst_port
= ctl_base
+ 0x00c;
241 unsigned long sdmact_port
= ctl_base
+ 0x010;
242 unsigned long scrcst_port
= ctl_base
+ 0x014;
243 unsigned long udenvt_port
= ctl_base
+ 0x018;
244 unsigned long tdvhsel_port
= ctl_base
+ 0x020;
245 int is_slave
= (&hwif
->drives
[1] == drive
);
248 unsigned long jcactsel
;
250 reg
= in_be32((void __iomem
*)cckctrl_port
);
251 if (reg
& CCKCTRL_ATACLKOEN
) {
252 offset
= 1; /* 133MHz */
254 offset
= 0; /* 100MHz */
265 idx
= speed
- XFER_UDMA_0
;
271 jcactsel
= JCACTSELtbl
[offset
][idx
];
273 out_be32((void __iomem
*)sdmact_port
, JCHDCTxtbl
[offset
][idx
]);
274 out_be32((void __iomem
*)scrcst_port
, JCSTWTxtbl
[offset
][idx
]);
275 jcactsel
= jcactsel
<< 2;
276 out_be32((void __iomem
*)tdvhsel_port
, (in_be32((void __iomem
*)tdvhsel_port
) & ~TDVHSEL_SLAVE
) | jcactsel
);
278 out_be32((void __iomem
*)mdmact_port
, JCHDCTxtbl
[offset
][idx
]);
279 out_be32((void __iomem
*)mcrcst_port
, JCSTWTxtbl
[offset
][idx
]);
280 out_be32((void __iomem
*)tdvhsel_port
, (in_be32((void __iomem
*)tdvhsel_port
) & ~TDVHSEL_MASTER
) | jcactsel
);
282 reg
= JCTSStbl
[offset
][idx
] << 16 | JCENVTtbl
[offset
][idx
];
283 out_be32((void __iomem
*)udenvt_port
, reg
);
287 * scc_configure_drive_for_dma - set up for DMA transfers
288 * @drive: drive we are going to set up
290 * Set up the drive for DMA, tune the controller and drive as
292 * If the drive isn't suitable for DMA or we hit other problems
293 * then we will drop down to PIO and set up PIO appropriately.
297 static int scc_config_drive_for_dma(ide_drive_t
*drive
)
299 if (ide_tune_dma(drive
))
302 ide_set_max_pio(drive
);
308 * scc_ide_dma_setup - begin a DMA phase
309 * @drive: target device
311 * Build an IDE DMA PRD (IDE speak for scatter gather table)
312 * and then set up the DMA transfer registers.
314 * Returns 0 on success. If a PIO fallback is required then 1
318 static int scc_dma_setup(ide_drive_t
*drive
)
320 ide_hwif_t
*hwif
= drive
->hwif
;
321 struct request
*rq
= HWGROUP(drive
)->rq
;
322 unsigned int reading
;
330 /* fall back to pio! */
331 if (!ide_build_dmatable(drive
, rq
)) {
332 ide_map_sg(drive
, rq
);
337 out_be32((void __iomem
*)hwif
->dma_prdtable
, hwif
->dmatable_dma
);
340 out_be32((void __iomem
*)hwif
->dma_command
, reading
);
342 /* read dma_status for INTR & ERROR flags */
343 dma_stat
= in_be32((void __iomem
*)hwif
->dma_status
);
345 /* clear INTR & ERROR flags */
346 out_be32((void __iomem
*)hwif
->dma_status
, dma_stat
|6);
347 drive
->waiting_for_dma
= 1;
353 * scc_ide_dma_end - Stop DMA
356 * Check and clear INT Status register.
357 * Then call __ide_dma_end().
360 static int scc_ide_dma_end(ide_drive_t
* drive
)
362 ide_hwif_t
*hwif
= HWIF(drive
);
363 unsigned long intsts_port
= hwif
->dma_base
+ 0x014;
365 int dma_stat
, data_loss
= 0;
366 static int retry
= 0;
368 /* errata A308 workaround: Step5 (check data loss) */
369 /* We don't check non ide_disk because it is limited to UDMA4 */
370 if (!(in_be32((void __iomem
*)IDE_ALTSTATUS_REG
) & ERR_STAT
) &&
371 drive
->media
== ide_disk
&& drive
->current_speed
> XFER_UDMA_4
) {
372 reg
= in_be32((void __iomem
*)intsts_port
);
373 if (!(reg
& INTSTS_ACTEINT
)) {
374 printk(KERN_WARNING
"%s: operation failed (transfer data loss)\n",
378 struct request
*rq
= HWGROUP(drive
)->rq
;
380 /* ERROR_RESET and drive->crc_count are needed
381 * to reduce DMA transfer mode in retry process.
384 rq
->errors
|= ERROR_RESET
;
385 for (unit
= 0; unit
< MAX_DRIVES
; unit
++) {
386 ide_drive_t
*drive
= &hwif
->drives
[unit
];
394 reg
= in_be32((void __iomem
*)intsts_port
);
396 if (reg
& INTSTS_SERROR
) {
397 printk(KERN_WARNING
"%s: SERROR\n", SCC_PATA_NAME
);
398 out_be32((void __iomem
*)intsts_port
, INTSTS_SERROR
|INTSTS_BMSINT
);
400 out_be32((void __iomem
*)hwif
->dma_command
, in_be32((void __iomem
*)hwif
->dma_command
) & ~QCHCD_IOS_SS
);
404 if (reg
& INTSTS_PRERR
) {
406 unsigned long ctl_base
= hwif
->config_data
;
408 maea0
= in_be32((void __iomem
*)(ctl_base
+ 0xF50));
409 maec0
= in_be32((void __iomem
*)(ctl_base
+ 0xF54));
411 printk(KERN_WARNING
"%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME
, maea0
, maec0
);
413 out_be32((void __iomem
*)intsts_port
, INTSTS_PRERR
|INTSTS_BMSINT
);
415 out_be32((void __iomem
*)hwif
->dma_command
, in_be32((void __iomem
*)hwif
->dma_command
) & ~QCHCD_IOS_SS
);
419 if (reg
& INTSTS_RERR
) {
420 printk(KERN_WARNING
"%s: Response Error\n", SCC_PATA_NAME
);
421 out_be32((void __iomem
*)intsts_port
, INTSTS_RERR
|INTSTS_BMSINT
);
423 out_be32((void __iomem
*)hwif
->dma_command
, in_be32((void __iomem
*)hwif
->dma_command
) & ~QCHCD_IOS_SS
);
427 if (reg
& INTSTS_ICERR
) {
428 out_be32((void __iomem
*)hwif
->dma_command
, in_be32((void __iomem
*)hwif
->dma_command
) & ~QCHCD_IOS_SS
);
430 printk(KERN_WARNING
"%s: Illegal Configuration\n", SCC_PATA_NAME
);
431 out_be32((void __iomem
*)intsts_port
, INTSTS_ICERR
|INTSTS_BMSINT
);
435 if (reg
& INTSTS_BMSINT
) {
436 printk(KERN_WARNING
"%s: Internal Bus Error\n", SCC_PATA_NAME
);
437 out_be32((void __iomem
*)intsts_port
, INTSTS_BMSINT
);
443 if (reg
& INTSTS_BMHE
) {
444 out_be32((void __iomem
*)intsts_port
, INTSTS_BMHE
);
448 if (reg
& INTSTS_ACTEINT
) {
449 out_be32((void __iomem
*)intsts_port
, INTSTS_ACTEINT
);
453 if (reg
& INTSTS_IOIRQS
) {
454 out_be32((void __iomem
*)intsts_port
, INTSTS_IOIRQS
);
460 dma_stat
= __ide_dma_end(drive
);
462 dma_stat
|= 2; /* emulate DMA error (to retry command) */
466 /* returns 1 if dma irq issued, 0 otherwise */
467 static int scc_dma_test_irq(ide_drive_t
*drive
)
469 ide_hwif_t
*hwif
= HWIF(drive
);
470 u32 int_stat
= in_be32((void __iomem
*)hwif
->dma_base
+ 0x014);
472 /* SCC errata A252,A308 workaround: Step4 */
473 if ((in_be32((void __iomem
*)IDE_ALTSTATUS_REG
) & ERR_STAT
) &&
474 (int_stat
& INTSTS_INTRQ
))
477 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
478 if (int_stat
& INTSTS_IOIRQS
)
481 if (!drive
->waiting_for_dma
)
482 printk(KERN_WARNING
"%s: (%s) called while not waiting\n",
483 drive
->name
, __FUNCTION__
);
487 static u8
scc_udma_filter(ide_drive_t
*drive
)
489 ide_hwif_t
*hwif
= drive
->hwif
;
490 u8 mask
= hwif
->ultra_mask
;
492 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
493 if ((drive
->media
!= ide_disk
) && (mask
& 0xE0)) {
494 printk(KERN_INFO
"%s: limit %s to UDMA4\n",
495 SCC_PATA_NAME
, drive
->name
);
503 * setup_mmio_scc - map CTRL/BMID region
504 * @dev: PCI device we are configuring
509 static int setup_mmio_scc (struct pci_dev
*dev
, const char *name
)
511 unsigned long ctl_base
= pci_resource_start(dev
, 0);
512 unsigned long dma_base
= pci_resource_start(dev
, 1);
513 unsigned long ctl_size
= pci_resource_len(dev
, 0);
514 unsigned long dma_size
= pci_resource_len(dev
, 1);
515 void __iomem
*ctl_addr
;
516 void __iomem
*dma_addr
;
519 for (i
= 0; i
< MAX_HWIFS
; i
++) {
520 if (scc_ports
[i
].ctl
== 0)
526 if (!request_mem_region(ctl_base
, ctl_size
, name
)) {
527 printk(KERN_WARNING
"%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME
);
531 if (!request_mem_region(dma_base
, dma_size
, name
)) {
532 printk(KERN_WARNING
"%s: IDE controller MMIO ports not available.\n", SCC_PATA_NAME
);
536 if ((ctl_addr
= ioremap(ctl_base
, ctl_size
)) == NULL
)
539 if ((dma_addr
= ioremap(dma_base
, dma_size
)) == NULL
)
543 scc_ports
[i
].ctl
= (unsigned long)ctl_addr
;
544 scc_ports
[i
].dma
= (unsigned long)dma_addr
;
545 pci_set_drvdata(dev
, (void *) &scc_ports
[i
]);
552 release_mem_region(dma_base
, dma_size
);
554 release_mem_region(ctl_base
, ctl_size
);
560 * init_setup_scc - set up an SCC PATA Controller
564 * Perform the initial set up for this device.
567 static int __devinit
init_setup_scc(struct pci_dev
*dev
, ide_pci_device_t
*d
)
569 unsigned long ctl_base
;
570 unsigned long dma_base
;
571 unsigned long cckctrl_port
;
572 unsigned long intmask_port
;
573 unsigned long mode_port
;
574 unsigned long ecmode_port
;
575 unsigned long dma_status_port
;
577 struct scc_ports
*ports
;
580 rc
= setup_mmio_scc(dev
, d
->name
);
585 ports
= pci_get_drvdata(dev
);
586 ctl_base
= ports
->ctl
;
587 dma_base
= ports
->dma
;
588 cckctrl_port
= ctl_base
+ 0xff0;
589 intmask_port
= dma_base
+ 0x010;
590 mode_port
= ctl_base
+ 0x024;
591 ecmode_port
= ctl_base
+ 0xf00;
592 dma_status_port
= dma_base
+ 0x004;
594 /* controller initialization */
596 out_be32((void*)cckctrl_port
, reg
);
597 reg
|= CCKCTRL_ATACLKOEN
;
598 out_be32((void*)cckctrl_port
, reg
);
599 reg
|= CCKCTRL_LCLKEN
| CCKCTRL_OCLKEN
;
600 out_be32((void*)cckctrl_port
, reg
);
602 out_be32((void*)cckctrl_port
, reg
);
605 reg
= in_be32((void*)cckctrl_port
);
606 if (reg
& CCKCTRL_CRST
)
611 reg
|= CCKCTRL_ATARESET
;
612 out_be32((void*)cckctrl_port
, reg
);
614 out_be32((void*)ecmode_port
, ECMODE_VALUE
);
615 out_be32((void*)mode_port
, MODE_JCUSFEN
);
616 out_be32((void*)intmask_port
, INTMASK_MSK
);
618 return ide_setup_pci_device(dev
, d
);
622 * init_mmio_iops_scc - set up the iops for MMIO
623 * @hwif: interface to set up
627 static void __devinit
init_mmio_iops_scc(ide_hwif_t
*hwif
)
629 struct pci_dev
*dev
= hwif
->pci_dev
;
630 struct scc_ports
*ports
= pci_get_drvdata(dev
);
631 unsigned long dma_base
= ports
->dma
;
633 ide_set_hwifdata(hwif
, ports
);
635 hwif
->INB
= scc_ide_inb
;
636 hwif
->INW
= scc_ide_inw
;
637 hwif
->INSW
= scc_ide_insw
;
638 hwif
->INSL
= scc_ide_insl
;
639 hwif
->OUTB
= scc_ide_outb
;
640 hwif
->OUTBSYNC
= scc_ide_outbsync
;
641 hwif
->OUTW
= scc_ide_outw
;
642 hwif
->OUTSW
= scc_ide_outsw
;
643 hwif
->OUTSL
= scc_ide_outsl
;
645 hwif
->io_ports
[IDE_DATA_OFFSET
] = dma_base
+ 0x20;
646 hwif
->io_ports
[IDE_ERROR_OFFSET
] = dma_base
+ 0x24;
647 hwif
->io_ports
[IDE_NSECTOR_OFFSET
] = dma_base
+ 0x28;
648 hwif
->io_ports
[IDE_SECTOR_OFFSET
] = dma_base
+ 0x2c;
649 hwif
->io_ports
[IDE_LCYL_OFFSET
] = dma_base
+ 0x30;
650 hwif
->io_ports
[IDE_HCYL_OFFSET
] = dma_base
+ 0x34;
651 hwif
->io_ports
[IDE_SELECT_OFFSET
] = dma_base
+ 0x38;
652 hwif
->io_ports
[IDE_STATUS_OFFSET
] = dma_base
+ 0x3c;
653 hwif
->io_ports
[IDE_CONTROL_OFFSET
] = dma_base
+ 0x40;
655 hwif
->irq
= hwif
->pci_dev
->irq
;
656 hwif
->dma_base
= dma_base
;
657 hwif
->config_data
= ports
->ctl
;
662 * init_iops_scc - set up iops
663 * @hwif: interface to set up
665 * Do the basic setup for the SCC hardware interface
666 * and then do the MMIO setup.
669 static void __devinit
init_iops_scc(ide_hwif_t
*hwif
)
671 struct pci_dev
*dev
= hwif
->pci_dev
;
672 hwif
->hwif_data
= NULL
;
673 if (pci_get_drvdata(dev
) == NULL
)
675 init_mmio_iops_scc(hwif
);
679 * init_hwif_scc - set up hwif
680 * @hwif: interface to set up
682 * We do the basic set up of the interface structure. The SCC
683 * requires several custom handlers so we override the default
684 * ide DMA handlers appropriately.
687 static void __devinit
init_hwif_scc(ide_hwif_t
*hwif
)
689 struct scc_ports
*ports
= ide_get_hwifdata(hwif
);
691 ports
->hwif_id
= hwif
->index
;
693 hwif
->dma_command
= hwif
->dma_base
;
694 hwif
->dma_status
= hwif
->dma_base
+ 0x04;
695 hwif
->dma_prdtable
= hwif
->dma_base
+ 0x08;
698 out_be32((void __iomem
*)(hwif
->dma_base
+ 0x018), hwif
->dmatable_dma
);
700 hwif
->dma_setup
= scc_dma_setup
;
701 hwif
->ide_dma_end
= scc_ide_dma_end
;
702 hwif
->set_pio_mode
= scc_set_pio_mode
;
703 hwif
->set_dma_mode
= scc_set_dma_mode
;
704 hwif
->ide_dma_check
= scc_config_drive_for_dma
;
705 hwif
->ide_dma_test_irq
= scc_dma_test_irq
;
706 hwif
->udma_filter
= scc_udma_filter
;
708 hwif
->drives
[0].autotune
= IDE_TUNE_AUTO
;
709 hwif
->drives
[1].autotune
= IDE_TUNE_AUTO
;
711 if (in_be32((void __iomem
*)(hwif
->config_data
+ 0xff0)) & CCKCTRL_ATACLKOEN
) {
712 hwif
->ultra_mask
= 0x7f; /* 133MHz */
714 hwif
->ultra_mask
= 0x3f; /* 100MHz */
716 hwif
->mwdma_mask
= 0x00;
717 hwif
->swdma_mask
= 0x00;
720 /* we support 80c cable only. */
721 hwif
->cbl
= ATA_CBL_PATA80
;
726 hwif
->drives
[0].autodma
= hwif
->autodma
;
727 hwif
->drives
[1].autodma
= hwif
->autodma
;
730 #define DECLARE_SCC_DEV(name_str) \
733 .init_setup = init_setup_scc, \
734 .init_iops = init_iops_scc, \
735 .init_hwif = init_hwif_scc, \
736 .autodma = AUTODMA, \
737 .bootable = ON_BOARD, \
738 .host_flags = IDE_HFLAG_SINGLE, \
739 .pio_mask = ATA_PIO4, \
742 static ide_pci_device_t scc_chipsets
[] __devinitdata
= {
743 /* 0 */ DECLARE_SCC_DEV("sccIDE"),
747 * scc_init_one - pci layer discovery entry
749 * @id: ident table entry
751 * Called by the PCI code when it finds an SCC PATA controller.
752 * We then use the IDE PCI generic helper to do most of the work.
755 static int __devinit
scc_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
757 ide_pci_device_t
*d
= &scc_chipsets
[id
->driver_data
];
758 return d
->init_setup(dev
, d
);
762 * scc_remove - pci layer remove entry
765 * Called by the PCI code when it removes an SCC PATA controller.
768 static void __devexit
scc_remove(struct pci_dev
*dev
)
770 struct scc_ports
*ports
= pci_get_drvdata(dev
);
771 ide_hwif_t
*hwif
= &ide_hwifs
[ports
->hwif_id
];
772 unsigned long ctl_base
= pci_resource_start(dev
, 0);
773 unsigned long dma_base
= pci_resource_start(dev
, 1);
774 unsigned long ctl_size
= pci_resource_len(dev
, 0);
775 unsigned long dma_size
= pci_resource_len(dev
, 1);
777 if (hwif
->dmatable_cpu
) {
778 pci_free_consistent(hwif
->pci_dev
,
779 PRD_ENTRIES
* PRD_BYTES
,
782 hwif
->dmatable_cpu
= NULL
;
785 ide_unregister(hwif
->index
);
787 hwif
->chipset
= ide_unknown
;
788 iounmap((void*)ports
->dma
);
789 iounmap((void*)ports
->ctl
);
790 release_mem_region(dma_base
, dma_size
);
791 release_mem_region(ctl_base
, ctl_size
);
792 memset(ports
, 0, sizeof(*ports
));
795 static struct pci_device_id scc_pci_tbl
[] = {
796 { PCI_VENDOR_ID_TOSHIBA_2
, PCI_DEVICE_ID_TOSHIBA_SCC_ATA
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
799 MODULE_DEVICE_TABLE(pci
, scc_pci_tbl
);
801 static struct pci_driver driver
= {
803 .id_table
= scc_pci_tbl
,
804 .probe
= scc_init_one
,
805 .remove
= scc_remove
,
808 static int scc_ide_init(void)
810 return ide_pci_register_driver(&driver
);
813 module_init(scc_ide_init
);
815 static void scc_ide_exit(void)
817 ide_pci_unregister_driver(&driver);
819 module_exit(scc_ide_exit);
823 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
824 MODULE_LICENSE("GPL");