drivers/ide/pci/serverworks.c

   1 /*
   2  * linux/drivers/ide/pci/serverworks.c          Version 0.22    Jun 27 2007
   3  *
   4  * Copyright (C) 1998-2000 Michel Aubry
   5  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   6  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   7  * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
   8  * Portions copyright (c) 2001 Sun Microsystems
   9  *
  10  *
  11  * RCC/ServerWorks IDE driver for Linux
  12  *
  13  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  14  *         supports UDMA mode 2 (33 MB/s)
  15  *
  16  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  17  *         all revisions support UDMA mode 4 (66 MB/s)
  18  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  19  *
  20  *         *** The CSB5 does not provide ANY register ***
  21  *         *** to detect 80-conductor cable presence. ***
  22  *
  23  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  24  *
  25  *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  26  *   controller same as the CSB6. Single channel ATA100 only.
  27  *
  28  * Documentation:
  29  *      Available under NDA only. Errata info very hard to get.
  30  *
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/ioport.h>
  37 #include <linux/pci.h>
  38 #include <linux/hdreg.h>
  39 #include <linux/ide.h>
  40 #include <linux/init.h>
  41 #include <linux/delay.h>
  42
  43 #include <asm/io.h>
  44
  45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  46 #define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  47
  48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  49  * can overrun their FIFOs when used with the CSB5 */
  50 static const char *svwks_bad_ata100[] = {
  51         "ST320011A",
  52         "ST340016A",
  53         "ST360021A",
  54         "ST380021A",
  55         NULL
  56 };
  57
  58 static struct pci_dev *isa_dev;
  59
  60 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  61 {
  62         while (*list)
  63                 if (!strcmp(*list++, drive->id->model))
  64                         return 1;
  65         return 0;
  66 }
  67
  68 static u8 svwks_udma_filter(ide_drive_t *drive)
  69 {
  70         struct pci_dev *dev     = HWIF(drive)->pci_dev;
  71         u8 mask = 0;
  72
  73         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  74                 return 0x1f;
  75         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  76                 u32 reg = 0;
  77                 if (isa_dev)
  78                         pci_read_config_dword(isa_dev, 0x64, &reg);
  79
  80                 /*
  81                  *      Don't enable UDMA on disk devices for the moment
  82                  */
  83                 if(drive->media == ide_disk)
  84                         return 0;
  85                 /* Check the OSB4 DMA33 enable bit */
  86                 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
  87         } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
  88                 return 0x07;
  89         } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
  90                 u8 btr = 0, mode;
  91                 pci_read_config_byte(dev, 0x5A, &btr);
  92                 mode = btr & 0x3;
  93
  94                 /* If someone decides to do UDMA133 on CSB5 the same
  95                    issue will bite so be inclusive */
  96                 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
  97                         mode = 2;
  98
  99                 switch(mode) {
 100                 case 3:  mask = 0x3f; break;
 101                 case 2:  mask = 0x1f; break;
 102                 case 1:  mask = 0x07; break;
 103                 default: mask = 0x00; break;
 104                 }
 105         }
 106         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 107              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 108             (!(PCI_FUNC(dev->devfn) & 1)))
 109                 mask = 0x1f;
 110
 111         return mask;
 112 }
 113
 114 static u8 svwks_csb_check (struct pci_dev *dev)
 115 {
 116         switch (dev->device) {
 117                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 118                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 119                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 120                 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 121                         return 1;
 122                 default:
 123                         break;
 124         }
 125         return 0;
 126 }
 127
 128 static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
 129 {
 130         static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 131         static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
 132
 133         struct pci_dev *dev = drive->hwif->pci_dev;
 134
 135         pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
 136
 137         if (svwks_csb_check(dev)) {
 138                 u16 csb_pio = 0;
 139
 140                 pci_read_config_word(dev, 0x4a, &csb_pio);
 141
 142                 csb_pio &= ~(0x0f << (4 * drive->dn));
 143                 csb_pio |= (pio << (4 * drive->dn));
 144
 145                 pci_write_config_word(dev, 0x4a, csb_pio);
 146         }
 147 }
 148
 149 static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed)
 150 {
 151         static const u8 udma_modes[]            = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 152         static const u8 dma_modes[]             = { 0x77, 0x21, 0x20 };
 153         static const u8 drive_pci2[]            = { 0x45, 0x44, 0x47, 0x46 };
 154
 155         ide_hwif_t *hwif        = HWIF(drive);
 156         struct pci_dev *dev     = hwif->pci_dev;
 157         u8 unit                 = (drive->select.b.unit & 0x01);
 158
 159         u8 ultra_enable  = 0, ultra_timing = 0, dma_timing = 0;
 160
 161         /* If we are about to put a disk into UDMA mode we screwed up.
 162            Our code assumes we never _ever_ do this on an OSB4 */
 163
 164         if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
 165                 drive->media == ide_disk && speed >= XFER_UDMA_0)
 166                         BUG();
 167
 168         pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 169         pci_read_config_byte(dev, 0x54, &ultra_enable);
 170
 171         ultra_timing    &= ~(0x0F << (4*unit));
 172         ultra_enable    &= ~(0x01 << drive->dn);
 173
 174         switch(speed) {
 175                 case XFER_MW_DMA_2:
 176                 case XFER_MW_DMA_1:
 177                 case XFER_MW_DMA_0:
 178                         dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
 179                         break;
 180
 181                 case XFER_UDMA_5:
 182                 case XFER_UDMA_4:
 183                 case XFER_UDMA_3:
 184                 case XFER_UDMA_2:
 185                 case XFER_UDMA_1:
 186                 case XFER_UDMA_0:
 187                         dma_timing   |= dma_modes[2];
 188                         ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
 189                         ultra_enable |= (0x01 << drive->dn);
 190                 default:
 191                         break;
 192         }
 193
 194         pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 195         pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 196         pci_write_config_byte(dev, 0x54, ultra_enable);
 197 }
 198
 199 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
 200 {
 201         if (ide_tune_dma(drive))
 202                 return 0;
 203
 204         ide_set_max_pio(drive);
 205
 206         return -1;
 207 }
 208
 209 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
 210 {
 211         unsigned int reg;
 212         u8 btr;
 213
 214         /* force Master Latency Timer value to 64 PCICLKs */
 215         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 216
 217         /* OSB4 : South Bridge and IDE */
 218         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 219                 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 220                           PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 221                 if (isa_dev) {
 222                         pci_read_config_dword(isa_dev, 0x64, &reg);
 223                         reg &= ~0x00002000; /* disable 600ns interrupt mask */
 224                         if(!(reg & 0x00004000))
 225                                 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
 226                         reg |=  0x00004000; /* enable UDMA/33 support */
 227                         pci_write_config_dword(isa_dev, 0x64, reg);
 228                 }
 229         }
 230
 231         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 232         else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 233                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 234                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 235
 236                 /* Third Channel Test */
 237                 if (!(PCI_FUNC(dev->devfn) & 1)) {
 238                         struct pci_dev * findev = NULL;
 239                         u32 reg4c = 0;
 240                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 241                                 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 242                         if (findev) {
 243                                 pci_read_config_dword(findev, 0x4C, &reg4c);
 244                                 reg4c &= ~0x000007FF;
 245                                 reg4c |=  0x00000040;
 246                                 reg4c |=  0x00000020;
 247                                 pci_write_config_dword(findev, 0x4C, reg4c);
 248                                 pci_dev_put(findev);
 249                         }
 250                         outb_p(0x06, 0x0c00);
 251                         dev->irq = inb_p(0x0c01);
 252                 } else {
 253                         struct pci_dev * findev = NULL;
 254                         u8 reg41 = 0;
 255
 256                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 257                                         PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 258                         if (findev) {
 259                                 pci_read_config_byte(findev, 0x41, &reg41);
 260                                 reg41 &= ~0x40;
 261                                 pci_write_config_byte(findev, 0x41, reg41);
 262                                 pci_dev_put(findev);
 263                         }
 264                         /*
 265                          * This is a device pin issue on CSB6.
 266                          * Since there will be a future raid mode,
 267                          * early versions of the chipset require the
 268                          * interrupt pin to be set, and it is a compatibility
 269                          * mode issue.
 270                          */
 271                         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 272                                 dev->irq = 0;
 273                 }
 274 //              pci_read_config_dword(dev, 0x40, &pioreg)
 275 //              pci_write_config_dword(dev, 0x40, 0x99999999);
 276 //              pci_read_config_dword(dev, 0x44, &dmareg);
 277 //              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 278                 /* setup the UDMA Control register
 279                  *
 280                  * 1. clear bit 6 to enable DMA
 281                  * 2. enable DMA modes with bits 0-1
 282                  *      00 : legacy
 283                  *      01 : udma2
 284                  *      10 : udma2/udma4
 285                  *      11 : udma2/udma4/udma5
 286                  */
 287                 pci_read_config_byte(dev, 0x5A, &btr);
 288                 btr &= ~0x40;
 289                 if (!(PCI_FUNC(dev->devfn) & 1))
 290                         btr |= 0x2;
 291                 else
 292                         btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 293                 pci_write_config_byte(dev, 0x5A, btr);
 294         }
 295         /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 296         else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
 297                 pci_read_config_byte(dev, 0x5A, &btr);
 298                 btr &= ~0x40;
 299                 btr |= 0x3;
 300                 pci_write_config_byte(dev, 0x5A, btr);
 301         }
 302
 303         return dev->irq;
 304 }
 305
 306 static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif)
 307 {
 308         return ATA_CBL_PATA80;
 309 }
 310
 311 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 312  * of the subsystem device ID indicate presence of an 80-pin cable.
 313  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 314  * Bit 15 set   = secondary IDE channel has 80-pin cable.
 315  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 316  * Bit 14 set   = primary IDE channel has 80-pin cable.
 317  */
 318 static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif)
 319 {
 320         struct pci_dev *dev = hwif->pci_dev;
 321         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 322             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 323             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 324              dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 325                 return ((1 << (hwif->channel + 14)) &
 326                         dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 327         return ATA_CBL_PATA40;
 328 }
 329
 330 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
 331  * detect issue by attaching the drives directly to the board.
 332  * This check follows the Dell precedent (how scary is that?!)
 333  *
 334  * WARNING: this only works on Alpine hardware!
 335  */
 336 static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif)
 337 {
 338         struct pci_dev *dev = hwif->pci_dev;
 339         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 340             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 341             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 342                 return ((1 << (hwif->channel + 14)) &
 343                         dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
 344         return ATA_CBL_PATA40;
 345 }
 346
 347 static u8 __devinit ata66_svwks(ide_hwif_t *hwif)
 348 {
 349         struct pci_dev *dev = hwif->pci_dev;
 350
 351         /* Server Works */
 352         if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 353                 return ata66_svwks_svwks (hwif);
 354
 355         /* Dell PowerEdge */
 356         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 357                 return ata66_svwks_dell (hwif);
 358
 359         /* Cobalt Alpine */
 360         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 361                 return ata66_svwks_cobalt (hwif);
 362
 363         /* Per Specified Design by OEM, and ASIC Architect */
 364         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 365             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 366                 return ATA_CBL_PATA80;
 367
 368         return ATA_CBL_PATA40;
 369 }
 370
 371 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
 372 {
 373         if (!hwif->irq)
 374                 hwif->irq = hwif->channel ? 15 : 14;
 375
 376         hwif->set_pio_mode = &svwks_set_pio_mode;
 377         hwif->set_dma_mode = &svwks_set_dma_mode;
 378         hwif->udma_filter = &svwks_udma_filter;
 379
 380         hwif->atapi_dma = 1;
 381
 382         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
 383                 hwif->ultra_mask = 0x3f;
 384
 385         hwif->mwdma_mask = 0x07;
 386
 387         hwif->autodma = 0;
 388
 389         hwif->drives[0].autotune = 1;
 390         hwif->drives[1].autotune = 1;
 391
 392         if (!hwif->dma_base)
 393                 return;
 394
 395         hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
 396         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 397                 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 398                         hwif->cbl = ata66_svwks(hwif);
 399         }
 400         if (!noautodma)
 401                 hwif->autodma = 1;
 402
 403         hwif->drives[0].autodma = hwif->drives[1].autodma = 1;
 404 }
 405
 406 static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
 407 {
 408         return ide_setup_pci_device(dev, d);
 409 }
 410
 411 static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
 412 {
 413         if (!(PCI_FUNC(dev->devfn) & 1)) {
 414                 d->bootable = NEVER_BOARD;
 415                 if (dev->resource[0].start == 0x01f1)
 416                         d->bootable = ON_BOARD;
 417         }
 418
 419         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
 420             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
 421             (!(PCI_FUNC(dev->devfn) & 1)))
 422                 d->host_flags |= IDE_HFLAG_SINGLE;
 423         else
 424                 d->host_flags &= ~IDE_HFLAG_SINGLE;
 425
 426         return ide_setup_pci_device(dev, d);
 427 }
 428
 429 static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
 430         {       /* 0 */
 431                 .name           = "SvrWks OSB4",
 432                 .init_setup     = init_setup_svwks,
 433                 .init_chipset   = init_chipset_svwks,
 434                 .init_hwif      = init_hwif_svwks,
 435                 .autodma        = AUTODMA,
 436                 .bootable       = ON_BOARD,
 437                 .pio_mask       = ATA_PIO4,
 438         },{     /* 1 */
 439                 .name           = "SvrWks CSB5",
 440                 .init_setup     = init_setup_svwks,
 441                 .init_chipset   = init_chipset_svwks,
 442                 .init_hwif      = init_hwif_svwks,
 443                 .autodma        = AUTODMA,
 444                 .bootable       = ON_BOARD,
 445                 .pio_mask       = ATA_PIO4,
 446         },{     /* 2 */
 447                 .name           = "SvrWks CSB6",
 448                 .init_setup     = init_setup_csb6,
 449                 .init_chipset   = init_chipset_svwks,
 450                 .init_hwif      = init_hwif_svwks,
 451                 .autodma        = AUTODMA,
 452                 .bootable       = ON_BOARD,
 453                 .pio_mask       = ATA_PIO4,
 454         },{     /* 3 */
 455                 .name           = "SvrWks CSB6",
 456                 .init_setup     = init_setup_csb6,
 457                 .init_chipset   = init_chipset_svwks,
 458                 .init_hwif      = init_hwif_svwks,
 459                 .autodma        = AUTODMA,
 460                 .bootable       = ON_BOARD,
 461                 .host_flags     = IDE_HFLAG_SINGLE,
 462                 .pio_mask       = ATA_PIO4,
 463         },{     /* 4 */
 464                 .name           = "SvrWks HT1000",
 465                 .init_setup     = init_setup_svwks,
 466                 .init_chipset   = init_chipset_svwks,
 467                 .init_hwif      = init_hwif_svwks,
 468                 .autodma        = AUTODMA,
 469                 .bootable       = ON_BOARD,
 470                 .host_flags     = IDE_HFLAG_SINGLE,
 471                 .pio_mask       = ATA_PIO4,
 472         }
 473 };
 474
 475 /**
 476  *      svwks_init_one  -       called when a OSB/CSB is found
 477  *      @dev: the svwks device
 478  *      @id: the matching pci id
 479  *
 480  *      Called when the PCI registration layer (or the IDE initialization)
 481  *      finds a device matching our IDE device tables.
 482  */
 483
 484 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 485 {
 486         ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
 487
 488         return d->init_setup(dev, d);
 489 }
 490
 491 static struct pci_device_id svwks_pci_tbl[] = {
 492         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 493         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 494         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 495         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 496         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 497         { 0, },
 498 };
 499 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
 500
 501 static struct pci_driver driver = {
 502         .name           = "Serverworks_IDE",
 503         .id_table       = svwks_pci_tbl,
 504         .probe          = svwks_init_one,
 505 };
 506
 507 static int __init svwks_ide_init(void)
 508 {
 509         return ide_pci_register_driver(&driver);
 510 }
 511
 512 module_init(svwks_ide_init);
 513
 514 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
 515 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 516 MODULE_LICENSE("GPL");