ide: add ->cable_detect method to ide_hwif_t
[deliverable/linux.git] / drivers / ide / pci / serverworks.c
1 /*
2 * Copyright (C) 1998-2000 Michel Aubry
3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Portions copyright (c) 2001 Sun Microsystems
7 *
8 *
9 * RCC/ServerWorks IDE driver for Linux
10 *
11 * OSB4: `Open South Bridge' IDE Interface (fn 1)
12 * supports UDMA mode 2 (33 MB/s)
13 *
14 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
15 * all revisions support UDMA mode 4 (66 MB/s)
16 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
17 *
18 * *** The CSB5 does not provide ANY register ***
19 * *** to detect 80-conductor cable presence. ***
20 *
21 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
22 *
23 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
24 * controller same as the CSB6. Single channel ATA100 only.
25 *
26 * Documentation:
27 * Available under NDA only. Errata info very hard to get.
28 *
29 */
30
31 #include <linux/types.h>
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/ioport.h>
35 #include <linux/pci.h>
36 #include <linux/hdreg.h>
37 #include <linux/ide.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40
41 #include <asm/io.h>
42
43 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
44 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
45
46 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
47 * can overrun their FIFOs when used with the CSB5 */
48 static const char *svwks_bad_ata100[] = {
49 "ST320011A",
50 "ST340016A",
51 "ST360021A",
52 "ST380021A",
53 NULL
54 };
55
56 static struct pci_dev *isa_dev;
57
58 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
59 {
60 while (*list)
61 if (!strcmp(*list++, drive->id->model))
62 return 1;
63 return 0;
64 }
65
66 static u8 svwks_udma_filter(ide_drive_t *drive)
67 {
68 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
69 u8 mask = 0;
70
71 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
72 return 0x1f;
73 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
74 u32 reg = 0;
75 if (isa_dev)
76 pci_read_config_dword(isa_dev, 0x64, &reg);
77
78 /*
79 * Don't enable UDMA on disk devices for the moment
80 */
81 if(drive->media == ide_disk)
82 return 0;
83 /* Check the OSB4 DMA33 enable bit */
84 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
85 } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
86 return 0x07;
87 } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
88 u8 btr = 0, mode;
89 pci_read_config_byte(dev, 0x5A, &btr);
90 mode = btr & 0x3;
91
92 /* If someone decides to do UDMA133 on CSB5 the same
93 issue will bite so be inclusive */
94 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
95 mode = 2;
96
97 switch(mode) {
98 case 3: mask = 0x3f; break;
99 case 2: mask = 0x1f; break;
100 case 1: mask = 0x07; break;
101 default: mask = 0x00; break;
102 }
103 }
104 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
105 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
106 (!(PCI_FUNC(dev->devfn) & 1)))
107 mask = 0x1f;
108
109 return mask;
110 }
111
112 static u8 svwks_csb_check (struct pci_dev *dev)
113 {
114 switch (dev->device) {
115 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
116 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
117 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
118 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
119 return 1;
120 default:
121 break;
122 }
123 return 0;
124 }
125
126 static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
127 {
128 static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
129 static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
130
131 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
132
133 pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
134
135 if (svwks_csb_check(dev)) {
136 u16 csb_pio = 0;
137
138 pci_read_config_word(dev, 0x4a, &csb_pio);
139
140 csb_pio &= ~(0x0f << (4 * drive->dn));
141 csb_pio |= (pio << (4 * drive->dn));
142
143 pci_write_config_word(dev, 0x4a, csb_pio);
144 }
145 }
146
147 static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed)
148 {
149 static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
150 static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
151 static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
152
153 ide_hwif_t *hwif = HWIF(drive);
154 struct pci_dev *dev = to_pci_dev(hwif->dev);
155 u8 unit = (drive->select.b.unit & 0x01);
156
157 u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
158
159 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
160 pci_read_config_byte(dev, 0x54, &ultra_enable);
161
162 ultra_timing &= ~(0x0F << (4*unit));
163 ultra_enable &= ~(0x01 << drive->dn);
164
165 if (speed >= XFER_UDMA_0) {
166 dma_timing |= dma_modes[2];
167 ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
168 ultra_enable |= (0x01 << drive->dn);
169 } else if (speed >= XFER_MW_DMA_0)
170 dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
171
172 pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
173 pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
174 pci_write_config_byte(dev, 0x54, ultra_enable);
175 }
176
177 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
178 {
179 unsigned int reg;
180 u8 btr;
181
182 /* force Master Latency Timer value to 64 PCICLKs */
183 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
184
185 /* OSB4 : South Bridge and IDE */
186 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
187 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
188 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
189 if (isa_dev) {
190 pci_read_config_dword(isa_dev, 0x64, &reg);
191 reg &= ~0x00002000; /* disable 600ns interrupt mask */
192 if(!(reg & 0x00004000))
193 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
194 reg |= 0x00004000; /* enable UDMA/33 support */
195 pci_write_config_dword(isa_dev, 0x64, reg);
196 }
197 }
198
199 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
200 else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
201 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
202 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
203
204 /* Third Channel Test */
205 if (!(PCI_FUNC(dev->devfn) & 1)) {
206 struct pci_dev * findev = NULL;
207 u32 reg4c = 0;
208 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
209 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
210 if (findev) {
211 pci_read_config_dword(findev, 0x4C, &reg4c);
212 reg4c &= ~0x000007FF;
213 reg4c |= 0x00000040;
214 reg4c |= 0x00000020;
215 pci_write_config_dword(findev, 0x4C, reg4c);
216 pci_dev_put(findev);
217 }
218 outb_p(0x06, 0x0c00);
219 dev->irq = inb_p(0x0c01);
220 } else {
221 struct pci_dev * findev = NULL;
222 u8 reg41 = 0;
223
224 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
225 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
226 if (findev) {
227 pci_read_config_byte(findev, 0x41, &reg41);
228 reg41 &= ~0x40;
229 pci_write_config_byte(findev, 0x41, reg41);
230 pci_dev_put(findev);
231 }
232 /*
233 * This is a device pin issue on CSB6.
234 * Since there will be a future raid mode,
235 * early versions of the chipset require the
236 * interrupt pin to be set, and it is a compatibility
237 * mode issue.
238 */
239 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
240 dev->irq = 0;
241 }
242 // pci_read_config_dword(dev, 0x40, &pioreg)
243 // pci_write_config_dword(dev, 0x40, 0x99999999);
244 // pci_read_config_dword(dev, 0x44, &dmareg);
245 // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
246 /* setup the UDMA Control register
247 *
248 * 1. clear bit 6 to enable DMA
249 * 2. enable DMA modes with bits 0-1
250 * 00 : legacy
251 * 01 : udma2
252 * 10 : udma2/udma4
253 * 11 : udma2/udma4/udma5
254 */
255 pci_read_config_byte(dev, 0x5A, &btr);
256 btr &= ~0x40;
257 if (!(PCI_FUNC(dev->devfn) & 1))
258 btr |= 0x2;
259 else
260 btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
261 pci_write_config_byte(dev, 0x5A, btr);
262 }
263 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
264 else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
265 pci_read_config_byte(dev, 0x5A, &btr);
266 btr &= ~0x40;
267 btr |= 0x3;
268 pci_write_config_byte(dev, 0x5A, btr);
269 }
270
271 return dev->irq;
272 }
273
274 static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif)
275 {
276 return ATA_CBL_PATA80;
277 }
278
279 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
280 * of the subsystem device ID indicate presence of an 80-pin cable.
281 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
282 * Bit 15 set = secondary IDE channel has 80-pin cable.
283 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
284 * Bit 14 set = primary IDE channel has 80-pin cable.
285 */
286 static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif)
287 {
288 struct pci_dev *dev = to_pci_dev(hwif->dev);
289
290 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
291 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
292 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
293 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
294 return ((1 << (hwif->channel + 14)) &
295 dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
296 return ATA_CBL_PATA40;
297 }
298
299 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
300 * detect issue by attaching the drives directly to the board.
301 * This check follows the Dell precedent (how scary is that?!)
302 *
303 * WARNING: this only works on Alpine hardware!
304 */
305 static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif)
306 {
307 struct pci_dev *dev = to_pci_dev(hwif->dev);
308
309 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
310 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
311 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
312 return ((1 << (hwif->channel + 14)) &
313 dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
314 return ATA_CBL_PATA40;
315 }
316
317 static u8 __devinit ata66_svwks(ide_hwif_t *hwif)
318 {
319 struct pci_dev *dev = to_pci_dev(hwif->dev);
320
321 /* Server Works */
322 if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
323 return ata66_svwks_svwks (hwif);
324
325 /* Dell PowerEdge */
326 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
327 return ata66_svwks_dell (hwif);
328
329 /* Cobalt Alpine */
330 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
331 return ata66_svwks_cobalt (hwif);
332
333 /* Per Specified Design by OEM, and ASIC Architect */
334 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
335 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
336 return ATA_CBL_PATA80;
337
338 return ATA_CBL_PATA40;
339 }
340
341 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
342 {
343 struct pci_dev *dev = to_pci_dev(hwif->dev);
344
345 hwif->set_pio_mode = &svwks_set_pio_mode;
346 hwif->set_dma_mode = &svwks_set_dma_mode;
347 hwif->udma_filter = &svwks_udma_filter;
348
349 if (dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
350 hwif->cable_detect = ata66_svwks;
351 }
352
353 #define IDE_HFLAGS_SVWKS \
354 (IDE_HFLAG_LEGACY_IRQS | \
355 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
356 IDE_HFLAG_BOOTABLE)
357
358 static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
359 { /* 0 */
360 .name = "SvrWks OSB4",
361 .init_chipset = init_chipset_svwks,
362 .init_hwif = init_hwif_svwks,
363 .host_flags = IDE_HFLAGS_SVWKS,
364 .pio_mask = ATA_PIO4,
365 .mwdma_mask = ATA_MWDMA2,
366 .udma_mask = 0x00, /* UDMA is problematic on OSB4 */
367 },{ /* 1 */
368 .name = "SvrWks CSB5",
369 .init_chipset = init_chipset_svwks,
370 .init_hwif = init_hwif_svwks,
371 .host_flags = IDE_HFLAGS_SVWKS,
372 .pio_mask = ATA_PIO4,
373 .mwdma_mask = ATA_MWDMA2,
374 .udma_mask = ATA_UDMA5,
375 },{ /* 2 */
376 .name = "SvrWks CSB6",
377 .init_chipset = init_chipset_svwks,
378 .init_hwif = init_hwif_svwks,
379 .host_flags = IDE_HFLAGS_SVWKS,
380 .pio_mask = ATA_PIO4,
381 .mwdma_mask = ATA_MWDMA2,
382 .udma_mask = ATA_UDMA5,
383 },{ /* 3 */
384 .name = "SvrWks CSB6",
385 .init_chipset = init_chipset_svwks,
386 .init_hwif = init_hwif_svwks,
387 .host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
388 .pio_mask = ATA_PIO4,
389 .mwdma_mask = ATA_MWDMA2,
390 .udma_mask = ATA_UDMA5,
391 },{ /* 4 */
392 .name = "SvrWks HT1000",
393 .init_chipset = init_chipset_svwks,
394 .init_hwif = init_hwif_svwks,
395 .host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
396 .pio_mask = ATA_PIO4,
397 .mwdma_mask = ATA_MWDMA2,
398 .udma_mask = ATA_UDMA5,
399 }
400 };
401
402 /**
403 * svwks_init_one - called when a OSB/CSB is found
404 * @dev: the svwks device
405 * @id: the matching pci id
406 *
407 * Called when the PCI registration layer (or the IDE initialization)
408 * finds a device matching our IDE device tables.
409 */
410
411 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
412 {
413 struct ide_port_info d;
414 u8 idx = id->driver_data;
415
416 d = serverworks_chipsets[idx];
417
418 if (idx == 1)
419 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
420 else if (idx == 2 || idx == 3) {
421 if ((PCI_FUNC(dev->devfn) & 1) == 0) {
422 if (pci_resource_start(dev, 0) != 0x01f1)
423 d.host_flags &= ~IDE_HFLAG_BOOTABLE;
424 d.host_flags |= IDE_HFLAG_SINGLE;
425 } else
426 d.host_flags &= ~IDE_HFLAG_SINGLE;
427 }
428
429 return ide_setup_pci_device(dev, &d);
430 }
431
432 static const struct pci_device_id svwks_pci_tbl[] = {
433 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 },
434 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 },
435 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 },
436 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 },
437 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
438 { 0, },
439 };
440 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
441
442 static struct pci_driver driver = {
443 .name = "Serverworks_IDE",
444 .id_table = svwks_pci_tbl,
445 .probe = svwks_init_one,
446 };
447
448 static int __init svwks_ide_init(void)
449 {
450 return ide_pci_register_driver(&driver);
451 }
452
453 module_init(svwks_ide_init);
454
455 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
456 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
457 MODULE_LICENSE("GPL");
This page took 0.061554 seconds and 5 git commands to generate.