2 * linux/drivers/ide/pci/siimage.c Version 1.16 Jul 13 2007
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
6 * Copyright (C) 2007 MontaVista Software, Inc.
7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
9 * May be copied or modified under the terms of the GNU General Public License
11 * Documentation for CMD680:
12 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
14 * Documentation for SiI 3112:
15 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
17 * Errata and other documentation only available under NDA.
21 * If you are using Marvell SATA-IDE adapters with Maxtor drives
22 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
24 * If you are using WD drives with SATA bridges you must set the
25 * drive to "Single". "Master" will hang
27 * If you have strange problems with nVidia chipset systems please
28 * see the SI support documentation and update your system BIOS
31 * The Dell DRAC4 has some interesting features including effectively hot
32 * unplugging/replugging the virtual CD interface when the DRAC is reset.
33 * This often causes drivers/ide/siimage to panic but is ok with the rather
34 * smarter code in libata.
41 #include <linux/types.h>
42 #include <linux/module.h>
43 #include <linux/pci.h>
44 #include <linux/delay.h>
45 #include <linux/hdreg.h>
46 #include <linux/ide.h>
47 #include <linux/init.h>
52 * pdev_is_sata - check if device is SATA
53 * @pdev: PCI device to check
55 * Returns true if this is a SATA controller
58 static int pdev_is_sata(struct pci_dev
*pdev
)
62 case PCI_DEVICE_ID_SII_3112
:
63 case PCI_DEVICE_ID_SII_1210SA
:
65 case PCI_DEVICE_ID_SII_680
:
73 * is_sata - check if hwif is SATA
74 * @hwif: interface to check
76 * Returns true if this is a SATA controller
79 static inline int is_sata(ide_hwif_t
*hwif
)
81 return pdev_is_sata(hwif
->pci_dev
);
85 * siimage_selreg - return register base
89 * Turn a config register offset into the right address in either
90 * PCI space or MMIO space to access the control register in question
91 * Thankfully this is a configuration operation so isnt performance
95 static unsigned long siimage_selreg(ide_hwif_t
*hwif
, int r
)
97 unsigned long base
= (unsigned long)hwif
->hwif_data
;
100 base
+= (hwif
->channel
<< 6);
102 base
+= (hwif
->channel
<< 4);
107 * siimage_seldev - return register base
111 * Turn a config register offset into the right address in either
112 * PCI space or MMIO space to access the control register in question
113 * including accounting for the unit shift.
116 static inline unsigned long siimage_seldev(ide_drive_t
*drive
, int r
)
118 ide_hwif_t
*hwif
= HWIF(drive
);
119 unsigned long base
= (unsigned long)hwif
->hwif_data
;
122 base
+= (hwif
->channel
<< 6);
124 base
+= (hwif
->channel
<< 4);
125 base
|= drive
->select
.b
.unit
<< drive
->select
.b
.unit
;
130 * sil_udma_filter - compute UDMA mask
133 * Compute the available UDMA speeds for the device on the interface.
135 * For the CMD680 this depends on the clocking mode (scsc), for the
136 * SI3112 SATA controller life is a bit simpler.
139 static u8
sil_udma_filter(ide_drive_t
*drive
)
141 ide_hwif_t
*hwif
= drive
->hwif
;
142 unsigned long base
= (unsigned long) hwif
->hwif_data
;
143 u8 mask
= 0, scsc
= 0;
146 scsc
= hwif
->INB(base
+ 0x4A);
148 pci_read_config_byte(hwif
->pci_dev
, 0x8A, &scsc
);
151 mask
= strstr(drive
->id
->model
, "Maxtor") ? 0x3f : 0x7f;
155 if ((scsc
& 0x30) == 0x10) /* 133 */
157 else if ((scsc
& 0x30) == 0x20) /* 2xPCI */
159 else if ((scsc
& 0x30) == 0x00) /* 100 */
161 else /* Disabled ? */
168 * sil_tune_pio - tune a drive
169 * @drive: drive to tune
170 * @pio: the desired PIO mode
172 * Load the timing settings for this device mode into the
173 * controller. If we are in PIO mode 3 or 4 turn on IORDY
174 * monitoring (bit 9). The TF timing is bits 31:16
177 static void sil_tune_pio(ide_drive_t
*drive
, u8 pio
)
179 const u16 tf_speed
[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
180 const u16 data_speed
[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
182 ide_hwif_t
*hwif
= HWIF(drive
);
183 ide_drive_t
*pair
= &hwif
->drives
[drive
->dn
^ 1];
186 unsigned long addr
= siimage_seldev(drive
, 0x04);
187 unsigned long tfaddr
= siimage_selreg(hwif
, 0x02);
188 unsigned long base
= (unsigned long)hwif
->hwif_data
;
190 u8 addr_mask
= hwif
->channel
? (hwif
->mmio
? 0xF4 : 0x84)
191 : (hwif
->mmio
? 0xB4 : 0x80);
193 u8 unit
= drive
->select
.b
.unit
;
195 /* trim *taskfile* PIO to the slowest of the master/slave */
197 u8 pair_pio
= ide_get_best_pio_mode(pair
, 255, 4);
199 if (pair_pio
< tf_pio
)
203 /* cheat for now and use the docs */
204 speedp
= data_speed
[pio
];
205 speedt
= tf_speed
[tf_pio
];
208 hwif
->OUTW(speedp
, addr
);
209 hwif
->OUTW(speedt
, tfaddr
);
210 /* Now set up IORDY */
212 hwif
->OUTW(hwif
->INW(tfaddr
-2)|0x200, tfaddr
-2);
214 hwif
->OUTW(hwif
->INW(tfaddr
-2)&~0x200, tfaddr
-2);
216 mode
= hwif
->INB(base
+ addr_mask
);
217 mode
&= ~(unit
? 0x30 : 0x03);
218 mode
|= (unit
? 0x10 : 0x01);
219 hwif
->OUTB(mode
, base
+ addr_mask
);
221 pci_write_config_word(hwif
->pci_dev
, addr
, speedp
);
222 pci_write_config_word(hwif
->pci_dev
, tfaddr
, speedt
);
223 pci_read_config_word(hwif
->pci_dev
, tfaddr
-2, &speedp
);
225 /* Set IORDY for mode 3 or 4 */
228 pci_write_config_word(hwif
->pci_dev
, tfaddr
-2, speedp
);
230 pci_read_config_byte(hwif
->pci_dev
, addr_mask
, &mode
);
231 mode
&= ~(unit
? 0x30 : 0x03);
232 mode
|= (unit
? 0x10 : 0x01);
233 pci_write_config_byte(hwif
->pci_dev
, addr_mask
, mode
);
237 static void sil_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
239 sil_tune_pio(drive
, pio
);
240 (void)ide_config_drive_speed(drive
, XFER_PIO_0
+ pio
);
244 * siimage_tune_chipset - set controller timings
245 * @drive: Drive to set up
246 * @speed: speed we want to achieve
248 * Tune the SII chipset for the desired mode.
251 static int siimage_tune_chipset(ide_drive_t
*drive
, const u8 speed
)
253 u8 ultra6
[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
254 u8 ultra5
[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
255 u16 dma
[] = { 0x2208, 0x10C2, 0x10C1 };
257 ide_hwif_t
*hwif
= HWIF(drive
);
258 u16 ultra
= 0, multi
= 0;
259 u8 mode
= 0, unit
= drive
->select
.b
.unit
;
260 unsigned long base
= (unsigned long)hwif
->hwif_data
;
261 u8 scsc
= 0, addr_mask
= ((hwif
->channel
) ?
262 ((hwif
->mmio
) ? 0xF4 : 0x84) :
263 ((hwif
->mmio
) ? 0xB4 : 0x80));
265 unsigned long ma
= siimage_seldev(drive
, 0x08);
266 unsigned long ua
= siimage_seldev(drive
, 0x0C);
269 scsc
= hwif
->INB(base
+ 0x4A);
270 mode
= hwif
->INB(base
+ addr_mask
);
271 multi
= hwif
->INW(ma
);
272 ultra
= hwif
->INW(ua
);
274 pci_read_config_byte(hwif
->pci_dev
, 0x8A, &scsc
);
275 pci_read_config_byte(hwif
->pci_dev
, addr_mask
, &mode
);
276 pci_read_config_word(hwif
->pci_dev
, ma
, &multi
);
277 pci_read_config_word(hwif
->pci_dev
, ua
, &ultra
);
280 mode
&= ~((unit
) ? 0x30 : 0x03);
282 scsc
= ((scsc
& 0x30) == 0x00) ? 0 : 1;
284 scsc
= is_sata(hwif
) ? 1 : scsc
;
292 sil_tune_pio(drive
, speed
- XFER_PIO_0
);
293 return ide_config_drive_speed(drive
, speed
);
297 multi
= dma
[speed
- XFER_MW_DMA_0
];
298 mode
|= ((unit
) ? 0x20 : 0x02);
308 ultra
|= ((scsc
) ? (ultra6
[speed
- XFER_UDMA_0
]) :
309 (ultra5
[speed
- XFER_UDMA_0
]));
310 mode
|= ((unit
) ? 0x30 : 0x03);
317 hwif
->OUTB(mode
, base
+ addr_mask
);
318 hwif
->OUTW(multi
, ma
);
319 hwif
->OUTW(ultra
, ua
);
321 pci_write_config_byte(hwif
->pci_dev
, addr_mask
, mode
);
322 pci_write_config_word(hwif
->pci_dev
, ma
, multi
);
323 pci_write_config_word(hwif
->pci_dev
, ua
, ultra
);
325 return (ide_config_drive_speed(drive
, speed
));
329 * siimage_configure_drive_for_dma - set up for DMA transfers
330 * @drive: drive we are going to set up
332 * Set up the drive for DMA, tune the controller and drive as
333 * required. If the drive isn't suitable for DMA or we hit
334 * other problems then we will drop down to PIO and set up
338 static int siimage_config_drive_for_dma (ide_drive_t
*drive
)
340 if (ide_tune_dma(drive
))
343 if (ide_use_fast_pio(drive
))
344 ide_set_max_pio(drive
);
349 /* returns 1 if dma irq issued, 0 otherwise */
350 static int siimage_io_ide_dma_test_irq (ide_drive_t
*drive
)
352 ide_hwif_t
*hwif
= HWIF(drive
);
354 unsigned long addr
= siimage_selreg(hwif
, 1);
356 /* return 1 if INTR asserted */
357 if ((hwif
->INB(hwif
->dma_status
) & 4) == 4)
360 /* return 1 if Device INTR asserted */
361 pci_read_config_byte(hwif
->pci_dev
, addr
, &dma_altstat
);
363 return 0; //return 1;
368 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
369 * @drive: drive we are testing
371 * Check if we caused an IDE DMA interrupt. We may also have caused
372 * SATA status interrupts, if so we clean them up and continue.
375 static int siimage_mmio_ide_dma_test_irq (ide_drive_t
*drive
)
377 ide_hwif_t
*hwif
= HWIF(drive
);
378 unsigned long base
= (unsigned long)hwif
->hwif_data
;
379 unsigned long addr
= siimage_selreg(hwif
, 0x1);
381 if (SATA_ERROR_REG
) {
382 u32 ext_stat
= readl((void __iomem
*)(base
+ 0x10));
384 if (ext_stat
& ((hwif
->channel
) ? 0x40 : 0x10)) {
385 u32 sata_error
= readl((void __iomem
*)SATA_ERROR_REG
);
386 writel(sata_error
, (void __iomem
*)SATA_ERROR_REG
);
387 watchdog
= (sata_error
& 0x00680000) ? 1 : 0;
388 printk(KERN_WARNING
"%s: sata_error = 0x%08x, "
389 "watchdog = %d, %s\n",
390 drive
->name
, sata_error
, watchdog
,
394 watchdog
= (ext_stat
& 0x8000) ? 1 : 0;
398 if (!(ext_stat
& 0x0404) && !watchdog
)
402 /* return 1 if INTR asserted */
403 if ((readb((void __iomem
*)hwif
->dma_status
) & 0x04) == 0x04)
406 /* return 1 if Device INTR asserted */
407 if ((readb((void __iomem
*)addr
) & 8) == 8)
408 return 0; //return 1;
414 * siimage_busproc - bus isolation ioctl
415 * @drive: drive to isolate/restore
416 * @state: bus state to set
418 * Used by the SII3112 to handle bus isolation. As this is a
419 * SATA controller the work required is quite limited, we
420 * just have to clean up the statistics
423 static int siimage_busproc (ide_drive_t
* drive
, int state
)
425 ide_hwif_t
*hwif
= HWIF(drive
);
427 unsigned long addr
= siimage_selreg(hwif
, 0);
430 stat_config
= readl((void __iomem
*)addr
);
432 pci_read_config_dword(hwif
->pci_dev
, addr
, &stat_config
);
436 hwif
->drives
[0].failures
= 0;
437 hwif
->drives
[1].failures
= 0;
440 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
441 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
443 case BUSSTATE_TRISTATE
:
444 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
445 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
450 hwif
->bus_state
= state
;
455 * siimage_reset_poll - wait for sata reset
456 * @drive: drive we are resetting
458 * Poll the SATA phy and see whether it has come back from the dead
462 static int siimage_reset_poll (ide_drive_t
*drive
)
464 if (SATA_STATUS_REG
) {
465 ide_hwif_t
*hwif
= HWIF(drive
);
467 /* SATA_STATUS_REG is valid only when in MMIO mode */
468 if ((readl((void __iomem
*)SATA_STATUS_REG
) & 0x03) != 0x03) {
469 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
470 hwif
->name
, readl((void __iomem
*)SATA_STATUS_REG
));
471 HWGROUP(drive
)->polling
= 0;
481 * siimage_pre_reset - reset hook
482 * @drive: IDE device being reset
484 * For the SATA devices we need to handle recalibration/geometry
488 static void siimage_pre_reset (ide_drive_t
*drive
)
490 if (drive
->media
!= ide_disk
)
493 if (is_sata(HWIF(drive
)))
495 drive
->special
.b
.set_geometry
= 0;
496 drive
->special
.b
.recalibrate
= 0;
501 * siimage_reset - reset a device on an siimage controller
502 * @drive: drive to reset
504 * Perform a controller level reset fo the device. For
505 * SATA we must also check the PHY.
508 static void siimage_reset (ide_drive_t
*drive
)
510 ide_hwif_t
*hwif
= HWIF(drive
);
512 unsigned long addr
= siimage_selreg(hwif
, 0);
515 reset
= hwif
->INB(addr
);
516 hwif
->OUTB((reset
|0x03), addr
);
519 hwif
->OUTB(reset
, addr
);
520 (void) hwif
->INB(addr
);
522 pci_read_config_byte(hwif
->pci_dev
, addr
, &reset
);
523 pci_write_config_byte(hwif
->pci_dev
, addr
, reset
|0x03);
525 pci_write_config_byte(hwif
->pci_dev
, addr
, reset
);
526 pci_read_config_byte(hwif
->pci_dev
, addr
, &reset
);
529 if (SATA_STATUS_REG
) {
530 /* SATA_STATUS_REG is valid only when in MMIO mode */
531 u32 sata_stat
= readl((void __iomem
*)SATA_STATUS_REG
);
532 printk(KERN_WARNING
"%s: reset phy, status=0x%08x, %s\n",
533 hwif
->name
, sata_stat
, __FUNCTION__
);
535 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
536 hwif
->name
, sata_stat
);
544 * proc_reports_siimage - add siimage controller to proc
546 * @clocking: SCSC value
547 * @name: controller name
549 * Report the clocking mode of the controller and add it to
550 * the /proc interface layer
553 static void proc_reports_siimage (struct pci_dev
*dev
, u8 clocking
, const char *name
)
555 if (!pdev_is_sata(dev
)) {
556 printk(KERN_INFO
"%s: BASE CLOCK ", name
);
559 case 0x03: printk("DISABLED!\n"); break;
560 case 0x02: printk("== 2X PCI\n"); break;
561 case 0x01: printk("== 133\n"); break;
562 case 0x00: printk("== 100\n"); break;
568 * setup_mmio_siimage - switch an SI controller into MMIO
569 * @dev: PCI device we are configuring
572 * Attempt to put the device into mmio mode. There are some slight
573 * complications here with certain systems where the mmio bar isnt
574 * mapped so we have to be sure we can fall back to I/O.
577 static unsigned int setup_mmio_siimage (struct pci_dev
*dev
, const char *name
)
579 unsigned long bar5
= pci_resource_start(dev
, 5);
580 unsigned long barsize
= pci_resource_len(dev
, 5);
582 void __iomem
*ioaddr
;
586 * Drop back to PIO if we can't map the mmio. Some
587 * systems seem to get terminally confused in the PCI
591 if(!request_mem_region(bar5
, barsize
, name
))
593 printk(KERN_WARNING
"siimage: IDE controller MMIO ports not available.\n");
597 ioaddr
= ioremap(bar5
, barsize
);
601 release_mem_region(bar5
, barsize
);
606 pci_set_drvdata(dev
, (void *) ioaddr
);
608 if (pdev_is_sata(dev
)) {
609 /* make sure IDE0/1 interrupts are not masked */
610 irq_mask
= (1 << 22) | (1 << 23);
611 tmp
= readl(ioaddr
+ 0x48);
612 if (tmp
& irq_mask
) {
614 writel(tmp
, ioaddr
+ 0x48);
615 readl(ioaddr
+ 0x48); /* flush */
617 writel(0, ioaddr
+ 0x148);
618 writel(0, ioaddr
+ 0x1C8);
621 writeb(0, ioaddr
+ 0xB4);
622 writeb(0, ioaddr
+ 0xF4);
623 tmpbyte
= readb(ioaddr
+ 0x4A);
625 switch(tmpbyte
& 0x30) {
627 /* In 100 MHz clocking, try and switch to 133 */
628 writeb(tmpbyte
|0x10, ioaddr
+ 0x4A);
631 /* On 133Mhz clocking */
634 /* On PCIx2 clocking */
637 /* Clocking is disabled */
638 /* 133 clock attempt to force it on */
639 writeb(tmpbyte
& ~0x20, ioaddr
+ 0x4A);
643 writeb( 0x72, ioaddr
+ 0xA1);
644 writew( 0x328A, ioaddr
+ 0xA2);
645 writel(0x62DD62DD, ioaddr
+ 0xA4);
646 writel(0x43924392, ioaddr
+ 0xA8);
647 writel(0x40094009, ioaddr
+ 0xAC);
648 writeb( 0x72, ioaddr
+ 0xE1);
649 writew( 0x328A, ioaddr
+ 0xE2);
650 writel(0x62DD62DD, ioaddr
+ 0xE4);
651 writel(0x43924392, ioaddr
+ 0xE8);
652 writel(0x40094009, ioaddr
+ 0xEC);
654 if (pdev_is_sata(dev
)) {
655 writel(0xFFFF0000, ioaddr
+ 0x108);
656 writel(0xFFFF0000, ioaddr
+ 0x188);
657 writel(0x00680000, ioaddr
+ 0x148);
658 writel(0x00680000, ioaddr
+ 0x1C8);
661 tmpbyte
= readb(ioaddr
+ 0x4A);
663 proc_reports_siimage(dev
, (tmpbyte
>>4), name
);
668 * init_chipset_siimage - set up an SI device
672 * Perform the initial PCI set up for this device. Attempt to switch
673 * to 133MHz clocking if the system isn't already set up to do it.
676 static unsigned int __devinit
init_chipset_siimage(struct pci_dev
*dev
, const char *name
)
682 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
684 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, (class_rev
) ? 1 : 255);
686 pci_read_config_byte(dev
, 0x8A, &BA5_EN
);
687 if ((BA5_EN
& 0x01) || (pci_resource_start(dev
, 5))) {
688 if (setup_mmio_siimage(dev
, name
)) {
693 pci_write_config_byte(dev
, 0x80, 0x00);
694 pci_write_config_byte(dev
, 0x84, 0x00);
695 pci_read_config_byte(dev
, 0x8A, &tmpbyte
);
696 switch(tmpbyte
& 0x30) {
698 /* 133 clock attempt to force it on */
699 pci_write_config_byte(dev
, 0x8A, tmpbyte
|0x10);
701 /* if clocking is disabled */
702 /* 133 clock attempt to force it on */
703 pci_write_config_byte(dev
, 0x8A, tmpbyte
& ~0x20);
708 /* BIOS set PCI x2 clocking */
712 pci_read_config_byte(dev
, 0x8A, &tmpbyte
);
714 pci_write_config_byte(dev
, 0xA1, 0x72);
715 pci_write_config_word(dev
, 0xA2, 0x328A);
716 pci_write_config_dword(dev
, 0xA4, 0x62DD62DD);
717 pci_write_config_dword(dev
, 0xA8, 0x43924392);
718 pci_write_config_dword(dev
, 0xAC, 0x40094009);
719 pci_write_config_byte(dev
, 0xB1, 0x72);
720 pci_write_config_word(dev
, 0xB2, 0x328A);
721 pci_write_config_dword(dev
, 0xB4, 0x62DD62DD);
722 pci_write_config_dword(dev
, 0xB8, 0x43924392);
723 pci_write_config_dword(dev
, 0xBC, 0x40094009);
725 proc_reports_siimage(dev
, (tmpbyte
>>4), name
);
730 * init_mmio_iops_siimage - set up the iops for MMIO
731 * @hwif: interface to set up
733 * The basic setup here is fairly simple, we can use standard MMIO
734 * operations. However we do have to set the taskfile register offsets
735 * by hand as there isnt a standard defined layout for them this
738 * The hardware supports buffered taskfiles and also some rather nice
739 * extended PRD tables. For better SI3112 support use the libata driver
742 static void __devinit
init_mmio_iops_siimage(ide_hwif_t
*hwif
)
744 struct pci_dev
*dev
= hwif
->pci_dev
;
745 void *addr
= pci_get_drvdata(dev
);
746 u8 ch
= hwif
->channel
;
751 * Fill in the basic HWIF bits
754 default_hwif_mmiops(hwif
);
755 hwif
->hwif_data
= addr
;
758 * Now set up the hw. We have to do this ourselves as
759 * the MMIO layout isnt the same as the standard port
763 memset(&hw
, 0, sizeof(hw_regs_t
));
765 base
= (unsigned long)addr
;
772 * The buffered task file doesn't have status/control
773 * so we can't currently use it sanely since we want to
776 hw
.io_ports
[IDE_DATA_OFFSET
] = base
;
777 hw
.io_ports
[IDE_ERROR_OFFSET
] = base
+ 1;
778 hw
.io_ports
[IDE_NSECTOR_OFFSET
] = base
+ 2;
779 hw
.io_ports
[IDE_SECTOR_OFFSET
] = base
+ 3;
780 hw
.io_ports
[IDE_LCYL_OFFSET
] = base
+ 4;
781 hw
.io_ports
[IDE_HCYL_OFFSET
] = base
+ 5;
782 hw
.io_ports
[IDE_SELECT_OFFSET
] = base
+ 6;
783 hw
.io_ports
[IDE_STATUS_OFFSET
] = base
+ 7;
784 hw
.io_ports
[IDE_CONTROL_OFFSET
] = base
+ 10;
786 hw
.io_ports
[IDE_IRQ_OFFSET
] = 0;
788 if (pdev_is_sata(dev
)) {
789 base
= (unsigned long)addr
;
792 hwif
->sata_scr
[SATA_STATUS_OFFSET
] = base
+ 0x104;
793 hwif
->sata_scr
[SATA_ERROR_OFFSET
] = base
+ 0x108;
794 hwif
->sata_scr
[SATA_CONTROL_OFFSET
] = base
+ 0x100;
795 hwif
->sata_misc
[SATA_MISC_OFFSET
] = base
+ 0x140;
796 hwif
->sata_misc
[SATA_PHY_OFFSET
] = base
+ 0x144;
797 hwif
->sata_misc
[SATA_IEN_OFFSET
] = base
+ 0x148;
800 hw
.irq
= hwif
->pci_dev
->irq
;
802 memcpy(&hwif
->hw
, &hw
, sizeof(hw
));
803 memcpy(hwif
->io_ports
, hwif
->hw
.io_ports
, sizeof(hwif
->hw
.io_ports
));
807 base
= (unsigned long) addr
;
809 hwif
->dma_base
= base
+ (ch
? 0x08 : 0x00);
814 static int is_dev_seagate_sata(ide_drive_t
*drive
)
816 const char *s
= &drive
->id
->model
[0];
822 len
= strnlen(s
, sizeof(drive
->id
->model
));
824 if ((len
> 4) && (!memcmp(s
, "ST", 2))) {
825 if ((!memcmp(s
+ len
- 2, "AS", 2)) ||
826 (!memcmp(s
+ len
- 3, "ASL", 3))) {
827 printk(KERN_INFO
"%s: applying pessimistic Seagate "
828 "errata fix\n", drive
->name
);
836 * siimage_fixup - post probe fixups
837 * @hwif: interface to fix up
839 * Called after drive probe we use this to decide whether the
840 * Seagate fixup must be applied. This used to be in init_iops but
841 * that can occur before we know what drives are present.
844 static void __devinit
siimage_fixup(ide_hwif_t
*hwif
)
846 /* Try and raise the rqsize */
847 if (!is_sata(hwif
) || !is_dev_seagate_sata(&hwif
->drives
[0]))
852 * init_iops_siimage - set up iops
853 * @hwif: interface to set up
855 * Do the basic setup for the SIIMAGE hardware interface
856 * and then do the MMIO setup if we can. This is the first
857 * look in we get for setting up the hwif so that we
858 * can get the iops right before using them.
861 static void __devinit
init_iops_siimage(ide_hwif_t
*hwif
)
863 struct pci_dev
*dev
= hwif
->pci_dev
;
866 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
869 hwif
->hwif_data
= NULL
;
871 /* Pessimal until we finish probing */
874 if (pci_get_drvdata(dev
) == NULL
)
876 init_mmio_iops_siimage(hwif
);
880 * ata66_siimage - check for 80 pin cable
881 * @hwif: interface to check
883 * Check for the presence of an ATA66 capable cable on the
887 static u8 __devinit
ata66_siimage(ide_hwif_t
*hwif
)
889 unsigned long addr
= siimage_selreg(hwif
, 0);
892 if (pci_get_drvdata(hwif
->pci_dev
) == NULL
)
893 pci_read_config_byte(hwif
->pci_dev
, addr
, &ata66
);
895 ata66
= hwif
->INB(addr
);
897 return (ata66
& 0x01) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
901 * init_hwif_siimage - set up hwif structs
902 * @hwif: interface to set up
904 * We do the basic set up of the interface structure. The SIIMAGE
905 * requires several custom handlers so we override the default
906 * ide DMA handlers appropriately
909 static void __devinit
init_hwif_siimage(ide_hwif_t
*hwif
)
913 hwif
->resetproc
= &siimage_reset
;
914 hwif
->speedproc
= &siimage_tune_chipset
;
915 hwif
->set_pio_mode
= &sil_set_pio_mode
;
916 hwif
->reset_poll
= &siimage_reset_poll
;
917 hwif
->pre_reset
= &siimage_pre_reset
;
918 hwif
->udma_filter
= &sil_udma_filter
;
921 static int first
= 1;
923 hwif
->busproc
= &siimage_busproc
;
926 printk(KERN_INFO
"siimage: For full SATA support you should use the libata sata_sil module.\n");
931 hwif
->drives
[0].autotune
= hwif
->drives
[1].autotune
= 1;
933 if (hwif
->dma_base
== 0)
936 hwif
->ultra_mask
= 0x7f;
937 hwif
->mwdma_mask
= 0x07;
942 hwif
->ide_dma_check
= &siimage_config_drive_for_dma
;
944 if (hwif
->cbl
!= ATA_CBL_PATA40_SHORT
)
945 hwif
->cbl
= ata66_siimage(hwif
);
948 hwif
->ide_dma_test_irq
= &siimage_mmio_ide_dma_test_irq
;
950 hwif
->ide_dma_test_irq
= & siimage_io_ide_dma_test_irq
;
954 * The BIOS often doesn't set up DMA on this controller
955 * so we always do it.
959 hwif
->drives
[0].autodma
= hwif
->autodma
;
960 hwif
->drives
[1].autodma
= hwif
->autodma
;
963 #define DECLARE_SII_DEV(name_str) \
966 .init_chipset = init_chipset_siimage, \
967 .init_iops = init_iops_siimage, \
968 .init_hwif = init_hwif_siimage, \
969 .fixup = siimage_fixup, \
970 .autodma = AUTODMA, \
971 .bootable = ON_BOARD, \
972 .pio_mask = ATA_PIO4, \
975 static ide_pci_device_t siimage_chipsets
[] __devinitdata
= {
976 /* 0 */ DECLARE_SII_DEV("SiI680"),
977 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
978 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
982 * siimage_init_one - pci layer discovery entry
984 * @id: ident table entry
986 * Called by the PCI code when it finds an SI680 or SI3112 controller.
987 * We then use the IDE PCI generic helper to do most of the work.
990 static int __devinit
siimage_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
992 return ide_setup_pci_device(dev
, &siimage_chipsets
[id
->driver_data
]);
995 static struct pci_device_id siimage_pci_tbl
[] = {
996 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_SII_680
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
997 #ifdef CONFIG_BLK_DEV_IDE_SATA
998 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_SII_3112
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1},
999 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_SII_1210SA
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2},
1003 MODULE_DEVICE_TABLE(pci
, siimage_pci_tbl
);
1005 static struct pci_driver driver
= {
1007 .id_table
= siimage_pci_tbl
,
1008 .probe
= siimage_init_one
,
1011 static int __init
siimage_ide_init(void)
1013 return ide_pci_register_driver(&driver
);
1016 module_init(siimage_ide_init
);
1018 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1019 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1020 MODULE_LICENSE("GPL");