2 * linux/drivers/ide/pci/siimage.c Version 1.16 Jul 13 2007
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
6 * Copyright (C) 2007 MontaVista Software, Inc.
7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
9 * May be copied or modified under the terms of the GNU General Public License
11 * Documentation for CMD680:
12 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
14 * Documentation for SiI 3112:
15 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
17 * Errata and other documentation only available under NDA.
21 * If you are using Marvell SATA-IDE adapters with Maxtor drives
22 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
24 * If you are using WD drives with SATA bridges you must set the
25 * drive to "Single". "Master" will hang
27 * If you have strange problems with nVidia chipset systems please
28 * see the SI support documentation and update your system BIOS
31 * The Dell DRAC4 has some interesting features including effectively hot
32 * unplugging/replugging the virtual CD interface when the DRAC is reset.
33 * This often causes drivers/ide/siimage to panic but is ok with the rather
34 * smarter code in libata.
41 #include <linux/types.h>
42 #include <linux/module.h>
43 #include <linux/pci.h>
44 #include <linux/delay.h>
45 #include <linux/hdreg.h>
46 #include <linux/ide.h>
47 #include <linux/init.h>
52 * pdev_is_sata - check if device is SATA
53 * @pdev: PCI device to check
55 * Returns true if this is a SATA controller
58 static int pdev_is_sata(struct pci_dev
*pdev
)
62 case PCI_DEVICE_ID_SII_3112
:
63 case PCI_DEVICE_ID_SII_1210SA
:
65 case PCI_DEVICE_ID_SII_680
:
73 * is_sata - check if hwif is SATA
74 * @hwif: interface to check
76 * Returns true if this is a SATA controller
79 static inline int is_sata(ide_hwif_t
*hwif
)
81 return pdev_is_sata(hwif
->pci_dev
);
85 * siimage_selreg - return register base
89 * Turn a config register offset into the right address in either
90 * PCI space or MMIO space to access the control register in question
91 * Thankfully this is a configuration operation so isnt performance
95 static unsigned long siimage_selreg(ide_hwif_t
*hwif
, int r
)
97 unsigned long base
= (unsigned long)hwif
->hwif_data
;
100 base
+= (hwif
->channel
<< 6);
102 base
+= (hwif
->channel
<< 4);
107 * siimage_seldev - return register base
111 * Turn a config register offset into the right address in either
112 * PCI space or MMIO space to access the control register in question
113 * including accounting for the unit shift.
116 static inline unsigned long siimage_seldev(ide_drive_t
*drive
, int r
)
118 ide_hwif_t
*hwif
= HWIF(drive
);
119 unsigned long base
= (unsigned long)hwif
->hwif_data
;
122 base
+= (hwif
->channel
<< 6);
124 base
+= (hwif
->channel
<< 4);
125 base
|= drive
->select
.b
.unit
<< drive
->select
.b
.unit
;
130 * sil_udma_filter - compute UDMA mask
133 * Compute the available UDMA speeds for the device on the interface.
135 * For the CMD680 this depends on the clocking mode (scsc), for the
136 * SI3112 SATA controller life is a bit simpler.
139 static u8
sil_udma_filter(ide_drive_t
*drive
)
141 ide_hwif_t
*hwif
= drive
->hwif
;
142 unsigned long base
= (unsigned long) hwif
->hwif_data
;
143 u8 mask
= 0, scsc
= 0;
146 scsc
= hwif
->INB(base
+ 0x4A);
148 pci_read_config_byte(hwif
->pci_dev
, 0x8A, &scsc
);
151 mask
= strstr(drive
->id
->model
, "Maxtor") ? 0x3f : 0x7f;
155 if ((scsc
& 0x30) == 0x10) /* 133 */
157 else if ((scsc
& 0x30) == 0x20) /* 2xPCI */
159 else if ((scsc
& 0x30) == 0x00) /* 100 */
161 else /* Disabled ? */
168 * sil_set_pio_mode - set host controller for PIO mode
170 * @pio: PIO mode number
172 * Load the timing settings for this device mode into the
173 * controller. If we are in PIO mode 3 or 4 turn on IORDY
174 * monitoring (bit 9). The TF timing is bits 31:16
177 static void sil_set_pio_mode(ide_drive_t
*drive
, u8 pio
)
179 const u16 tf_speed
[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
180 const u16 data_speed
[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
182 ide_hwif_t
*hwif
= HWIF(drive
);
183 ide_drive_t
*pair
= &hwif
->drives
[drive
->dn
^ 1];
186 unsigned long addr
= siimage_seldev(drive
, 0x04);
187 unsigned long tfaddr
= siimage_selreg(hwif
, 0x02);
188 unsigned long base
= (unsigned long)hwif
->hwif_data
;
190 u8 addr_mask
= hwif
->channel
? (hwif
->mmio
? 0xF4 : 0x84)
191 : (hwif
->mmio
? 0xB4 : 0x80);
193 u8 unit
= drive
->select
.b
.unit
;
195 /* trim *taskfile* PIO to the slowest of the master/slave */
197 u8 pair_pio
= ide_get_best_pio_mode(pair
, 255, 4);
199 if (pair_pio
< tf_pio
)
203 /* cheat for now and use the docs */
204 speedp
= data_speed
[pio
];
205 speedt
= tf_speed
[tf_pio
];
208 hwif
->OUTW(speedp
, addr
);
209 hwif
->OUTW(speedt
, tfaddr
);
210 /* Now set up IORDY */
212 hwif
->OUTW(hwif
->INW(tfaddr
-2)|0x200, tfaddr
-2);
214 hwif
->OUTW(hwif
->INW(tfaddr
-2)&~0x200, tfaddr
-2);
216 mode
= hwif
->INB(base
+ addr_mask
);
217 mode
&= ~(unit
? 0x30 : 0x03);
218 mode
|= (unit
? 0x10 : 0x01);
219 hwif
->OUTB(mode
, base
+ addr_mask
);
221 pci_write_config_word(hwif
->pci_dev
, addr
, speedp
);
222 pci_write_config_word(hwif
->pci_dev
, tfaddr
, speedt
);
223 pci_read_config_word(hwif
->pci_dev
, tfaddr
-2, &speedp
);
225 /* Set IORDY for mode 3 or 4 */
228 pci_write_config_word(hwif
->pci_dev
, tfaddr
-2, speedp
);
230 pci_read_config_byte(hwif
->pci_dev
, addr_mask
, &mode
);
231 mode
&= ~(unit
? 0x30 : 0x03);
232 mode
|= (unit
? 0x10 : 0x01);
233 pci_write_config_byte(hwif
->pci_dev
, addr_mask
, mode
);
238 * sil_set_dma_mode - set host controller for DMA mode
242 * Tune the SiI chipset for the desired DMA mode.
245 static void sil_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
247 u8 ultra6
[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
248 u8 ultra5
[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
249 u16 dma
[] = { 0x2208, 0x10C2, 0x10C1 };
251 ide_hwif_t
*hwif
= HWIF(drive
);
252 u16 ultra
= 0, multi
= 0;
253 u8 mode
= 0, unit
= drive
->select
.b
.unit
;
254 unsigned long base
= (unsigned long)hwif
->hwif_data
;
255 u8 scsc
= 0, addr_mask
= ((hwif
->channel
) ?
256 ((hwif
->mmio
) ? 0xF4 : 0x84) :
257 ((hwif
->mmio
) ? 0xB4 : 0x80));
259 unsigned long ma
= siimage_seldev(drive
, 0x08);
260 unsigned long ua
= siimage_seldev(drive
, 0x0C);
263 scsc
= hwif
->INB(base
+ 0x4A);
264 mode
= hwif
->INB(base
+ addr_mask
);
265 multi
= hwif
->INW(ma
);
266 ultra
= hwif
->INW(ua
);
268 pci_read_config_byte(hwif
->pci_dev
, 0x8A, &scsc
);
269 pci_read_config_byte(hwif
->pci_dev
, addr_mask
, &mode
);
270 pci_read_config_word(hwif
->pci_dev
, ma
, &multi
);
271 pci_read_config_word(hwif
->pci_dev
, ua
, &ultra
);
274 mode
&= ~((unit
) ? 0x30 : 0x03);
276 scsc
= ((scsc
& 0x30) == 0x00) ? 0 : 1;
278 scsc
= is_sata(hwif
) ? 1 : scsc
;
284 multi
= dma
[speed
- XFER_MW_DMA_0
];
285 mode
|= ((unit
) ? 0x20 : 0x02);
295 ultra
|= ((scsc
) ? (ultra6
[speed
- XFER_UDMA_0
]) :
296 (ultra5
[speed
- XFER_UDMA_0
]));
297 mode
|= ((unit
) ? 0x30 : 0x03);
304 hwif
->OUTB(mode
, base
+ addr_mask
);
305 hwif
->OUTW(multi
, ma
);
306 hwif
->OUTW(ultra
, ua
);
308 pci_write_config_byte(hwif
->pci_dev
, addr_mask
, mode
);
309 pci_write_config_word(hwif
->pci_dev
, ma
, multi
);
310 pci_write_config_word(hwif
->pci_dev
, ua
, ultra
);
315 * siimage_configure_drive_for_dma - set up for DMA transfers
316 * @drive: drive we are going to set up
318 * Set up the drive for DMA, tune the controller and drive as
319 * required. If the drive isn't suitable for DMA or we hit
320 * other problems then we will drop down to PIO and set up
324 static int siimage_config_drive_for_dma (ide_drive_t
*drive
)
326 if (ide_tune_dma(drive
))
329 if (ide_use_fast_pio(drive
))
330 ide_set_max_pio(drive
);
335 /* returns 1 if dma irq issued, 0 otherwise */
336 static int siimage_io_ide_dma_test_irq (ide_drive_t
*drive
)
338 ide_hwif_t
*hwif
= HWIF(drive
);
340 unsigned long addr
= siimage_selreg(hwif
, 1);
342 /* return 1 if INTR asserted */
343 if ((hwif
->INB(hwif
->dma_status
) & 4) == 4)
346 /* return 1 if Device INTR asserted */
347 pci_read_config_byte(hwif
->pci_dev
, addr
, &dma_altstat
);
349 return 0; //return 1;
354 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
355 * @drive: drive we are testing
357 * Check if we caused an IDE DMA interrupt. We may also have caused
358 * SATA status interrupts, if so we clean them up and continue.
361 static int siimage_mmio_ide_dma_test_irq (ide_drive_t
*drive
)
363 ide_hwif_t
*hwif
= HWIF(drive
);
364 unsigned long base
= (unsigned long)hwif
->hwif_data
;
365 unsigned long addr
= siimage_selreg(hwif
, 0x1);
367 if (SATA_ERROR_REG
) {
368 u32 ext_stat
= readl((void __iomem
*)(base
+ 0x10));
370 if (ext_stat
& ((hwif
->channel
) ? 0x40 : 0x10)) {
371 u32 sata_error
= readl((void __iomem
*)SATA_ERROR_REG
);
372 writel(sata_error
, (void __iomem
*)SATA_ERROR_REG
);
373 watchdog
= (sata_error
& 0x00680000) ? 1 : 0;
374 printk(KERN_WARNING
"%s: sata_error = 0x%08x, "
375 "watchdog = %d, %s\n",
376 drive
->name
, sata_error
, watchdog
,
380 watchdog
= (ext_stat
& 0x8000) ? 1 : 0;
384 if (!(ext_stat
& 0x0404) && !watchdog
)
388 /* return 1 if INTR asserted */
389 if ((readb((void __iomem
*)hwif
->dma_status
) & 0x04) == 0x04)
392 /* return 1 if Device INTR asserted */
393 if ((readb((void __iomem
*)addr
) & 8) == 8)
394 return 0; //return 1;
400 * siimage_busproc - bus isolation ioctl
401 * @drive: drive to isolate/restore
402 * @state: bus state to set
404 * Used by the SII3112 to handle bus isolation. As this is a
405 * SATA controller the work required is quite limited, we
406 * just have to clean up the statistics
409 static int siimage_busproc (ide_drive_t
* drive
, int state
)
411 ide_hwif_t
*hwif
= HWIF(drive
);
413 unsigned long addr
= siimage_selreg(hwif
, 0);
416 stat_config
= readl((void __iomem
*)addr
);
418 pci_read_config_dword(hwif
->pci_dev
, addr
, &stat_config
);
422 hwif
->drives
[0].failures
= 0;
423 hwif
->drives
[1].failures
= 0;
426 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
427 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
429 case BUSSTATE_TRISTATE
:
430 hwif
->drives
[0].failures
= hwif
->drives
[0].max_failures
+ 1;
431 hwif
->drives
[1].failures
= hwif
->drives
[1].max_failures
+ 1;
436 hwif
->bus_state
= state
;
441 * siimage_reset_poll - wait for sata reset
442 * @drive: drive we are resetting
444 * Poll the SATA phy and see whether it has come back from the dead
448 static int siimage_reset_poll (ide_drive_t
*drive
)
450 if (SATA_STATUS_REG
) {
451 ide_hwif_t
*hwif
= HWIF(drive
);
453 /* SATA_STATUS_REG is valid only when in MMIO mode */
454 if ((readl((void __iomem
*)SATA_STATUS_REG
) & 0x03) != 0x03) {
455 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
456 hwif
->name
, readl((void __iomem
*)SATA_STATUS_REG
));
457 HWGROUP(drive
)->polling
= 0;
467 * siimage_pre_reset - reset hook
468 * @drive: IDE device being reset
470 * For the SATA devices we need to handle recalibration/geometry
474 static void siimage_pre_reset (ide_drive_t
*drive
)
476 if (drive
->media
!= ide_disk
)
479 if (is_sata(HWIF(drive
)))
481 drive
->special
.b
.set_geometry
= 0;
482 drive
->special
.b
.recalibrate
= 0;
487 * siimage_reset - reset a device on an siimage controller
488 * @drive: drive to reset
490 * Perform a controller level reset fo the device. For
491 * SATA we must also check the PHY.
494 static void siimage_reset (ide_drive_t
*drive
)
496 ide_hwif_t
*hwif
= HWIF(drive
);
498 unsigned long addr
= siimage_selreg(hwif
, 0);
501 reset
= hwif
->INB(addr
);
502 hwif
->OUTB((reset
|0x03), addr
);
505 hwif
->OUTB(reset
, addr
);
506 (void) hwif
->INB(addr
);
508 pci_read_config_byte(hwif
->pci_dev
, addr
, &reset
);
509 pci_write_config_byte(hwif
->pci_dev
, addr
, reset
|0x03);
511 pci_write_config_byte(hwif
->pci_dev
, addr
, reset
);
512 pci_read_config_byte(hwif
->pci_dev
, addr
, &reset
);
515 if (SATA_STATUS_REG
) {
516 /* SATA_STATUS_REG is valid only when in MMIO mode */
517 u32 sata_stat
= readl((void __iomem
*)SATA_STATUS_REG
);
518 printk(KERN_WARNING
"%s: reset phy, status=0x%08x, %s\n",
519 hwif
->name
, sata_stat
, __FUNCTION__
);
521 printk(KERN_WARNING
"%s: reset phy dead, status=0x%08x\n",
522 hwif
->name
, sata_stat
);
530 * proc_reports_siimage - add siimage controller to proc
532 * @clocking: SCSC value
533 * @name: controller name
535 * Report the clocking mode of the controller and add it to
536 * the /proc interface layer
539 static void proc_reports_siimage (struct pci_dev
*dev
, u8 clocking
, const char *name
)
541 if (!pdev_is_sata(dev
)) {
542 printk(KERN_INFO
"%s: BASE CLOCK ", name
);
545 case 0x03: printk("DISABLED!\n"); break;
546 case 0x02: printk("== 2X PCI\n"); break;
547 case 0x01: printk("== 133\n"); break;
548 case 0x00: printk("== 100\n"); break;
554 * setup_mmio_siimage - switch an SI controller into MMIO
555 * @dev: PCI device we are configuring
558 * Attempt to put the device into mmio mode. There are some slight
559 * complications here with certain systems where the mmio bar isnt
560 * mapped so we have to be sure we can fall back to I/O.
563 static unsigned int setup_mmio_siimage (struct pci_dev
*dev
, const char *name
)
565 unsigned long bar5
= pci_resource_start(dev
, 5);
566 unsigned long barsize
= pci_resource_len(dev
, 5);
568 void __iomem
*ioaddr
;
572 * Drop back to PIO if we can't map the mmio. Some
573 * systems seem to get terminally confused in the PCI
577 if(!request_mem_region(bar5
, barsize
, name
))
579 printk(KERN_WARNING
"siimage: IDE controller MMIO ports not available.\n");
583 ioaddr
= ioremap(bar5
, barsize
);
587 release_mem_region(bar5
, barsize
);
592 pci_set_drvdata(dev
, (void *) ioaddr
);
594 if (pdev_is_sata(dev
)) {
595 /* make sure IDE0/1 interrupts are not masked */
596 irq_mask
= (1 << 22) | (1 << 23);
597 tmp
= readl(ioaddr
+ 0x48);
598 if (tmp
& irq_mask
) {
600 writel(tmp
, ioaddr
+ 0x48);
601 readl(ioaddr
+ 0x48); /* flush */
603 writel(0, ioaddr
+ 0x148);
604 writel(0, ioaddr
+ 0x1C8);
607 writeb(0, ioaddr
+ 0xB4);
608 writeb(0, ioaddr
+ 0xF4);
609 tmpbyte
= readb(ioaddr
+ 0x4A);
611 switch(tmpbyte
& 0x30) {
613 /* In 100 MHz clocking, try and switch to 133 */
614 writeb(tmpbyte
|0x10, ioaddr
+ 0x4A);
617 /* On 133Mhz clocking */
620 /* On PCIx2 clocking */
623 /* Clocking is disabled */
624 /* 133 clock attempt to force it on */
625 writeb(tmpbyte
& ~0x20, ioaddr
+ 0x4A);
629 writeb( 0x72, ioaddr
+ 0xA1);
630 writew( 0x328A, ioaddr
+ 0xA2);
631 writel(0x62DD62DD, ioaddr
+ 0xA4);
632 writel(0x43924392, ioaddr
+ 0xA8);
633 writel(0x40094009, ioaddr
+ 0xAC);
634 writeb( 0x72, ioaddr
+ 0xE1);
635 writew( 0x328A, ioaddr
+ 0xE2);
636 writel(0x62DD62DD, ioaddr
+ 0xE4);
637 writel(0x43924392, ioaddr
+ 0xE8);
638 writel(0x40094009, ioaddr
+ 0xEC);
640 if (pdev_is_sata(dev
)) {
641 writel(0xFFFF0000, ioaddr
+ 0x108);
642 writel(0xFFFF0000, ioaddr
+ 0x188);
643 writel(0x00680000, ioaddr
+ 0x148);
644 writel(0x00680000, ioaddr
+ 0x1C8);
647 tmpbyte
= readb(ioaddr
+ 0x4A);
649 proc_reports_siimage(dev
, (tmpbyte
>>4), name
);
654 * init_chipset_siimage - set up an SI device
658 * Perform the initial PCI set up for this device. Attempt to switch
659 * to 133MHz clocking if the system isn't already set up to do it.
662 static unsigned int __devinit
init_chipset_siimage(struct pci_dev
*dev
, const char *name
)
668 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
670 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, (class_rev
) ? 1 : 255);
672 pci_read_config_byte(dev
, 0x8A, &BA5_EN
);
673 if ((BA5_EN
& 0x01) || (pci_resource_start(dev
, 5))) {
674 if (setup_mmio_siimage(dev
, name
)) {
679 pci_write_config_byte(dev
, 0x80, 0x00);
680 pci_write_config_byte(dev
, 0x84, 0x00);
681 pci_read_config_byte(dev
, 0x8A, &tmpbyte
);
682 switch(tmpbyte
& 0x30) {
684 /* 133 clock attempt to force it on */
685 pci_write_config_byte(dev
, 0x8A, tmpbyte
|0x10);
687 /* if clocking is disabled */
688 /* 133 clock attempt to force it on */
689 pci_write_config_byte(dev
, 0x8A, tmpbyte
& ~0x20);
694 /* BIOS set PCI x2 clocking */
698 pci_read_config_byte(dev
, 0x8A, &tmpbyte
);
700 pci_write_config_byte(dev
, 0xA1, 0x72);
701 pci_write_config_word(dev
, 0xA2, 0x328A);
702 pci_write_config_dword(dev
, 0xA4, 0x62DD62DD);
703 pci_write_config_dword(dev
, 0xA8, 0x43924392);
704 pci_write_config_dword(dev
, 0xAC, 0x40094009);
705 pci_write_config_byte(dev
, 0xB1, 0x72);
706 pci_write_config_word(dev
, 0xB2, 0x328A);
707 pci_write_config_dword(dev
, 0xB4, 0x62DD62DD);
708 pci_write_config_dword(dev
, 0xB8, 0x43924392);
709 pci_write_config_dword(dev
, 0xBC, 0x40094009);
711 proc_reports_siimage(dev
, (tmpbyte
>>4), name
);
716 * init_mmio_iops_siimage - set up the iops for MMIO
717 * @hwif: interface to set up
719 * The basic setup here is fairly simple, we can use standard MMIO
720 * operations. However we do have to set the taskfile register offsets
721 * by hand as there isnt a standard defined layout for them this
724 * The hardware supports buffered taskfiles and also some rather nice
725 * extended PRD tables. For better SI3112 support use the libata driver
728 static void __devinit
init_mmio_iops_siimage(ide_hwif_t
*hwif
)
730 struct pci_dev
*dev
= hwif
->pci_dev
;
731 void *addr
= pci_get_drvdata(dev
);
732 u8 ch
= hwif
->channel
;
737 * Fill in the basic HWIF bits
740 default_hwif_mmiops(hwif
);
741 hwif
->hwif_data
= addr
;
744 * Now set up the hw. We have to do this ourselves as
745 * the MMIO layout isnt the same as the standard port
749 memset(&hw
, 0, sizeof(hw_regs_t
));
751 base
= (unsigned long)addr
;
758 * The buffered task file doesn't have status/control
759 * so we can't currently use it sanely since we want to
762 hw
.io_ports
[IDE_DATA_OFFSET
] = base
;
763 hw
.io_ports
[IDE_ERROR_OFFSET
] = base
+ 1;
764 hw
.io_ports
[IDE_NSECTOR_OFFSET
] = base
+ 2;
765 hw
.io_ports
[IDE_SECTOR_OFFSET
] = base
+ 3;
766 hw
.io_ports
[IDE_LCYL_OFFSET
] = base
+ 4;
767 hw
.io_ports
[IDE_HCYL_OFFSET
] = base
+ 5;
768 hw
.io_ports
[IDE_SELECT_OFFSET
] = base
+ 6;
769 hw
.io_ports
[IDE_STATUS_OFFSET
] = base
+ 7;
770 hw
.io_ports
[IDE_CONTROL_OFFSET
] = base
+ 10;
772 hw
.io_ports
[IDE_IRQ_OFFSET
] = 0;
774 if (pdev_is_sata(dev
)) {
775 base
= (unsigned long)addr
;
778 hwif
->sata_scr
[SATA_STATUS_OFFSET
] = base
+ 0x104;
779 hwif
->sata_scr
[SATA_ERROR_OFFSET
] = base
+ 0x108;
780 hwif
->sata_scr
[SATA_CONTROL_OFFSET
] = base
+ 0x100;
781 hwif
->sata_misc
[SATA_MISC_OFFSET
] = base
+ 0x140;
782 hwif
->sata_misc
[SATA_PHY_OFFSET
] = base
+ 0x144;
783 hwif
->sata_misc
[SATA_IEN_OFFSET
] = base
+ 0x148;
786 hw
.irq
= hwif
->pci_dev
->irq
;
788 memcpy(&hwif
->hw
, &hw
, sizeof(hw
));
789 memcpy(hwif
->io_ports
, hwif
->hw
.io_ports
, sizeof(hwif
->hw
.io_ports
));
793 base
= (unsigned long) addr
;
795 hwif
->dma_base
= base
+ (ch
? 0x08 : 0x00);
800 static int is_dev_seagate_sata(ide_drive_t
*drive
)
802 const char *s
= &drive
->id
->model
[0];
808 len
= strnlen(s
, sizeof(drive
->id
->model
));
810 if ((len
> 4) && (!memcmp(s
, "ST", 2))) {
811 if ((!memcmp(s
+ len
- 2, "AS", 2)) ||
812 (!memcmp(s
+ len
- 3, "ASL", 3))) {
813 printk(KERN_INFO
"%s: applying pessimistic Seagate "
814 "errata fix\n", drive
->name
);
822 * siimage_fixup - post probe fixups
823 * @hwif: interface to fix up
825 * Called after drive probe we use this to decide whether the
826 * Seagate fixup must be applied. This used to be in init_iops but
827 * that can occur before we know what drives are present.
830 static void __devinit
siimage_fixup(ide_hwif_t
*hwif
)
832 /* Try and raise the rqsize */
833 if (!is_sata(hwif
) || !is_dev_seagate_sata(&hwif
->drives
[0]))
838 * init_iops_siimage - set up iops
839 * @hwif: interface to set up
841 * Do the basic setup for the SIIMAGE hardware interface
842 * and then do the MMIO setup if we can. This is the first
843 * look in we get for setting up the hwif so that we
844 * can get the iops right before using them.
847 static void __devinit
init_iops_siimage(ide_hwif_t
*hwif
)
849 struct pci_dev
*dev
= hwif
->pci_dev
;
852 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
855 hwif
->hwif_data
= NULL
;
857 /* Pessimal until we finish probing */
860 if (pci_get_drvdata(dev
) == NULL
)
862 init_mmio_iops_siimage(hwif
);
866 * ata66_siimage - check for 80 pin cable
867 * @hwif: interface to check
869 * Check for the presence of an ATA66 capable cable on the
873 static u8 __devinit
ata66_siimage(ide_hwif_t
*hwif
)
875 unsigned long addr
= siimage_selreg(hwif
, 0);
878 if (pci_get_drvdata(hwif
->pci_dev
) == NULL
)
879 pci_read_config_byte(hwif
->pci_dev
, addr
, &ata66
);
881 ata66
= hwif
->INB(addr
);
883 return (ata66
& 0x01) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
887 * init_hwif_siimage - set up hwif structs
888 * @hwif: interface to set up
890 * We do the basic set up of the interface structure. The SIIMAGE
891 * requires several custom handlers so we override the default
892 * ide DMA handlers appropriately
895 static void __devinit
init_hwif_siimage(ide_hwif_t
*hwif
)
899 hwif
->resetproc
= &siimage_reset
;
900 hwif
->set_pio_mode
= &sil_set_pio_mode
;
901 hwif
->set_dma_mode
= &sil_set_dma_mode
;
902 hwif
->reset_poll
= &siimage_reset_poll
;
903 hwif
->pre_reset
= &siimage_pre_reset
;
904 hwif
->udma_filter
= &sil_udma_filter
;
907 static int first
= 1;
909 hwif
->busproc
= &siimage_busproc
;
912 printk(KERN_INFO
"siimage: For full SATA support you should use the libata sata_sil module.\n");
917 hwif
->drives
[0].autotune
= hwif
->drives
[1].autotune
= 1;
919 if (hwif
->dma_base
== 0)
922 hwif
->ultra_mask
= 0x7f;
923 hwif
->mwdma_mask
= 0x07;
928 hwif
->ide_dma_check
= &siimage_config_drive_for_dma
;
930 if (hwif
->cbl
!= ATA_CBL_PATA40_SHORT
)
931 hwif
->cbl
= ata66_siimage(hwif
);
934 hwif
->ide_dma_test_irq
= &siimage_mmio_ide_dma_test_irq
;
936 hwif
->ide_dma_test_irq
= & siimage_io_ide_dma_test_irq
;
940 * The BIOS often doesn't set up DMA on this controller
941 * so we always do it.
945 hwif
->drives
[0].autodma
= hwif
->autodma
;
946 hwif
->drives
[1].autodma
= hwif
->autodma
;
949 #define DECLARE_SII_DEV(name_str) \
952 .init_chipset = init_chipset_siimage, \
953 .init_iops = init_iops_siimage, \
954 .init_hwif = init_hwif_siimage, \
955 .fixup = siimage_fixup, \
956 .autodma = AUTODMA, \
957 .bootable = ON_BOARD, \
958 .pio_mask = ATA_PIO4, \
961 static ide_pci_device_t siimage_chipsets
[] __devinitdata
= {
962 /* 0 */ DECLARE_SII_DEV("SiI680"),
963 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
964 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
968 * siimage_init_one - pci layer discovery entry
970 * @id: ident table entry
972 * Called by the PCI code when it finds an SI680 or SI3112 controller.
973 * We then use the IDE PCI generic helper to do most of the work.
976 static int __devinit
siimage_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
978 return ide_setup_pci_device(dev
, &siimage_chipsets
[id
->driver_data
]);
981 static struct pci_device_id siimage_pci_tbl
[] = {
982 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_SII_680
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
983 #ifdef CONFIG_BLK_DEV_IDE_SATA
984 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_SII_3112
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 1},
985 { PCI_VENDOR_ID_CMD
, PCI_DEVICE_ID_SII_1210SA
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 2},
989 MODULE_DEVICE_TABLE(pci
, siimage_pci_tbl
);
991 static struct pci_driver driver
= {
993 .id_table
= siimage_pci_tbl
,
994 .probe
= siimage_init_one
,
997 static int __init
siimage_ide_init(void)
999 return ide_pci_register_driver(&driver
);
1002 module_init(siimage_ide_init
);
1004 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1005 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1006 MODULE_LICENSE("GPL");