2 * linux/drivers/ide/pci/sl82c105.c
4 * SL82C105/Winbond 553 IDE driver
8 * Drive tuning added from Rebel.com's kernel sources
9 * -- Russell King (15/11/98) linux@arm.linux.org.uk
11 * Merge in Russell's HW workarounds, fix various problems
12 * with the timing registers setup.
13 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
15 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
18 #include <linux/types.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/timer.h>
23 #include <linux/ioport.h>
24 #include <linux/interrupt.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/pci.h>
28 #include <linux/ide.h>
36 #define DBG(arg) printk arg
41 * SL82C105 PCI config register 0x40 bits.
43 #define CTRL_IDE_IRQB (1 << 30)
44 #define CTRL_IDE_IRQA (1 << 28)
45 #define CTRL_LEGIRQ (1 << 11)
46 #define CTRL_P1F16 (1 << 5)
47 #define CTRL_P1EN (1 << 4)
48 #define CTRL_P0F16 (1 << 1)
49 #define CTRL_P0EN (1 << 0)
52 * Convert a PIO mode and cycle time to the required on/off times
53 * for the interface. This has protection against runaway timings.
55 static unsigned int get_pio_timings(ide_pio_data_t
*p
)
57 unsigned int cmd_on
, cmd_off
;
59 cmd_on
= (ide_pio_timings
[p
->pio_mode
].active_time
+ 29) / 30;
60 cmd_off
= (p
->cycle_time
- 30 * cmd_on
+ 29) / 30;
68 return (cmd_on
- 1) << 8 | (cmd_off
- 1) | (p
->use_iordy
? 0x40 : 0x00);
72 * Configure the chipset for PIO mode.
74 static u8
sl82c105_tune_pio(ide_drive_t
*drive
, u8 pio
)
76 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
77 int reg
= 0x44 + drive
->dn
* 4;
81 DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive
->name
, pio
));
83 pio
= ide_get_best_pio_mode(drive
, pio
, 5, &p
);
85 drv_ctrl
= get_pio_timings(&p
);
88 * Store the PIO timings so that we can restore them
89 * in case DMA will be turned off...
91 drive
->drive_data
&= 0xffff0000;
92 drive
->drive_data
|= drv_ctrl
;
94 if (!drive
->using_dma
) {
96 * If we are actually using MW DMA, then we can not
97 * reprogram the interface drive control register.
99 pci_write_config_word(dev
, reg
, drv_ctrl
);
100 pci_read_config_word (dev
, reg
, &drv_ctrl
);
103 printk(KERN_DEBUG
"%s: selected %s (%dns) (%04X)\n", drive
->name
,
104 ide_xfer_verbose(pio
+ XFER_PIO_0
), p
.cycle_time
, drv_ctrl
);
110 * Configure the drive and chipset for a new transfer speed.
112 static int sl82c105_tune_chipset(ide_drive_t
*drive
, u8 speed
)
114 static u16 mwdma_timings
[] = {0x0707, 0x0201, 0x0200};
117 DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
118 drive
->name
, ide_xfer_verbose(speed
)));
120 speed
= ide_rate_filter(drive
, speed
);
126 drv_ctrl
= mwdma_timings
[speed
- XFER_MW_DMA_0
];
129 * Store the DMA timings so that we can actually program
130 * them when DMA will be turned on...
132 drive
->drive_data
&= 0x0000ffff;
133 drive
->drive_data
|= (unsigned long)drv_ctrl
<< 16;
136 * If we are already using DMA, we just reprogram
137 * the drive control register.
139 if (drive
->using_dma
) {
140 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
141 int reg
= 0x44 + drive
->dn
* 4;
143 pci_write_config_word(dev
, reg
, drv_ctrl
);
152 (void) sl82c105_tune_pio(drive
, speed
- XFER_PIO_0
);
158 return ide_config_drive_speed(drive
, speed
);
162 * Check to see if the drive and chipset are capable of DMA mode.
164 static int sl82c105_ide_dma_check(ide_drive_t
*drive
)
166 DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive
->name
));
168 if (ide_tune_dma(drive
))
175 * The SL82C105 holds off all IDE interrupts while in DMA mode until
176 * all DMA activity is completed. Sometimes this causes problems (eg,
177 * when the drive wants to report an error condition).
179 * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
180 * state machine. We need to kick this to work around various bugs.
182 static inline void sl82c105_reset_host(struct pci_dev
*dev
)
186 pci_read_config_word(dev
, 0x7e, &val
);
187 pci_write_config_word(dev
, 0x7e, val
| (1 << 2));
188 pci_write_config_word(dev
, 0x7e, val
& ~(1 << 2));
192 * If we get an IRQ timeout, it might be that the DMA state machine
193 * got confused. Fix from Todd Inglett. Details from Winbond.
195 * This function is called when the IDE timer expires, the drive
196 * indicates that it is READY, and we were waiting for DMA to complete.
198 static void sl82c105_dma_lost_irq(ide_drive_t
*drive
)
200 ide_hwif_t
*hwif
= HWIF(drive
);
201 struct pci_dev
*dev
= hwif
->pci_dev
;
202 u32 val
, mask
= hwif
->channel
? CTRL_IDE_IRQB
: CTRL_IDE_IRQA
;
205 printk("sl82c105: lost IRQ, resetting host\n");
208 * Check the raw interrupt from the drive.
210 pci_read_config_dword(dev
, 0x40, &val
);
212 printk("sl82c105: drive was requesting IRQ, but host lost it\n");
215 * Was DMA enabled? If so, disable it - we're resetting the
216 * host. The IDE layer will be handling the drive for us.
218 dma_cmd
= inb(hwif
->dma_command
);
220 outb(dma_cmd
& ~1, hwif
->dma_command
);
221 printk("sl82c105: DMA was enabled\n");
224 sl82c105_reset_host(dev
);
228 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
229 * Winbond recommend that the DMA state machine is reset prior to
230 * setting the bus master DMA enable bit.
232 * The generic IDE core will have disabled the BMEN bit before this
233 * function is called.
235 static void sl82c105_dma_start(ide_drive_t
*drive
)
237 ide_hwif_t
*hwif
= HWIF(drive
);
238 struct pci_dev
*dev
= hwif
->pci_dev
;
240 sl82c105_reset_host(dev
);
241 ide_dma_start(drive
);
244 static void sl82c105_dma_timeout(ide_drive_t
*drive
)
246 DBG(("sl82c105_dma_timeout(drive:%s)\n", drive
->name
));
248 sl82c105_reset_host(HWIF(drive
)->pci_dev
);
249 ide_dma_timeout(drive
);
252 static int sl82c105_ide_dma_on(ide_drive_t
*drive
)
254 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
255 int rc
, reg
= 0x44 + drive
->dn
* 4;
257 DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive
->name
));
259 rc
= __ide_dma_on(drive
);
261 pci_write_config_word(dev
, reg
, drive
->drive_data
>> 16);
263 printk(KERN_INFO
"%s: DMA enabled\n", drive
->name
);
268 static void sl82c105_dma_off_quietly(ide_drive_t
*drive
)
270 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
271 int reg
= 0x44 + drive
->dn
* 4;
273 DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive
->name
));
275 pci_write_config_word(dev
, reg
, drive
->drive_data
);
277 ide_dma_off_quietly(drive
);
281 * Ok, that is nasty, but we must make sure the DMA timings
282 * won't be used for a PIO access. The solution here is
283 * to make sure the 16 bits mode is diabled on the channel
284 * when DMA is enabled, thus causing the chip to use PIO0
285 * timings for those operations.
287 static void sl82c105_selectproc(ide_drive_t
*drive
)
289 ide_hwif_t
*hwif
= HWIF(drive
);
290 struct pci_dev
*dev
= hwif
->pci_dev
;
293 //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
295 mask
= hwif
->channel
? CTRL_P1F16
: CTRL_P0F16
;
296 old
= val
= (u32
)pci_get_drvdata(dev
);
297 if (drive
->using_dma
)
302 pci_write_config_dword(dev
, 0x40, val
);
303 pci_set_drvdata(dev
, (void *)val
);
308 * ATA reset will clear the 16 bits mode in the control
309 * register, we need to update our cache
311 static void sl82c105_resetproc(ide_drive_t
*drive
)
313 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
316 DBG(("sl82c105_resetproc(drive:%s)\n", drive
->name
));
318 pci_read_config_dword(dev
, 0x40, &val
);
319 pci_set_drvdata(dev
, (void *)val
);
323 * We only deal with PIO mode here - DMA mode 'using_dma' is not
324 * initialised at the point that this function is called.
326 static void sl82c105_tune_drive(ide_drive_t
*drive
, u8 pio
)
328 DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive
->name
, pio
));
330 pio
= sl82c105_tune_pio(drive
, pio
);
331 (void) ide_config_drive_speed(drive
, XFER_PIO_0
+ pio
);
335 * Return the revision of the Winbond bridge
336 * which this function is part of.
338 static unsigned int sl82c105_bridge_revision(struct pci_dev
*dev
)
340 struct pci_dev
*bridge
;
343 * The bridge should be part of the same device, but function 0.
345 bridge
= pci_get_bus_and_slot(dev
->bus
->number
,
346 PCI_DEVFN(PCI_SLOT(dev
->devfn
), 0));
351 * Make sure it is a Winbond 553 and is an ISA bridge.
353 if (bridge
->vendor
!= PCI_VENDOR_ID_WINBOND
||
354 bridge
->device
!= PCI_DEVICE_ID_WINBOND_83C553
||
355 bridge
->class >> 8 != PCI_CLASS_BRIDGE_ISA
) {
360 * We need to find function 0's revision, not function 1
364 return bridge
->revision
;
368 * Enable the PCI device
370 * --BenH: It's arch fixup code that should enable channels that
371 * have not been enabled by firmware. I decided we can still enable
372 * channel 0 here at least, but channel 1 has to be enabled by
373 * firmware or arch code. We still set both to 16 bits mode.
375 static unsigned int __devinit
init_chipset_sl82c105(struct pci_dev
*dev
, const char *msg
)
379 DBG(("init_chipset_sl82c105()\n"));
381 pci_read_config_dword(dev
, 0x40, &val
);
382 val
|= CTRL_P0EN
| CTRL_P0F16
| CTRL_P1F16
;
383 pci_write_config_dword(dev
, 0x40, val
);
384 pci_set_drvdata(dev
, (void *)val
);
390 * Initialise IDE channel
392 static void __devinit
init_hwif_sl82c105(ide_hwif_t
*hwif
)
396 DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif
->index
));
398 hwif
->tuneproc
= &sl82c105_tune_drive
;
399 hwif
->speedproc
= &sl82c105_tune_chipset
;
400 hwif
->selectproc
= &sl82c105_selectproc
;
401 hwif
->resetproc
= &sl82c105_resetproc
;
404 * We support 32-bit I/O on this interface, and
405 * it doesn't have problems with interrupts.
407 hwif
->drives
[0].io_32bit
= hwif
->drives
[1].io_32bit
= 1;
408 hwif
->drives
[0].unmask
= hwif
->drives
[1].unmask
= 1;
411 * We always autotune PIO, this is done before DMA is checked,
412 * so there's no risk of accidentally disabling DMA
414 hwif
->drives
[0].autotune
= hwif
->drives
[1].autotune
= 1;
419 rev
= sl82c105_bridge_revision(hwif
->pci_dev
);
422 * Never ever EVER under any circumstances enable
423 * DMA when the bridge is this old.
425 printk(" %s: Winbond W83C553 bridge revision %d, "
426 "BM-DMA disabled\n", hwif
->name
, rev
);
431 hwif
->mwdma_mask
= 0x07;
433 hwif
->ide_dma_check
= &sl82c105_ide_dma_check
;
434 hwif
->ide_dma_on
= &sl82c105_ide_dma_on
;
435 hwif
->dma_off_quietly
= &sl82c105_dma_off_quietly
;
436 hwif
->dma_lost_irq
= &sl82c105_dma_lost_irq
;
437 hwif
->dma_start
= &sl82c105_dma_start
;
438 hwif
->dma_timeout
= &sl82c105_dma_timeout
;
442 hwif
->drives
[0].autodma
= hwif
->drives
[1].autodma
= hwif
->autodma
;
445 hwif
->serialized
= hwif
->mate
->serialized
= 1;
448 static ide_pci_device_t sl82c105_chipset __devinitdata
= {
450 .init_chipset
= init_chipset_sl82c105
,
451 .init_hwif
= init_hwif_sl82c105
,
453 .autodma
= NOAUTODMA
,
454 .enablebits
= {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
455 .bootable
= ON_BOARD
,
458 static int __devinit
sl82c105_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
460 return ide_setup_pci_device(dev
, &sl82c105_chipset
);
463 static struct pci_device_id sl82c105_pci_tbl
[] = {
464 { PCI_DEVICE(PCI_VENDOR_ID_WINBOND
, PCI_DEVICE_ID_WINBOND_82C105
), 0},
467 MODULE_DEVICE_TABLE(pci
, sl82c105_pci_tbl
);
469 static struct pci_driver driver
= {
470 .name
= "W82C105_IDE",
471 .id_table
= sl82c105_pci_tbl
,
472 .probe
= sl82c105_init_one
,
475 static int __init
sl82c105_ide_init(void)
477 return ide_pci_register_driver(&driver
);
480 module_init(sl82c105_ide_init
);
482 MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
483 MODULE_LICENSE("GPL");