2 * linux/drivers/ide/pci/slc90e66.c Version 0.15 Jul 6, 2007
4 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
7 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
8 * but this keeps the ISA-Bridge and slots alive.
12 #include <linux/types.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/hdreg.h>
18 #include <linux/ide.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
24 static u8
slc90e66_dma_2_pio (u8 xfer_rate
) {
45 static void slc90e66_tune_pio (ide_drive_t
*drive
, u8 pio
)
47 ide_hwif_t
*hwif
= HWIF(drive
);
48 struct pci_dev
*dev
= hwif
->pci_dev
;
49 int is_slave
= drive
->dn
& 1;
50 int master_port
= hwif
->channel
? 0x42 : 0x40;
51 int slave_port
= 0x44;
57 static const u8 timings
[][2]= {
64 spin_lock_irqsave(&ide_lock
, flags
);
65 pci_read_config_word(dev
, master_port
, &master_data
);
68 control
|= 1; /* Programmable timing on */
69 if (drive
->media
== ide_disk
)
70 control
|= 4; /* Prefetch, post write */
72 control
|= 2; /* IORDY */
74 master_data
|= 0x4000;
75 master_data
&= ~0x0070;
77 /* Set PPE, IE and TIME */
78 master_data
|= control
<< 4;
80 pci_read_config_byte(dev
, slave_port
, &slave_data
);
81 slave_data
&= hwif
->channel
? 0x0f : 0xf0;
82 slave_data
|= ((timings
[pio
][0] << 2) | timings
[pio
][1]) <<
83 (hwif
->channel
? 4 : 0);
85 master_data
&= ~0x3307;
87 /* enable PPE, IE and TIME */
88 master_data
|= control
;
90 master_data
|= (timings
[pio
][0] << 12) | (timings
[pio
][1] << 8);
92 pci_write_config_word(dev
, master_port
, master_data
);
94 pci_write_config_byte(dev
, slave_port
, slave_data
);
95 spin_unlock_irqrestore(&ide_lock
, flags
);
98 static void slc90e66_tune_drive (ide_drive_t
*drive
, u8 pio
)
100 pio
= ide_get_best_pio_mode(drive
, pio
, 4);
101 slc90e66_tune_pio(drive
, pio
);
102 (void) ide_config_drive_speed(drive
, XFER_PIO_0
+ pio
);
105 static int slc90e66_tune_chipset(ide_drive_t
*drive
, const u8 speed
)
107 ide_hwif_t
*hwif
= HWIF(drive
);
108 struct pci_dev
*dev
= hwif
->pci_dev
;
109 u8 maslave
= hwif
->channel
? 0x42 : 0x40;
110 int sitre
= 0, a_speed
= 7 << (drive
->dn
* 4);
111 int u_speed
= 0, u_flag
= 1 << drive
->dn
;
112 u16 reg4042
, reg44
, reg48
, reg4a
;
114 pci_read_config_word(dev
, maslave
, ®4042
);
115 sitre
= (reg4042
& 0x4000) ? 1 : 0;
116 pci_read_config_word(dev
, 0x44, ®44
);
117 pci_read_config_word(dev
, 0x48, ®48
);
118 pci_read_config_word(dev
, 0x4a, ®4a
);
121 case XFER_UDMA_4
: u_speed
= 4 << (drive
->dn
* 4); break;
122 case XFER_UDMA_3
: u_speed
= 3 << (drive
->dn
* 4); break;
123 case XFER_UDMA_2
: u_speed
= 2 << (drive
->dn
* 4); break;
124 case XFER_UDMA_1
: u_speed
= 1 << (drive
->dn
* 4); break;
125 case XFER_UDMA_0
: u_speed
= 0 << (drive
->dn
* 4); break;
128 case XFER_SW_DMA_2
: break;
133 case XFER_PIO_0
: break;
137 if (speed
>= XFER_UDMA_0
) {
138 if (!(reg48
& u_flag
))
139 pci_write_config_word(dev
, 0x48, reg48
|u_flag
);
140 /* FIXME: (reg4a & a_speed) ? */
141 if ((reg4a
& u_speed
) != u_speed
) {
142 pci_write_config_word(dev
, 0x4a, reg4a
& ~a_speed
);
143 pci_read_config_word(dev
, 0x4a, ®4a
);
144 pci_write_config_word(dev
, 0x4a, reg4a
|u_speed
);
148 pci_write_config_word(dev
, 0x48, reg48
& ~u_flag
);
150 pci_write_config_word(dev
, 0x4a, reg4a
& ~a_speed
);
153 if (speed
> XFER_PIO_4
)
154 slc90e66_tune_pio(drive
, slc90e66_dma_2_pio(speed
));
156 slc90e66_tune_pio(drive
, speed
- XFER_PIO_0
);
158 return ide_config_drive_speed(drive
, speed
);
161 static int slc90e66_config_drive_xfer_rate (ide_drive_t
*drive
)
163 drive
->init_speed
= 0;
165 if (ide_tune_dma(drive
))
168 if (ide_use_fast_pio(drive
))
169 slc90e66_tune_drive(drive
, 255);
174 static void __devinit
init_hwif_slc90e66 (ide_hwif_t
*hwif
)
177 u8 mask
= hwif
->channel
? 0x01 : 0x02; /* bit0:Primary */
182 hwif
->irq
= hwif
->channel
? 15 : 14;
184 hwif
->speedproc
= &slc90e66_tune_chipset
;
185 hwif
->tuneproc
= &slc90e66_tune_drive
;
187 pci_read_config_byte(hwif
->pci_dev
, 0x47, ®47
);
189 if (!hwif
->dma_base
) {
190 hwif
->drives
[0].autotune
= 1;
191 hwif
->drives
[1].autotune
= 1;
196 hwif
->ultra_mask
= 0x1f;
197 hwif
->mwdma_mask
= 0x06;
198 hwif
->swdma_mask
= 0x04;
200 if (hwif
->cbl
!= ATA_CBL_PATA40_SHORT
)
201 /* bit[0(1)]: 0:80, 1:40 */
202 hwif
->cbl
= (reg47
& mask
) ? ATA_CBL_PATA40
: ATA_CBL_PATA80
;
204 hwif
->ide_dma_check
= &slc90e66_config_drive_xfer_rate
;
208 hwif
->drives
[0].autodma
= hwif
->autodma
;
209 hwif
->drives
[1].autodma
= hwif
->autodma
;
212 static ide_pci_device_t slc90e66_chipset __devinitdata
= {
214 .init_hwif
= init_hwif_slc90e66
,
216 .enablebits
= {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
217 .bootable
= ON_BOARD
,
218 .pio_mask
= ATA_PIO4
,
221 static int __devinit
slc90e66_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
223 return ide_setup_pci_device(dev
, &slc90e66_chipset
);
226 static struct pci_device_id slc90e66_pci_tbl
[] = {
227 { PCI_DEVICE(PCI_VENDOR_ID_EFAR
, PCI_DEVICE_ID_EFAR_SLC90E66_1
), 0},
230 MODULE_DEVICE_TABLE(pci
, slc90e66_pci_tbl
);
232 static struct pci_driver driver
= {
233 .name
= "SLC90e66_IDE",
234 .id_table
= slc90e66_pci_tbl
,
235 .probe
= slc90e66_init_one
,
238 static int __init
slc90e66_ide_init(void)
240 return ide_pci_register_driver(&driver
);
243 module_init(slc90e66_ide_init
);
245 MODULE_AUTHOR("Andre Hedrick");
246 MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
247 MODULE_LICENSE("GPL");