drivers/ide/pci/tc86c001.c

   1 /*
   2  * drivers/ide/pci/tc86c001.c   Version 1.00    Dec 12, 2006
   3  *
   4  * Copyright (C) 2002 Toshiba Corporation
   5  * Copyright (C) 2005-2006 MontaVista Software, Inc. <source@mvista.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2.  This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/pci.h>
  14 #include <linux/ide.h>
  15
  16 static int tc86c001_tune_chipset(ide_drive_t *drive, const u8 speed)
  17 {
  18         ide_hwif_t *hwif        = HWIF(drive);
  19         unsigned long scr_port  = hwif->config_data + (drive->dn ? 0x02 : 0x00);
  20         u16 mode, scr           = hwif->INW(scr_port);
  21
  22         switch (speed) {
  23                 case XFER_UDMA_4:       mode = 0x00c0; break;
  24                 case XFER_UDMA_3:       mode = 0x00b0; break;
  25                 case XFER_UDMA_2:       mode = 0x00a0; break;
  26                 case XFER_UDMA_1:       mode = 0x0090; break;
  27                 case XFER_UDMA_0:       mode = 0x0080; break;
  28                 case XFER_MW_DMA_2:     mode = 0x0070; break;
  29                 case XFER_MW_DMA_1:     mode = 0x0060; break;
  30                 case XFER_MW_DMA_0:     mode = 0x0050; break;
  31                 case XFER_PIO_4:        mode = 0x0400; break;
  32                 case XFER_PIO_3:        mode = 0x0300; break;
  33                 case XFER_PIO_2:        mode = 0x0200; break;
  34                 case XFER_PIO_1:        mode = 0x0100; break;
  35                 case XFER_PIO_0:
  36                 default:                mode = 0x0000; break;
  37         }
  38
  39         scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f;
  40         scr |= mode;
  41         outw(scr, scr_port);
  42
  43         return ide_config_drive_speed(drive, speed);
  44 }
  45
  46 static void tc86c001_set_pio_mode(ide_drive_t *drive, const u8 pio)
  47 {
  48         (void) tc86c001_tune_chipset(drive, XFER_PIO_0 + pio);
  49 }
  50
  51 /*
  52  * HACKITY HACK
  53  *
  54  * This is a workaround for the limitation 5 of the TC86C001 IDE controller:
  55  * if a DMA transfer terminates prematurely, the controller leaves the device's
  56  * interrupt request (INTRQ) pending and does not generate a PCI interrupt (or
  57  * set the interrupt bit in the DMA status register), thus no PCI interrupt
  58  * will occur until a DMA transfer has been successfully completed.
  59  *
  60  * We work around this by initiating dummy, zero-length DMA transfer on
  61  * a DMA timeout expiration. I found no better way to do this with the current
  62  * IDE core than to temporarily replace a higher level driver's timer expiry
  63  * handler with our own backing up to that handler in case our recovery fails.
  64  */
  65 static int tc86c001_timer_expiry(ide_drive_t *drive)
  66 {
  67         ide_hwif_t *hwif        = HWIF(drive);
  68         ide_expiry_t *expiry    = ide_get_hwifdata(hwif);
  69         ide_hwgroup_t *hwgroup  = HWGROUP(drive);
  70         u8 dma_stat             = hwif->INB(hwif->dma_status);
  71
  72         /* Restore a higher level driver's expiry handler first. */
  73         hwgroup->expiry = expiry;
  74
  75         if ((dma_stat & 5) == 1) {      /* DMA active and no interrupt */
  76                 unsigned long sc_base   = hwif->config_data;
  77                 unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04);
  78                 u8 dma_cmd              = hwif->INB(hwif->dma_command);
  79
  80                 printk(KERN_WARNING "%s: DMA interrupt possibly stuck, "
  81                        "attempting recovery...\n", drive->name);
  82
  83                 /* Stop DMA */
  84                 outb(dma_cmd & ~0x01, hwif->dma_command);
  85
  86                 /* Setup the dummy DMA transfer */
  87                 outw(0, sc_base + 0x0a);        /* Sector Count */
  88                 outw(0, twcr_port);     /* Transfer Word Count 1 or 2 */
  89
  90                 /* Start the dummy DMA transfer */
  91                 outb(0x00, hwif->dma_command); /* clear R_OR_WCTR for write */
  92                 outb(0x01, hwif->dma_command); /* set START_STOPBM */
  93
  94                 /*
  95                  * If an interrupt was pending, it should come thru shortly.
  96                  * If not, a higher level driver's expiry handler should
  97                  * eventually cause some kind of recovery from the DMA stall.
  98                  */
  99                 return WAIT_MIN_SLEEP;
 100         }
 101
 102         /* Chain to the restored expiry handler if DMA wasn't active. */
 103         if (likely(expiry != NULL))
 104                 return expiry(drive);
 105
 106         /* If there was no handler, "emulate" that for ide_timer_expiry()... */
 107         return -1;
 108 }
 109
 110 static void tc86c001_dma_start(ide_drive_t *drive)
 111 {
 112         ide_hwif_t *hwif        = HWIF(drive);
 113         ide_hwgroup_t *hwgroup  = HWGROUP(drive);
 114         unsigned long sc_base   = hwif->config_data;
 115         unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04);
 116         unsigned long nsectors  = hwgroup->rq->nr_sectors;
 117
 118         /*
 119          * We have to manually load the sector count and size into
 120          * the appropriate system control registers for DMA to work
 121          * with LBA48 and ATAPI devices...
 122          */
 123         outw(nsectors, sc_base + 0x0a); /* Sector Count */
 124         outw(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */
 125
 126         /* Install our timeout expiry hook, saving the current handler... */
 127         ide_set_hwifdata(hwif, hwgroup->expiry);
 128         hwgroup->expiry = &tc86c001_timer_expiry;
 129
 130         ide_dma_start(drive);
 131 }
 132
 133 static int tc86c001_busproc(ide_drive_t *drive, int state)
 134 {
 135         ide_hwif_t *hwif        = HWIF(drive);
 136         unsigned long sc_base   = hwif->config_data;
 137         u16 scr1;
 138
 139         /* System Control 1 Register bit 11 (ATA Hard Reset) read */
 140         scr1 = hwif->INW(sc_base + 0x00);
 141
 142         switch (state) {
 143                 case BUSSTATE_ON:
 144                         if (!(scr1 & 0x0800))
 145                                 return 0;
 146                         scr1 &= ~0x0800;
 147
 148                         hwif->drives[0].failures = hwif->drives[1].failures = 0;
 149                         break;
 150                 case BUSSTATE_OFF:
 151                         if (scr1 & 0x0800)
 152                                 return 0;
 153                         scr1 |= 0x0800;
 154
 155                         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 156                         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 157                         break;
 158                 default:
 159                         return -EINVAL;
 160         }
 161
 162         /* System Control 1 Register bit 11 (ATA Hard Reset) write */
 163         outw(scr1, sc_base + 0x00);
 164         return 0;
 165 }
 166
 167 static int tc86c001_config_drive_xfer_rate(ide_drive_t *drive)
 168 {
 169         if (ide_tune_dma(drive))
 170                 return 0;
 171
 172         if (ide_use_fast_pio(drive))
 173                 ide_set_max_pio(drive);
 174
 175         return -1;
 176 }
 177
 178 static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
 179 {
 180         unsigned long sc_base   = pci_resource_start(hwif->pci_dev, 5);
 181         u16 scr1                = hwif->INW(sc_base + 0x00);;
 182
 183         /* System Control 1 Register bit 15 (Soft Reset) set */
 184         outw(scr1 |  0x8000, sc_base + 0x00);
 185
 186         /* System Control 1 Register bit 14 (FIFO Reset) set */
 187         outw(scr1 |  0x4000, sc_base + 0x00);
 188
 189         /* System Control 1 Register: reset clear */
 190         outw(scr1 & ~0xc000, sc_base + 0x00);
 191
 192         /* Store the system control register base for convenience... */
 193         hwif->config_data = sc_base;
 194
 195         hwif->set_pio_mode = &tc86c001_set_pio_mode;
 196         hwif->speedproc = &tc86c001_tune_chipset;
 197         hwif->busproc   = &tc86c001_busproc;
 198
 199         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 200
 201         if (!hwif->dma_base)
 202                 return;
 203
 204         /*
 205          * Sector Count Control Register bits 0 and 1 set:
 206          * software sets Sector Count Register for master and slave device
 207          */
 208         outw(0x0003, sc_base + 0x0c);
 209
 210         /* Sector Count Register limit */
 211         hwif->rqsize     = 0xffff;
 212
 213         hwif->atapi_dma  = 1;
 214         hwif->ultra_mask = 0x1f;
 215         hwif->mwdma_mask = 0x07;
 216
 217         hwif->ide_dma_check     = &tc86c001_config_drive_xfer_rate;
 218         hwif->dma_start         = &tc86c001_dma_start;
 219
 220         if (hwif->cbl != ATA_CBL_PATA40_SHORT) {
 221                 /*
 222                  * System Control  1 Register bit 13 (PDIAGN):
 223                  * 0=80-pin cable, 1=40-pin cable
 224                  */
 225                 scr1 = hwif->INW(sc_base + 0x00);
 226                 hwif->cbl = (scr1 & 0x2000) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 227         }
 228
 229         if (!noautodma)
 230                 hwif->autodma = 1;
 231         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 232 }
 233
 234 static unsigned int __devinit init_chipset_tc86c001(struct pci_dev *dev,
 235                                                         const char *name)
 236 {
 237         int err = pci_request_region(dev, 5, name);
 238
 239         if (err)
 240                 printk(KERN_ERR "%s: system control regs already in use", name);
 241         return err;
 242 }
 243
 244 static ide_pci_device_t tc86c001_chipset __devinitdata = {
 245         .name           = "TC86C001",
 246         .init_chipset   = init_chipset_tc86c001,
 247         .init_hwif      = init_hwif_tc86c001,
 248         .autodma        = AUTODMA,
 249         .bootable       = OFF_BOARD,
 250         .host_flags     = IDE_HFLAG_SINGLE,
 251         .pio_mask       = ATA_PIO4,
 252 };
 253
 254 static int __devinit tc86c001_init_one(struct pci_dev *dev,
 255                                        const struct pci_device_id *id)
 256 {
 257         return ide_setup_pci_device(dev, &tc86c001_chipset);
 258 }
 259
 260 static struct pci_device_id tc86c001_pci_tbl[] = {
 261         { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
 262           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 263         { 0, }
 264 };
 265 MODULE_DEVICE_TABLE(pci, tc86c001_pci_tbl);
 266
 267 static struct pci_driver driver = {
 268         .name           = "TC86C001",
 269         .id_table       = tc86c001_pci_tbl,
 270         .probe          = tc86c001_init_one
 271 };
 272
 273 static int __init tc86c001_ide_init(void)
 274 {
 275         return ide_pci_register_driver(&driver);
 276 }
 277 module_init(tc86c001_ide_init);
 278
 279 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
 280 MODULE_DESCRIPTION("PCI driver module for TC86C001 IDE");
 281 MODULE_LICENSE("GPL");