ide: delete filenames/versions from comments
[deliverable/linux.git] / drivers / ide / pci / via82cxxx.c
1 /*
2 * VIA IDE driver for Linux. Supported southbridges:
3 *
4 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
5 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
6 * vt8235, vt8237, vt8237a
7 *
8 * Copyright (c) 2000-2002 Vojtech Pavlik
9 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
10 *
11 * Based on the work of:
12 * Michel Aubry
13 * Jeff Garzik
14 * Andre Hedrick
15 *
16 * Documentation:
17 * Obsolete device documentation publically available from via.com.tw
18 * Current device documentation available under NDA only
19 */
20
21 /*
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License version 2 as published by
24 * the Free Software Foundation.
25 */
26
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/ioport.h>
30 #include <linux/blkdev.h>
31 #include <linux/pci.h>
32 #include <linux/init.h>
33 #include <linux/ide.h>
34 #include <linux/dmi.h>
35
36 #include <asm/io.h>
37
38 #ifdef CONFIG_PPC_CHRP
39 #include <asm/processor.h>
40 #endif
41
42 #include "ide-timing.h"
43
44 #define VIA_IDE_ENABLE 0x40
45 #define VIA_IDE_CONFIG 0x41
46 #define VIA_FIFO_CONFIG 0x43
47 #define VIA_MISC_1 0x44
48 #define VIA_MISC_2 0x45
49 #define VIA_MISC_3 0x46
50 #define VIA_DRIVE_TIMING 0x48
51 #define VIA_8BIT_TIMING 0x4e
52 #define VIA_ADDRESS_SETUP 0x4c
53 #define VIA_UDMA_TIMING 0x50
54
55 #define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
56 #define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
57 #define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
58 #define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
59 #define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
60 #define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
61
62 /*
63 * VIA SouthBridge chips.
64 */
65
66 static struct via_isa_bridge {
67 char *name;
68 u16 id;
69 u8 rev_min;
70 u8 rev_max;
71 u8 udma_mask;
72 u8 flags;
73 } via_isa_bridges[] = {
74 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
75 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
76 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
77 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
78 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
79 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
80 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
81 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
82 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
83 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
84 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
85 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
86 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
87 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
88 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
89 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
90 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
91 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
92 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
93 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
94 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
95 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
96 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
97 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
98 { NULL }
99 };
100
101 static unsigned int via_clock;
102 static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
103
104 struct via82cxxx_dev
105 {
106 struct via_isa_bridge *via_config;
107 unsigned int via_80w;
108 };
109
110 /**
111 * via_set_speed - write timing registers
112 * @dev: PCI device
113 * @dn: device
114 * @timing: IDE timing data to use
115 *
116 * via_set_speed writes timing values to the chipset registers
117 */
118
119 static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
120 {
121 struct pci_dev *dev = to_pci_dev(hwif->dev);
122 struct via82cxxx_dev *vdev = pci_get_drvdata(dev);
123 u8 t;
124
125 if (~vdev->via_config->flags & VIA_BAD_AST) {
126 pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
127 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
128 pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
129 }
130
131 pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
132 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
133
134 pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
135 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
136
137 switch (vdev->via_config->udma_mask) {
138 case ATA_UDMA2: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
139 case ATA_UDMA4: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
140 case ATA_UDMA5: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
141 case ATA_UDMA6: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
142 default: return;
143 }
144
145 pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
146 }
147
148 /**
149 * via_set_drive - configure transfer mode
150 * @drive: Drive to set up
151 * @speed: desired speed
152 *
153 * via_set_drive() computes timing values configures the chipset to
154 * a desired transfer mode. It also can be called by upper layers.
155 */
156
157 static void via_set_drive(ide_drive_t *drive, const u8 speed)
158 {
159 ide_hwif_t *hwif = drive->hwif;
160 ide_drive_t *peer = hwif->drives + (~drive->dn & 1);
161 struct pci_dev *dev = to_pci_dev(hwif->dev);
162 struct via82cxxx_dev *vdev = pci_get_drvdata(dev);
163 struct ide_timing t, p;
164 unsigned int T, UT;
165
166 T = 1000000000 / via_clock;
167
168 switch (vdev->via_config->udma_mask) {
169 case ATA_UDMA2: UT = T; break;
170 case ATA_UDMA4: UT = T/2; break;
171 case ATA_UDMA5: UT = T/3; break;
172 case ATA_UDMA6: UT = T/4; break;
173 default: UT = T;
174 }
175
176 ide_timing_compute(drive, speed, &t, T, UT);
177
178 if (peer->present) {
179 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
180 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
181 }
182
183 via_set_speed(HWIF(drive), drive->dn, &t);
184 }
185
186 /**
187 * via_set_pio_mode - set host controller for PIO mode
188 * @drive: drive
189 * @pio: PIO mode number
190 *
191 * A callback from the upper layers for PIO-only tuning.
192 */
193
194 static void via_set_pio_mode(ide_drive_t *drive, const u8 pio)
195 {
196 via_set_drive(drive, XFER_PIO_0 + pio);
197 }
198
199 static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
200 {
201 struct via_isa_bridge *via_config;
202
203 for (via_config = via_isa_bridges; via_config->id; via_config++)
204 if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
205 !!(via_config->flags & VIA_BAD_ID),
206 via_config->id, NULL))) {
207
208 if ((*isa)->revision >= via_config->rev_min &&
209 (*isa)->revision <= via_config->rev_max)
210 break;
211 pci_dev_put(*isa);
212 }
213
214 return via_config;
215 }
216
217 /*
218 * Check and handle 80-wire cable presence
219 */
220 static void __devinit via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
221 {
222 int i;
223
224 switch (vdev->via_config->udma_mask) {
225 case ATA_UDMA4:
226 for (i = 24; i >= 0; i -= 8)
227 if (((u >> (i & 16)) & 8) &&
228 ((u >> i) & 0x20) &&
229 (((u >> i) & 7) < 2)) {
230 /*
231 * 2x PCI clock and
232 * UDMA w/ < 3T/cycle
233 */
234 vdev->via_80w |= (1 << (1 - (i >> 4)));
235 }
236 break;
237
238 case ATA_UDMA5:
239 for (i = 24; i >= 0; i -= 8)
240 if (((u >> i) & 0x10) ||
241 (((u >> i) & 0x20) &&
242 (((u >> i) & 7) < 4))) {
243 /* BIOS 80-wire bit or
244 * UDMA w/ < 60ns/cycle
245 */
246 vdev->via_80w |= (1 << (1 - (i >> 4)));
247 }
248 break;
249
250 case ATA_UDMA6:
251 for (i = 24; i >= 0; i -= 8)
252 if (((u >> i) & 0x10) ||
253 (((u >> i) & 0x20) &&
254 (((u >> i) & 7) < 6))) {
255 /* BIOS 80-wire bit or
256 * UDMA w/ < 60ns/cycle
257 */
258 vdev->via_80w |= (1 << (1 - (i >> 4)));
259 }
260 break;
261 }
262 }
263
264 /**
265 * init_chipset_via82cxxx - initialization handler
266 * @dev: PCI device
267 * @name: Name of interface
268 *
269 * The initialization callback. Here we determine the IDE chip type
270 * and initialize its drive independent registers.
271 */
272
273 static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
274 {
275 struct pci_dev *isa = NULL;
276 struct via82cxxx_dev *vdev;
277 struct via_isa_bridge *via_config;
278 u8 t, v;
279 u32 u;
280
281 vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
282 if (!vdev) {
283 printk(KERN_ERR "VP_IDE: out of memory :(\n");
284 return -ENOMEM;
285 }
286 pci_set_drvdata(dev, vdev);
287
288 /*
289 * Find the ISA bridge to see how good the IDE is.
290 */
291 vdev->via_config = via_config = via_config_find(&isa);
292
293 /* We checked this earlier so if it fails here deeep badness
294 is involved */
295
296 BUG_ON(!via_config->id);
297
298 /*
299 * Detect cable and configure Clk66
300 */
301 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
302
303 via_cable_detect(vdev, u);
304
305 if (via_config->udma_mask == ATA_UDMA4) {
306 /* Enable Clk66 */
307 pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
308 } else if (via_config->flags & VIA_BAD_CLK66) {
309 /* Would cause trouble on 596a and 686 */
310 pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
311 }
312
313 /*
314 * Check whether interfaces are enabled.
315 */
316
317 pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
318
319 /*
320 * Set up FIFO sizes and thresholds.
321 */
322
323 pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
324
325 /* Disable PREQ# till DDACK# */
326 if (via_config->flags & VIA_BAD_PREQ) {
327 /* Would crash on 586b rev 41 */
328 t &= 0x7f;
329 }
330
331 /* Fix FIFO split between channels */
332 if (via_config->flags & VIA_SET_FIFO) {
333 t &= (t & 0x9f);
334 switch (v & 3) {
335 case 2: t |= 0x00; break; /* 16 on primary */
336 case 1: t |= 0x60; break; /* 16 on secondary */
337 case 3: t |= 0x20; break; /* 8 pri 8 sec */
338 }
339 }
340
341 pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
342
343 /*
344 * Determine system bus clock.
345 */
346
347 via_clock = system_bus_clock() * 1000;
348
349 switch (via_clock) {
350 case 33000: via_clock = 33333; break;
351 case 37000: via_clock = 37500; break;
352 case 41000: via_clock = 41666; break;
353 }
354
355 if (via_clock < 20000 || via_clock > 50000) {
356 printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
357 "impossible (%d), using 33 MHz instead.\n", via_clock);
358 printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
359 "to assume 80-wire cable.\n");
360 via_clock = 33333;
361 }
362
363 /*
364 * Print the boot message.
365 */
366
367 printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %sDMA%s "
368 "controller on pci%s\n",
369 via_config->name, isa->revision,
370 via_config->udma_mask ? "U" : "MW",
371 via_dma[via_config->udma_mask ?
372 (fls(via_config->udma_mask) - 1) : 0],
373 pci_name(dev));
374
375 pci_dev_put(isa);
376 return 0;
377 }
378
379 /*
380 * Cable special cases
381 */
382
383 static const struct dmi_system_id cable_dmi_table[] = {
384 {
385 .ident = "Acer Ferrari 3400",
386 .matches = {
387 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
388 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
389 },
390 },
391 { }
392 };
393
394 static int via_cable_override(struct pci_dev *pdev)
395 {
396 /* Systems by DMI */
397 if (dmi_check_system(cable_dmi_table))
398 return 1;
399
400 /* Arima W730-K8/Targa Visionary 811/... */
401 if (pdev->subsystem_vendor == 0x161F &&
402 pdev->subsystem_device == 0x2032)
403 return 1;
404
405 return 0;
406 }
407
408 static u8 __devinit via82cxxx_cable_detect(ide_hwif_t *hwif)
409 {
410 struct pci_dev *pdev = to_pci_dev(hwif->dev);
411 struct via82cxxx_dev *vdev = pci_get_drvdata(pdev);
412
413 if (via_cable_override(pdev))
414 return ATA_CBL_PATA40_SHORT;
415
416 if ((vdev->via_80w >> hwif->channel) & 1)
417 return ATA_CBL_PATA80;
418 else
419 return ATA_CBL_PATA40;
420 }
421
422 static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
423 {
424 hwif->set_pio_mode = &via_set_pio_mode;
425 hwif->set_dma_mode = &via_set_drive;
426
427 if (!hwif->dma_base)
428 return;
429
430 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
431 hwif->cbl = via82cxxx_cable_detect(hwif);
432 }
433
434 static const struct ide_port_info via82cxxx_chipset __devinitdata = {
435 .name = "VP_IDE",
436 .init_chipset = init_chipset_via82cxxx,
437 .init_hwif = init_hwif_via82cxxx,
438 .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
439 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST |
440 IDE_HFLAG_PIO_NO_DOWNGRADE |
441 IDE_HFLAG_ABUSE_SET_DMA_MODE |
442 IDE_HFLAG_POST_SET_MODE |
443 IDE_HFLAG_IO_32BIT |
444 IDE_HFLAG_BOOTABLE,
445 .pio_mask = ATA_PIO5,
446 .swdma_mask = ATA_SWDMA2,
447 .mwdma_mask = ATA_MWDMA2,
448 };
449
450 static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
451 {
452 struct pci_dev *isa = NULL;
453 struct via_isa_bridge *via_config;
454 u8 idx = id->driver_data;
455 struct ide_port_info d;
456
457 d = via82cxxx_chipset;
458
459 /*
460 * Find the ISA bridge and check we know what it is.
461 */
462 via_config = via_config_find(&isa);
463 pci_dev_put(isa);
464 if (!via_config->id) {
465 printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
466 return -ENODEV;
467 }
468
469 if (idx == 0)
470 d.host_flags |= IDE_HFLAG_NO_AUTODMA;
471 else
472 d.enablebits[1].reg = d.enablebits[0].reg = 0;
473
474 if ((via_config->flags & VIA_NO_UNMASK) == 0)
475 d.host_flags |= IDE_HFLAG_UNMASK_IRQS;
476
477 #ifdef CONFIG_PPC_CHRP
478 if (machine_is(chrp) && _chrp_type == _CHRP_Pegasos)
479 d.host_flags |= IDE_HFLAG_FORCE_LEGACY_IRQS;
480 #endif
481
482 d.udma_mask = via_config->udma_mask;
483
484 return ide_setup_pci_device(dev, &d);
485 }
486
487 static const struct pci_device_id via_pci_tbl[] = {
488 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 },
489 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 },
490 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 },
491 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
492 { 0, },
493 };
494 MODULE_DEVICE_TABLE(pci, via_pci_tbl);
495
496 static struct pci_driver driver = {
497 .name = "VIA_IDE",
498 .id_table = via_pci_tbl,
499 .probe = via_init_one,
500 };
501
502 static int __init via_ide_init(void)
503 {
504 return ide_pci_register_driver(&driver);
505 }
506
507 module_init(via_ide_init);
508
509 MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
510 MODULE_DESCRIPTION("PCI driver module for VIA IDE");
511 MODULE_LICENSE("GPL");
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