2 * linux/drivers/ide/ppc/pmac.c
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
15 * Some code taken from drivers/ide/ide-dma.c:
17 * Copyright (c) 1995-1998 Mark Lord
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/pci.h>
33 #include <linux/adb.h>
34 #include <linux/pmu.h>
35 #include <linux/scatterlist.h>
39 #include <asm/dbdma.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/machdep.h>
43 #include <asm/pmac_feature.h>
44 #include <asm/sections.h>
48 #include <asm/mediabay.h>
51 #include "../ide-timing.h"
55 #define DMA_WAIT_TIMEOUT 50
57 typedef struct pmac_ide_hwif
{
58 unsigned long regbase
;
62 unsigned cable_80
: 1;
63 unsigned mediabay
: 1;
64 unsigned broken_dma
: 1;
65 unsigned broken_dma_warn
: 1;
66 struct device_node
* node
;
67 struct macio_dev
*mdev
;
69 volatile u32 __iomem
* *kauai_fcr
;
70 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
71 /* Those fields are duplicating what is in hwif. We currently
72 * can't use the hwif ones because of some assumptions that are
73 * beeing done by the generic code about the kind of dma controller
74 * and format of the dma table. This will have to be fixed though.
76 volatile struct dbdma_regs __iomem
* dma_regs
;
77 struct dbdma_cmd
* dma_table_cpu
;
82 static pmac_ide_hwif_t pmac_ide
[MAX_HWIFS
];
83 static int pmac_ide_count
;
86 controller_ohare
, /* OHare based */
87 controller_heathrow
, /* Heathrow/Paddington */
88 controller_kl_ata3
, /* KeyLargo ATA-3 */
89 controller_kl_ata4
, /* KeyLargo ATA-4 */
90 controller_un_ata6
, /* UniNorth2 ATA-6 */
91 controller_k2_ata6
, /* K2 ATA-6 */
92 controller_sh_ata6
, /* Shasta ATA-6 */
95 static const char* model_name
[] = {
96 "OHare ATA", /* OHare based */
97 "Heathrow ATA", /* Heathrow/Paddington */
98 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
99 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
100 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
101 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
102 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
106 * Extra registers, both 32-bit little-endian
108 #define IDE_TIMING_CONFIG 0x200
109 #define IDE_INTERRUPT 0x300
111 /* Kauai (U2) ATA has different register setup */
112 #define IDE_KAUAI_PIO_CONFIG 0x200
113 #define IDE_KAUAI_ULTRA_CONFIG 0x210
114 #define IDE_KAUAI_POLL_CONFIG 0x220
117 * Timing configuration register definitions
120 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
121 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
122 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
123 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
124 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
126 /* 133Mhz cell, found in shasta.
127 * See comments about 100 Mhz Uninorth 2...
128 * Note that PIO_MASK and MDMA_MASK seem to overlap
130 #define TR_133_PIOREG_PIO_MASK 0xff000fff
131 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
132 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
133 #define TR_133_UDMAREG_UDMA_EN 0x00000001
135 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
136 * this one yet, it appears as a pci device (106b/0033) on uninorth
137 * internal PCI bus and it's clock is controlled like gem or fw. It
138 * appears to be an evolution of keylargo ATA4 with a timing register
139 * extended to 2 32bits registers and a similar DBDMA channel. Other
140 * registers seem to exist but I can't tell much about them.
142 * So far, I'm using pre-calculated tables for this extracted from
143 * the values used by the MacOS X driver.
145 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
146 * register controls the UDMA timings. At least, it seems bit 0
147 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
148 * cycle time in units of 10ns. Bits 8..15 are used by I don't
149 * know their meaning yet
151 #define TR_100_PIOREG_PIO_MASK 0xff000fff
152 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
153 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
154 #define TR_100_UDMAREG_UDMA_EN 0x00000001
157 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
158 * 40 connector cable and to 4 on 80 connector one.
159 * Clock unit is 15ns (66Mhz)
161 * 3 Values can be programmed:
162 * - Write data setup, which appears to match the cycle time. They
163 * also call it DIOW setup.
164 * - Ready to pause time (from spec)
165 * - Address setup. That one is weird. I don't see where exactly
166 * it fits in UDMA cycles, I got it's name from an obscure piece
167 * of commented out code in Darwin. They leave it to 0, we do as
168 * well, despite a comment that would lead to think it has a
170 * Apple also add 60ns to the write data setup (or cycle time ?) on
173 #define TR_66_UDMA_MASK 0xfff00000
174 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
175 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
176 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
177 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
178 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
179 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
180 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
181 #define TR_66_MDMA_MASK 0x000ffc00
182 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
183 #define TR_66_MDMA_RECOVERY_SHIFT 15
184 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
185 #define TR_66_MDMA_ACCESS_SHIFT 10
186 #define TR_66_PIO_MASK 0x000003ff
187 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
188 #define TR_66_PIO_RECOVERY_SHIFT 5
189 #define TR_66_PIO_ACCESS_MASK 0x0000001f
190 #define TR_66_PIO_ACCESS_SHIFT 0
192 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
193 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
195 * The access time and recovery time can be programmed. Some older
196 * Darwin code base limit OHare to 150ns cycle time. I decided to do
197 * the same here fore safety against broken old hardware ;)
198 * The HalfTick bit, when set, adds half a clock (15ns) to the access
199 * time and removes one from recovery. It's not supported on KeyLargo
200 * implementation afaik. The E bit appears to be set for PIO mode 0 and
201 * is used to reach long timings used in this mode.
203 #define TR_33_MDMA_MASK 0x003ff800
204 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
205 #define TR_33_MDMA_RECOVERY_SHIFT 16
206 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
207 #define TR_33_MDMA_ACCESS_SHIFT 11
208 #define TR_33_MDMA_HALFTICK 0x00200000
209 #define TR_33_PIO_MASK 0x000007ff
210 #define TR_33_PIO_E 0x00000400
211 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
212 #define TR_33_PIO_RECOVERY_SHIFT 5
213 #define TR_33_PIO_ACCESS_MASK 0x0000001f
214 #define TR_33_PIO_ACCESS_SHIFT 0
217 * Interrupt register definitions
219 #define IDE_INTR_DMA 0x80000000
220 #define IDE_INTR_DEVICE 0x40000000
223 * FCR Register on Kauai. Not sure what bit 0x4 is ...
225 #define KAUAI_FCR_UATA_MAGIC 0x00000004
226 #define KAUAI_FCR_UATA_RESET_N 0x00000002
227 #define KAUAI_FCR_UATA_ENABLE 0x00000001
229 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
231 /* Rounded Multiword DMA timings
233 * I gave up finding a generic formula for all controller
234 * types and instead, built tables based on timing values
235 * used by Apple in Darwin's implementation.
237 struct mdma_timings_t
{
243 struct mdma_timings_t mdma_timings_33
[] =
256 struct mdma_timings_t mdma_timings_33k
[] =
269 struct mdma_timings_t mdma_timings_66
[] =
282 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
284 int addrSetup
; /* ??? */
287 } kl66_udma_timings
[] =
289 { 0, 180, 120 }, /* Mode 0 */
290 { 0, 150, 90 }, /* 1 */
291 { 0, 120, 60 }, /* 2 */
292 { 0, 90, 45 }, /* 3 */
293 { 0, 90, 30 } /* 4 */
296 /* UniNorth 2 ATA/100 timings */
297 struct kauai_timing
{
302 static struct kauai_timing kauai_pio_timings
[] =
304 { 930 , 0x08000fff },
305 { 600 , 0x08000a92 },
306 { 383 , 0x0800060f },
307 { 360 , 0x08000492 },
308 { 330 , 0x0800048f },
309 { 300 , 0x080003cf },
310 { 270 , 0x080003cc },
311 { 240 , 0x0800038b },
312 { 239 , 0x0800030c },
313 { 180 , 0x05000249 },
317 static struct kauai_timing kauai_mdma_timings
[] =
319 { 1260 , 0x00fff000 },
320 { 480 , 0x00618000 },
321 { 360 , 0x00492000 },
322 { 270 , 0x0038e000 },
323 { 240 , 0x0030c000 },
324 { 210 , 0x002cb000 },
325 { 180 , 0x00249000 },
326 { 150 , 0x00209000 },
327 { 120 , 0x00148000 },
331 static struct kauai_timing kauai_udma_timings
[] =
333 { 120 , 0x000070c0 },
342 static struct kauai_timing shasta_pio_timings
[] =
344 { 930 , 0x08000fff },
345 { 600 , 0x0A000c97 },
346 { 383 , 0x07000712 },
347 { 360 , 0x040003cd },
348 { 330 , 0x040003cd },
349 { 300 , 0x040003cd },
350 { 270 , 0x040003cd },
351 { 240 , 0x040003cd },
352 { 239 , 0x040003cd },
353 { 180 , 0x0400028b },
357 static struct kauai_timing shasta_mdma_timings
[] =
359 { 1260 , 0x00fff000 },
360 { 480 , 0x00820800 },
361 { 360 , 0x00820800 },
362 { 270 , 0x00820800 },
363 { 240 , 0x00820800 },
364 { 210 , 0x00820800 },
365 { 180 , 0x00820800 },
366 { 150 , 0x0028b000 },
367 { 120 , 0x001ca000 },
371 static struct kauai_timing shasta_udma133_timings
[] =
373 { 120 , 0x00035901, },
374 { 90 , 0x000348b1, },
375 { 60 , 0x00033881, },
376 { 45 , 0x00033861, },
377 { 30 , 0x00033841, },
378 { 20 , 0x00033031, },
379 { 15 , 0x00033021, },
385 kauai_lookup_timing(struct kauai_timing
* table
, int cycle_time
)
389 for (i
=0; table
[i
].cycle_time
; i
++)
390 if (cycle_time
> table
[i
+1].cycle_time
)
391 return table
[i
].timing_reg
;
395 /* allow up to 256 DBDMA commands per xfer */
396 #define MAX_DCMDS 256
399 * Wait 1s for disk to answer on IDE bus after a hard reset
400 * of the device (via GPIO/FCR).
402 * Some devices seem to "pollute" the bus even after dropping
403 * the BSY bit (typically some combo drives slave on the UDMA
404 * bus) after a hard reset. Since we hard reset all drives on
405 * KeyLargo ATA66, we have to keep that delay around. I may end
406 * up not hard resetting anymore on these and keep the delay only
407 * for older interfaces instead (we have to reset when coming
408 * from MacOS...) --BenH.
410 #define IDE_WAKEUP_DELAY (1*HZ)
412 static void pmac_ide_setup_dma(pmac_ide_hwif_t
*pmif
, ide_hwif_t
*hwif
);
413 static int pmac_ide_build_dmatable(ide_drive_t
*drive
, struct request
*rq
);
414 static void pmac_ide_selectproc(ide_drive_t
*drive
);
415 static void pmac_ide_kauai_selectproc(ide_drive_t
*drive
);
417 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
420 * N.B. this can't be an initfunc, because the media-bay task can
421 * call ide_[un]register at any time.
424 pmac_ide_init_hwif_ports(hw_regs_t
*hw
,
425 unsigned long data_port
, unsigned long ctrl_port
,
433 for (ix
= 0; ix
< MAX_HWIFS
; ++ix
)
434 if (data_port
== pmac_ide
[ix
].regbase
)
437 if (ix
>= MAX_HWIFS
) {
438 /* Probably a PCI interface... */
439 for (i
= IDE_DATA_OFFSET
; i
<= IDE_STATUS_OFFSET
; ++i
)
440 hw
->io_ports
[i
] = data_port
+ i
- IDE_DATA_OFFSET
;
441 hw
->io_ports
[IDE_CONTROL_OFFSET
] = ctrl_port
;
445 for (i
= 0; i
< 8; ++i
)
446 hw
->io_ports
[i
] = data_port
+ i
* 0x10;
447 hw
->io_ports
[8] = data_port
+ 0x160;
450 *irq
= pmac_ide
[ix
].irq
;
452 hw
->dev
= &pmac_ide
[ix
].mdev
->ofdev
.dev
;
455 #define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
458 * Apply the timings of the proper unit (master/slave) to the shared
459 * timing register when selecting that unit. This version is for
460 * ASICs with a single timing register
463 pmac_ide_selectproc(ide_drive_t
*drive
)
465 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
470 if (drive
->select
.b
.unit
& 0x01)
471 writel(pmif
->timings
[1], PMAC_IDE_REG(IDE_TIMING_CONFIG
));
473 writel(pmif
->timings
[0], PMAC_IDE_REG(IDE_TIMING_CONFIG
));
474 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
478 * Apply the timings of the proper unit (master/slave) to the shared
479 * timing register when selecting that unit. This version is for
480 * ASICs with a dual timing register (Kauai)
483 pmac_ide_kauai_selectproc(ide_drive_t
*drive
)
485 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
490 if (drive
->select
.b
.unit
& 0x01) {
491 writel(pmif
->timings
[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
492 writel(pmif
->timings
[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG
));
494 writel(pmif
->timings
[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
495 writel(pmif
->timings
[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG
));
497 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
501 * Force an update of controller timing values for a given drive
504 pmac_ide_do_update_timings(ide_drive_t
*drive
)
506 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
511 if (pmif
->kind
== controller_sh_ata6
||
512 pmif
->kind
== controller_un_ata6
||
513 pmif
->kind
== controller_k2_ata6
)
514 pmac_ide_kauai_selectproc(drive
);
516 pmac_ide_selectproc(drive
);
520 pmac_outbsync(ide_drive_t
*drive
, u8 value
, unsigned long port
)
524 writeb(value
, (void __iomem
*) port
);
525 tmp
= readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
529 * Send the SET_FEATURE IDE command to the drive and update drive->id with
530 * the new state. We currently don't use the generic routine as it used to
531 * cause various trouble, especially with older mediabays.
532 * This code is sometimes triggering a spurrious interrupt though, I need
533 * to sort that out sooner or later and see if I can finally get the
534 * common version to work properly in all cases
537 pmac_ide_do_setfeature(ide_drive_t
*drive
, u8 command
)
539 ide_hwif_t
*hwif
= HWIF(drive
);
542 disable_irq_nosync(hwif
->irq
);
545 SELECT_MASK(drive
, 0);
547 /* Get rid of pending error state */
548 (void) hwif
->INB(IDE_STATUS_REG
);
549 /* Timeout bumped for some powerbooks */
550 if (wait_for_ready(drive
, 2000)) {
551 /* Timeout bumped for some powerbooks */
552 printk(KERN_ERR
"%s: pmac_ide_do_setfeature disk not ready "
553 "before SET_FEATURE!\n", drive
->name
);
557 hwif
->OUTB(drive
->ctl
| 2, IDE_CONTROL_REG
);
558 hwif
->OUTB(command
, IDE_NSECTOR_REG
);
559 hwif
->OUTB(SETFEATURES_XFER
, IDE_FEATURE_REG
);
560 hwif
->OUTBSYNC(drive
, WIN_SETFEATURES
, IDE_COMMAND_REG
);
562 /* Timeout bumped for some powerbooks */
563 result
= wait_for_ready(drive
, 2000);
564 hwif
->OUTB(drive
->ctl
, IDE_CONTROL_REG
);
566 printk(KERN_ERR
"%s: pmac_ide_do_setfeature disk not ready "
567 "after SET_FEATURE !\n", drive
->name
);
569 SELECT_MASK(drive
, 0);
571 drive
->id
->dma_ultra
&= ~0xFF00;
572 drive
->id
->dma_mword
&= ~0x0F00;
573 drive
->id
->dma_1word
&= ~0x0F00;
576 drive
->id
->dma_ultra
|= 0x8080; break;
578 drive
->id
->dma_ultra
|= 0x4040; break;
580 drive
->id
->dma_ultra
|= 0x2020; break;
582 drive
->id
->dma_ultra
|= 0x1010; break;
584 drive
->id
->dma_ultra
|= 0x0808; break;
586 drive
->id
->dma_ultra
|= 0x0404; break;
588 drive
->id
->dma_ultra
|= 0x0202; break;
590 drive
->id
->dma_ultra
|= 0x0101; break;
592 drive
->id
->dma_mword
|= 0x0404; break;
594 drive
->id
->dma_mword
|= 0x0202; break;
596 drive
->id
->dma_mword
|= 0x0101; break;
598 drive
->id
->dma_1word
|= 0x0404; break;
600 drive
->id
->dma_1word
|= 0x0202; break;
602 drive
->id
->dma_1word
|= 0x0101; break;
605 if (!drive
->init_speed
)
606 drive
->init_speed
= command
;
607 drive
->current_speed
= command
;
609 enable_irq(hwif
->irq
);
614 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
617 pmac_ide_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
620 unsigned accessTicks
, recTicks
;
621 unsigned accessTime
, recTime
;
622 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
623 unsigned int cycle_time
;
628 /* which drive is it ? */
629 timings
= &pmif
->timings
[drive
->select
.b
.unit
& 0x01];
631 cycle_time
= ide_pio_cycle_time(drive
, pio
);
633 switch (pmif
->kind
) {
634 case controller_sh_ata6
: {
636 u32 tr
= kauai_lookup_timing(shasta_pio_timings
, cycle_time
);
639 *timings
= ((*timings
) & ~TR_133_PIOREG_PIO_MASK
) | tr
;
642 case controller_un_ata6
:
643 case controller_k2_ata6
: {
645 u32 tr
= kauai_lookup_timing(kauai_pio_timings
, cycle_time
);
648 *timings
= ((*timings
) & ~TR_100_PIOREG_PIO_MASK
) | tr
;
651 case controller_kl_ata4
:
653 recTime
= cycle_time
- ide_pio_timings
[pio
].active_time
654 - ide_pio_timings
[pio
].setup_time
;
655 recTime
= max(recTime
, 150U);
656 accessTime
= ide_pio_timings
[pio
].active_time
;
657 accessTime
= max(accessTime
, 150U);
658 accessTicks
= SYSCLK_TICKS_66(accessTime
);
659 accessTicks
= min(accessTicks
, 0x1fU
);
660 recTicks
= SYSCLK_TICKS_66(recTime
);
661 recTicks
= min(recTicks
, 0x1fU
);
662 *timings
= ((*timings
) & ~TR_66_PIO_MASK
) |
663 (accessTicks
<< TR_66_PIO_ACCESS_SHIFT
) |
664 (recTicks
<< TR_66_PIO_RECOVERY_SHIFT
);
669 recTime
= cycle_time
- ide_pio_timings
[pio
].active_time
670 - ide_pio_timings
[pio
].setup_time
;
671 recTime
= max(recTime
, 150U);
672 accessTime
= ide_pio_timings
[pio
].active_time
;
673 accessTime
= max(accessTime
, 150U);
674 accessTicks
= SYSCLK_TICKS(accessTime
);
675 accessTicks
= min(accessTicks
, 0x1fU
);
676 accessTicks
= max(accessTicks
, 4U);
677 recTicks
= SYSCLK_TICKS(recTime
);
678 recTicks
= min(recTicks
, 0x1fU
);
679 recTicks
= max(recTicks
, 5U) - 4;
681 recTicks
--; /* guess, but it's only for PIO0, so... */
684 *timings
= ((*timings
) & ~TR_33_PIO_MASK
) |
685 (accessTicks
<< TR_33_PIO_ACCESS_SHIFT
) |
686 (recTicks
<< TR_33_PIO_RECOVERY_SHIFT
);
688 *timings
|= TR_33_PIO_E
;
693 #ifdef IDE_PMAC_DEBUG
694 printk(KERN_ERR
"%s: Set PIO timing for mode %d, reg: 0x%08x\n",
695 drive
->name
, pio
, *timings
);
698 if (drive
->select
.all
== HWIF(drive
)->INB(IDE_SELECT_REG
))
699 pmac_ide_do_update_timings(drive
);
702 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
705 * Calculate KeyLargo ATA/66 UDMA timings
708 set_timings_udma_ata4(u32
*timings
, u8 speed
)
710 unsigned rdyToPauseTicks
, wrDataSetupTicks
, addrTicks
;
712 if (speed
> XFER_UDMA_4
)
715 rdyToPauseTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].rdy2pause
);
716 wrDataSetupTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].wrDataSetup
);
717 addrTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].addrSetup
);
719 *timings
= ((*timings
) & ~(TR_66_UDMA_MASK
| TR_66_MDMA_MASK
)) |
720 (wrDataSetupTicks
<< TR_66_UDMA_WRDATASETUP_SHIFT
) |
721 (rdyToPauseTicks
<< TR_66_UDMA_RDY2PAUS_SHIFT
) |
722 (addrTicks
<<TR_66_UDMA_ADDRSETUP_SHIFT
) |
724 #ifdef IDE_PMAC_DEBUG
725 printk(KERN_ERR
"ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
726 speed
& 0xf, *timings
);
733 * Calculate Kauai ATA/100 UDMA timings
736 set_timings_udma_ata6(u32
*pio_timings
, u32
*ultra_timings
, u8 speed
)
738 struct ide_timing
*t
= ide_timing_find_mode(speed
);
741 if (speed
> XFER_UDMA_5
|| t
== NULL
)
743 tr
= kauai_lookup_timing(kauai_udma_timings
, (int)t
->udma
);
746 *ultra_timings
= ((*ultra_timings
) & ~TR_100_UDMAREG_UDMA_MASK
) | tr
;
747 *ultra_timings
= (*ultra_timings
) | TR_100_UDMAREG_UDMA_EN
;
753 * Calculate Shasta ATA/133 UDMA timings
756 set_timings_udma_shasta(u32
*pio_timings
, u32
*ultra_timings
, u8 speed
)
758 struct ide_timing
*t
= ide_timing_find_mode(speed
);
761 if (speed
> XFER_UDMA_6
|| t
== NULL
)
763 tr
= kauai_lookup_timing(shasta_udma133_timings
, (int)t
->udma
);
766 *ultra_timings
= ((*ultra_timings
) & ~TR_133_UDMAREG_UDMA_MASK
) | tr
;
767 *ultra_timings
= (*ultra_timings
) | TR_133_UDMAREG_UDMA_EN
;
773 * Calculate MDMA timings for all cells
776 set_timings_mdma(ide_drive_t
*drive
, int intf_type
, u32
*timings
, u32
*timings2
,
777 u8 speed
, int drive_cycle_time
)
779 int cycleTime
, accessTime
= 0, recTime
= 0;
780 unsigned accessTicks
, recTicks
;
781 struct mdma_timings_t
* tm
= NULL
;
784 /* Get default cycle time for mode */
785 switch(speed
& 0xf) {
786 case 0: cycleTime
= 480; break;
787 case 1: cycleTime
= 150; break;
788 case 2: cycleTime
= 120; break;
792 /* Adjust for drive */
793 if (drive_cycle_time
&& drive_cycle_time
> cycleTime
)
794 cycleTime
= drive_cycle_time
;
795 /* OHare limits according to some old Apple sources */
796 if ((intf_type
== controller_ohare
) && (cycleTime
< 150))
798 /* Get the proper timing array for this controller */
800 case controller_sh_ata6
:
801 case controller_un_ata6
:
802 case controller_k2_ata6
:
804 case controller_kl_ata4
:
805 tm
= mdma_timings_66
;
807 case controller_kl_ata3
:
808 tm
= mdma_timings_33k
;
811 tm
= mdma_timings_33
;
815 /* Lookup matching access & recovery times */
818 if (tm
[i
+1].cycleTime
< cycleTime
)
824 cycleTime
= tm
[i
].cycleTime
;
825 accessTime
= tm
[i
].accessTime
;
826 recTime
= tm
[i
].recoveryTime
;
828 #ifdef IDE_PMAC_DEBUG
829 printk(KERN_ERR
"%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
830 drive
->name
, cycleTime
, accessTime
, recTime
);
834 case controller_sh_ata6
: {
836 u32 tr
= kauai_lookup_timing(shasta_mdma_timings
, cycleTime
);
839 *timings
= ((*timings
) & ~TR_133_PIOREG_MDMA_MASK
) | tr
;
840 *timings2
= (*timings2
) & ~TR_133_UDMAREG_UDMA_EN
;
842 case controller_un_ata6
:
843 case controller_k2_ata6
: {
845 u32 tr
= kauai_lookup_timing(kauai_mdma_timings
, cycleTime
);
848 *timings
= ((*timings
) & ~TR_100_PIOREG_MDMA_MASK
) | tr
;
849 *timings2
= (*timings2
) & ~TR_100_UDMAREG_UDMA_EN
;
852 case controller_kl_ata4
:
854 accessTicks
= SYSCLK_TICKS_66(accessTime
);
855 accessTicks
= min(accessTicks
, 0x1fU
);
856 accessTicks
= max(accessTicks
, 0x1U
);
857 recTicks
= SYSCLK_TICKS_66(recTime
);
858 recTicks
= min(recTicks
, 0x1fU
);
859 recTicks
= max(recTicks
, 0x3U
);
860 /* Clear out mdma bits and disable udma */
861 *timings
= ((*timings
) & ~(TR_66_MDMA_MASK
| TR_66_UDMA_MASK
)) |
862 (accessTicks
<< TR_66_MDMA_ACCESS_SHIFT
) |
863 (recTicks
<< TR_66_MDMA_RECOVERY_SHIFT
);
865 case controller_kl_ata3
:
866 /* 33Mhz cell on KeyLargo */
867 accessTicks
= SYSCLK_TICKS(accessTime
);
868 accessTicks
= max(accessTicks
, 1U);
869 accessTicks
= min(accessTicks
, 0x1fU
);
870 accessTime
= accessTicks
* IDE_SYSCLK_NS
;
871 recTicks
= SYSCLK_TICKS(recTime
);
872 recTicks
= max(recTicks
, 1U);
873 recTicks
= min(recTicks
, 0x1fU
);
874 *timings
= ((*timings
) & ~TR_33_MDMA_MASK
) |
875 (accessTicks
<< TR_33_MDMA_ACCESS_SHIFT
) |
876 (recTicks
<< TR_33_MDMA_RECOVERY_SHIFT
);
879 /* 33Mhz cell on others */
881 int origAccessTime
= accessTime
;
882 int origRecTime
= recTime
;
884 accessTicks
= SYSCLK_TICKS(accessTime
);
885 accessTicks
= max(accessTicks
, 1U);
886 accessTicks
= min(accessTicks
, 0x1fU
);
887 accessTime
= accessTicks
* IDE_SYSCLK_NS
;
888 recTicks
= SYSCLK_TICKS(recTime
);
889 recTicks
= max(recTicks
, 2U) - 1;
890 recTicks
= min(recTicks
, 0x1fU
);
891 recTime
= (recTicks
+ 1) * IDE_SYSCLK_NS
;
892 if ((accessTicks
> 1) &&
893 ((accessTime
- IDE_SYSCLK_NS
/2) >= origAccessTime
) &&
894 ((recTime
- IDE_SYSCLK_NS
/2) >= origRecTime
)) {
898 *timings
= ((*timings
) & ~TR_33_MDMA_MASK
) |
899 (accessTicks
<< TR_33_MDMA_ACCESS_SHIFT
) |
900 (recTicks
<< TR_33_MDMA_RECOVERY_SHIFT
);
902 *timings
|= TR_33_MDMA_HALFTICK
;
905 #ifdef IDE_PMAC_DEBUG
906 printk(KERN_ERR
"%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
907 drive
->name
, speed
& 0xf, *timings
);
911 #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
914 * Speedproc. This function is called by the core to set any of the standard
915 * timing (PIO, MDMA or UDMA) to both the drive and the controller.
916 * You may notice we don't use this function on normal "dma check" operation,
917 * our dedicated function is more precise as it uses the drive provided
918 * cycle time value. We should probably fix this one to deal with that too...
920 static int pmac_ide_tune_chipset(ide_drive_t
*drive
, const u8 speed
)
922 int unit
= (drive
->select
.b
.unit
& 0x01);
924 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
925 u32
*timings
, *timings2
;
930 timings
= &pmif
->timings
[unit
];
931 timings2
= &pmif
->timings
[unit
+2];
934 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
942 if (pmif
->kind
== controller_kl_ata4
)
943 ret
= set_timings_udma_ata4(timings
, speed
);
944 else if (pmif
->kind
== controller_un_ata6
945 || pmif
->kind
== controller_k2_ata6
)
946 ret
= set_timings_udma_ata6(timings
, timings2
, speed
);
947 else if (pmif
->kind
== controller_sh_ata6
)
948 ret
= set_timings_udma_shasta(timings
, timings2
, speed
);
955 ret
= set_timings_mdma(drive
, pmif
->kind
, timings
, timings2
, speed
, 0);
961 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
967 pmac_ide_set_pio_mode(drive
, speed
& 0x07);
975 ret
= pmac_ide_do_setfeature(drive
, speed
);
979 pmac_ide_do_update_timings(drive
);
985 * Blast some well known "safe" values to the timing registers at init or
986 * wakeup from sleep time, before we do real calculation
989 sanitize_timings(pmac_ide_hwif_t
*pmif
)
991 unsigned int value
, value2
= 0;
994 case controller_sh_ata6
:
998 case controller_un_ata6
:
999 case controller_k2_ata6
:
1001 value2
= 0x00002921;
1003 case controller_kl_ata4
:
1006 case controller_kl_ata3
:
1009 case controller_heathrow
:
1010 case controller_ohare
:
1015 pmif
->timings
[0] = pmif
->timings
[1] = value
;
1016 pmif
->timings
[2] = pmif
->timings
[3] = value2
;
1020 pmac_ide_get_base(int index
)
1022 return pmac_ide
[index
].regbase
;
1026 pmac_ide_check_base(unsigned long base
)
1030 for (ix
= 0; ix
< MAX_HWIFS
; ++ix
)
1031 if (base
== pmac_ide
[ix
].regbase
)
1037 pmac_ide_get_irq(unsigned long base
)
1041 for (ix
= 0; ix
< MAX_HWIFS
; ++ix
)
1042 if (base
== pmac_ide
[ix
].regbase
)
1043 return pmac_ide
[ix
].irq
;
1047 static int ide_majors
[] = { 3, 22, 33, 34, 56, 57 };
1050 pmac_find_ide_boot(char *bootdevice
, int n
)
1055 * Look through the list of IDE interfaces for this one.
1057 for (i
= 0; i
< pmac_ide_count
; ++i
) {
1059 if (!pmac_ide
[i
].node
|| !pmac_ide
[i
].node
->full_name
)
1061 name
= pmac_ide
[i
].node
->full_name
;
1062 if (memcmp(name
, bootdevice
, n
) == 0 && name
[n
] == 0) {
1063 /* XXX should cope with the 2nd drive as well... */
1064 return MKDEV(ide_majors
[i
], 0);
1071 /* Suspend call back, should be called after the child devices
1072 * have actually been suspended
1075 pmac_ide_do_suspend(ide_hwif_t
*hwif
)
1077 pmac_ide_hwif_t
*pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1079 /* We clear the timings */
1080 pmif
->timings
[0] = 0;
1081 pmif
->timings
[1] = 0;
1083 disable_irq(pmif
->irq
);
1085 /* The media bay will handle itself just fine */
1089 /* Kauai has bus control FCRs directly here */
1090 if (pmif
->kauai_fcr
) {
1091 u32 fcr
= readl(pmif
->kauai_fcr
);
1092 fcr
&= ~(KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
);
1093 writel(fcr
, pmif
->kauai_fcr
);
1096 /* Disable the bus on older machines and the cell on kauai */
1097 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, pmif
->node
, pmif
->aapl_bus_id
,
1103 /* Resume call back, should be called before the child devices
1107 pmac_ide_do_resume(ide_hwif_t
*hwif
)
1109 pmac_ide_hwif_t
*pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1111 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1112 if (!pmif
->mediabay
) {
1113 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, pmif
->node
, pmif
->aapl_bus_id
, 1);
1114 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, pmif
->node
, pmif
->aapl_bus_id
, 1);
1116 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, pmif
->node
, pmif
->aapl_bus_id
, 0);
1118 /* Kauai has it different */
1119 if (pmif
->kauai_fcr
) {
1120 u32 fcr
= readl(pmif
->kauai_fcr
);
1121 fcr
|= KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
;
1122 writel(fcr
, pmif
->kauai_fcr
);
1125 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY
));
1128 /* Sanitize drive timings */
1129 sanitize_timings(pmif
);
1131 enable_irq(pmif
->irq
);
1137 * Setup, register & probe an IDE channel driven by this driver, this is
1138 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1139 * that ends up beeing free of any device is not kept around by this driver
1140 * (it is kept in 2.4). This introduce an interface numbering change on some
1141 * rare machines unfortunately, but it's better this way.
1144 pmac_ide_setup_device(pmac_ide_hwif_t
*pmif
, ide_hwif_t
*hwif
)
1146 struct device_node
*np
= pmif
->node
;
1150 pmif
->broken_dma
= pmif
->broken_dma_warn
= 0;
1151 if (of_device_is_compatible(np
, "shasta-ata"))
1152 pmif
->kind
= controller_sh_ata6
;
1153 else if (of_device_is_compatible(np
, "kauai-ata"))
1154 pmif
->kind
= controller_un_ata6
;
1155 else if (of_device_is_compatible(np
, "K2-UATA"))
1156 pmif
->kind
= controller_k2_ata6
;
1157 else if (of_device_is_compatible(np
, "keylargo-ata")) {
1158 if (strcmp(np
->name
, "ata-4") == 0)
1159 pmif
->kind
= controller_kl_ata4
;
1161 pmif
->kind
= controller_kl_ata3
;
1162 } else if (of_device_is_compatible(np
, "heathrow-ata"))
1163 pmif
->kind
= controller_heathrow
;
1165 pmif
->kind
= controller_ohare
;
1166 pmif
->broken_dma
= 1;
1169 bidp
= of_get_property(np
, "AAPL,bus-id", NULL
);
1170 pmif
->aapl_bus_id
= bidp
? *bidp
: 0;
1172 /* Get cable type from device-tree */
1173 if (pmif
->kind
== controller_kl_ata4
|| pmif
->kind
== controller_un_ata6
1174 || pmif
->kind
== controller_k2_ata6
1175 || pmif
->kind
== controller_sh_ata6
) {
1176 const char* cable
= of_get_property(np
, "cable-type", NULL
);
1177 if (cable
&& !strncmp(cable
, "80-", 3))
1180 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1181 * they have a 80 conductor cable, this seem to be always the case unless
1182 * the user mucked around
1184 if (of_device_is_compatible(np
, "K2-UATA") ||
1185 of_device_is_compatible(np
, "shasta-ata"))
1188 /* On Kauai-type controllers, we make sure the FCR is correct */
1189 if (pmif
->kauai_fcr
)
1190 writel(KAUAI_FCR_UATA_MAGIC
|
1191 KAUAI_FCR_UATA_RESET_N
|
1192 KAUAI_FCR_UATA_ENABLE
, pmif
->kauai_fcr
);
1196 /* Make sure we have sane timings */
1197 sanitize_timings(pmif
);
1199 #ifndef CONFIG_PPC64
1200 /* XXX FIXME: Media bay stuff need re-organizing */
1201 if (np
->parent
&& np
->parent
->name
1202 && strcasecmp(np
->parent
->name
, "media-bay") == 0) {
1203 #ifdef CONFIG_PMAC_MEDIABAY
1204 media_bay_set_ide_infos(np
->parent
, pmif
->regbase
, pmif
->irq
, hwif
->index
);
1205 #endif /* CONFIG_PMAC_MEDIABAY */
1208 pmif
->aapl_bus_id
= 1;
1209 } else if (pmif
->kind
== controller_ohare
) {
1210 /* The code below is having trouble on some ohare machines
1211 * (timing related ?). Until I can put my hand on one of these
1212 * units, I keep the old way
1214 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, np
, 0, 1);
1218 /* This is necessary to enable IDE when net-booting */
1219 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, np
, pmif
->aapl_bus_id
, 1);
1220 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, np
, pmif
->aapl_bus_id
, 1);
1222 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, np
, pmif
->aapl_bus_id
, 0);
1223 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY
));
1226 /* Setup MMIO ops */
1227 default_hwif_mmiops(hwif
);
1228 hwif
->OUTBSYNC
= pmac_outbsync
;
1230 /* Tell common code _not_ to mess with resources */
1232 hwif
->hwif_data
= pmif
;
1233 pmac_ide_init_hwif_ports(&hwif
->hw
, pmif
->regbase
, 0, &hwif
->irq
);
1234 memcpy(hwif
->io_ports
, hwif
->hw
.io_ports
, sizeof(hwif
->io_ports
));
1235 hwif
->chipset
= ide_pmac
;
1236 hwif
->noprobe
= !hwif
->io_ports
[IDE_DATA_OFFSET
] || pmif
->mediabay
;
1237 hwif
->hold
= pmif
->mediabay
;
1238 hwif
->cbl
= pmif
->cable_80
? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
1239 hwif
->drives
[0].unmask
= 1;
1240 hwif
->drives
[1].unmask
= 1;
1241 hwif
->pio_mask
= ATA_PIO4
;
1242 hwif
->set_pio_mode
= pmac_ide_set_pio_mode
;
1243 if (pmif
->kind
== controller_un_ata6
1244 || pmif
->kind
== controller_k2_ata6
1245 || pmif
->kind
== controller_sh_ata6
)
1246 hwif
->selectproc
= pmac_ide_kauai_selectproc
;
1248 hwif
->selectproc
= pmac_ide_selectproc
;
1249 hwif
->speedproc
= pmac_ide_tune_chipset
;
1251 printk(KERN_INFO
"ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1252 hwif
->index
, model_name
[pmif
->kind
], pmif
->aapl_bus_id
,
1253 pmif
->mediabay
? " (mediabay)" : "", hwif
->irq
);
1255 #ifdef CONFIG_PMAC_MEDIABAY
1256 if (pmif
->mediabay
&& check_media_bay_by_base(pmif
->regbase
, MB_CD
) == 0)
1258 #endif /* CONFIG_PMAC_MEDIABAY */
1260 hwif
->sg_max_nents
= MAX_DCMDS
;
1262 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1263 /* has a DBDMA controller channel */
1265 pmac_ide_setup_dma(pmif
, hwif
);
1266 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1268 /* We probe the hwif now */
1269 probe_hwif_init(hwif
);
1271 ide_proc_register_port(hwif
);
1277 * Attach to a macio probed interface
1279 static int __devinit
1280 pmac_ide_macio_attach(struct macio_dev
*mdev
, const struct of_device_id
*match
)
1283 unsigned long regbase
;
1286 pmac_ide_hwif_t
*pmif
;
1290 while (i
< MAX_HWIFS
&& (ide_hwifs
[i
].io_ports
[IDE_DATA_OFFSET
] != 0
1291 || pmac_ide
[i
].node
!= NULL
))
1293 if (i
>= MAX_HWIFS
) {
1294 printk(KERN_ERR
"ide-pmac: MacIO interface attach with no slot\n");
1295 printk(KERN_ERR
" %s\n", mdev
->ofdev
.node
->full_name
);
1299 pmif
= &pmac_ide
[i
];
1300 hwif
= &ide_hwifs
[i
];
1302 if (macio_resource_count(mdev
) == 0) {
1303 printk(KERN_WARNING
"ide%d: no address for %s\n",
1304 i
, mdev
->ofdev
.node
->full_name
);
1308 /* Request memory resource for IO ports */
1309 if (macio_request_resource(mdev
, 0, "ide-pmac (ports)")) {
1310 printk(KERN_ERR
"ide%d: can't request mmio resource !\n", i
);
1314 /* XXX This is bogus. Should be fixed in the registry by checking
1315 * the kind of host interrupt controller, a bit like gatwick
1316 * fixes in irq.c. That works well enough for the single case
1317 * where that happens though...
1319 if (macio_irq_count(mdev
) == 0) {
1320 printk(KERN_WARNING
"ide%d: no intrs for device %s, using 13\n",
1321 i
, mdev
->ofdev
.node
->full_name
);
1322 irq
= irq_create_mapping(NULL
, 13);
1324 irq
= macio_irq(mdev
, 0);
1326 base
= ioremap(macio_resource_start(mdev
, 0), 0x400);
1327 regbase
= (unsigned long) base
;
1329 hwif
->pci_dev
= mdev
->bus
->pdev
;
1330 hwif
->gendev
.parent
= &mdev
->ofdev
.dev
;
1333 pmif
->node
= mdev
->ofdev
.node
;
1334 pmif
->regbase
= regbase
;
1336 pmif
->kauai_fcr
= NULL
;
1337 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1338 if (macio_resource_count(mdev
) >= 2) {
1339 if (macio_request_resource(mdev
, 1, "ide-pmac (dma)"))
1340 printk(KERN_WARNING
"ide%d: can't request DMA resource !\n", i
);
1342 pmif
->dma_regs
= ioremap(macio_resource_start(mdev
, 1), 0x1000);
1344 pmif
->dma_regs
= NULL
;
1345 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1346 dev_set_drvdata(&mdev
->ofdev
.dev
, hwif
);
1348 rc
= pmac_ide_setup_device(pmif
, hwif
);
1350 /* The inteface is released to the common IDE layer */
1351 dev_set_drvdata(&mdev
->ofdev
.dev
, NULL
);
1354 iounmap(pmif
->dma_regs
);
1355 memset(pmif
, 0, sizeof(*pmif
));
1356 macio_release_resource(mdev
, 0);
1358 macio_release_resource(mdev
, 1);
1365 pmac_ide_macio_suspend(struct macio_dev
*mdev
, pm_message_t mesg
)
1367 ide_hwif_t
*hwif
= (ide_hwif_t
*)dev_get_drvdata(&mdev
->ofdev
.dev
);
1370 if (mesg
.event
!= mdev
->ofdev
.dev
.power
.power_state
.event
1371 && mesg
.event
== PM_EVENT_SUSPEND
) {
1372 rc
= pmac_ide_do_suspend(hwif
);
1374 mdev
->ofdev
.dev
.power
.power_state
= mesg
;
1381 pmac_ide_macio_resume(struct macio_dev
*mdev
)
1383 ide_hwif_t
*hwif
= (ide_hwif_t
*)dev_get_drvdata(&mdev
->ofdev
.dev
);
1386 if (mdev
->ofdev
.dev
.power
.power_state
.event
!= PM_EVENT_ON
) {
1387 rc
= pmac_ide_do_resume(hwif
);
1389 mdev
->ofdev
.dev
.power
.power_state
= PMSG_ON
;
1396 * Attach to a PCI probed interface
1398 static int __devinit
1399 pmac_ide_pci_attach(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1402 struct device_node
*np
;
1403 pmac_ide_hwif_t
*pmif
;
1405 unsigned long rbase
, rlen
;
1408 np
= pci_device_to_OF_node(pdev
);
1410 printk(KERN_ERR
"ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1414 while (i
< MAX_HWIFS
&& (ide_hwifs
[i
].io_ports
[IDE_DATA_OFFSET
] != 0
1415 || pmac_ide
[i
].node
!= NULL
))
1417 if (i
>= MAX_HWIFS
) {
1418 printk(KERN_ERR
"ide-pmac: PCI interface attach with no slot\n");
1419 printk(KERN_ERR
" %s\n", np
->full_name
);
1423 pmif
= &pmac_ide
[i
];
1424 hwif
= &ide_hwifs
[i
];
1426 if (pci_enable_device(pdev
)) {
1427 printk(KERN_WARNING
"ide%i: Can't enable PCI device for %s\n",
1431 pci_set_master(pdev
);
1433 if (pci_request_regions(pdev
, "Kauai ATA")) {
1434 printk(KERN_ERR
"ide%d: Cannot obtain PCI resources for %s\n",
1439 hwif
->pci_dev
= pdev
;
1440 hwif
->gendev
.parent
= &pdev
->dev
;
1444 rbase
= pci_resource_start(pdev
, 0);
1445 rlen
= pci_resource_len(pdev
, 0);
1447 base
= ioremap(rbase
, rlen
);
1448 pmif
->regbase
= (unsigned long) base
+ 0x2000;
1449 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1450 pmif
->dma_regs
= base
+ 0x1000;
1451 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1452 pmif
->kauai_fcr
= base
;
1453 pmif
->irq
= pdev
->irq
;
1455 pci_set_drvdata(pdev
, hwif
);
1457 rc
= pmac_ide_setup_device(pmif
, hwif
);
1459 /* The inteface is released to the common IDE layer */
1460 pci_set_drvdata(pdev
, NULL
);
1462 memset(pmif
, 0, sizeof(*pmif
));
1463 pci_release_regions(pdev
);
1470 pmac_ide_pci_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1472 ide_hwif_t
*hwif
= (ide_hwif_t
*)pci_get_drvdata(pdev
);
1475 if (mesg
.event
!= pdev
->dev
.power
.power_state
.event
1476 && mesg
.event
== PM_EVENT_SUSPEND
) {
1477 rc
= pmac_ide_do_suspend(hwif
);
1479 pdev
->dev
.power
.power_state
= mesg
;
1486 pmac_ide_pci_resume(struct pci_dev
*pdev
)
1488 ide_hwif_t
*hwif
= (ide_hwif_t
*)pci_get_drvdata(pdev
);
1491 if (pdev
->dev
.power
.power_state
.event
!= PM_EVENT_ON
) {
1492 rc
= pmac_ide_do_resume(hwif
);
1494 pdev
->dev
.power
.power_state
= PMSG_ON
;
1500 static struct of_device_id pmac_ide_macio_match
[] =
1517 static struct macio_driver pmac_ide_macio_driver
=
1520 .match_table
= pmac_ide_macio_match
,
1521 .probe
= pmac_ide_macio_attach
,
1522 .suspend
= pmac_ide_macio_suspend
,
1523 .resume
= pmac_ide_macio_resume
,
1526 static struct pci_device_id pmac_ide_pci_match
[] = {
1527 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_ATA
,
1528 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1529 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_IPID_ATA100
,
1530 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1531 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_K2_ATA100
,
1532 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1533 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_SH_ATA
,
1534 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1535 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_IPID2_ATA
,
1536 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1540 static struct pci_driver pmac_ide_pci_driver
= {
1542 .id_table
= pmac_ide_pci_match
,
1543 .probe
= pmac_ide_pci_attach
,
1544 .suspend
= pmac_ide_pci_suspend
,
1545 .resume
= pmac_ide_pci_resume
,
1547 MODULE_DEVICE_TABLE(pci
, pmac_ide_pci_match
);
1549 int __init
pmac_ide_probe(void)
1553 if (!machine_is(powermac
))
1556 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1557 error
= pci_register_driver(&pmac_ide_pci_driver
);
1560 error
= macio_register_driver(&pmac_ide_macio_driver
);
1562 pci_unregister_driver(&pmac_ide_pci_driver
);
1566 error
= macio_register_driver(&pmac_ide_macio_driver
);
1569 error
= pci_register_driver(&pmac_ide_pci_driver
);
1571 macio_unregister_driver(&pmac_ide_macio_driver
);
1579 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1582 * pmac_ide_build_dmatable builds the DBDMA command list
1583 * for a transfer and sets the DBDMA channel to point to it.
1586 pmac_ide_build_dmatable(ide_drive_t
*drive
, struct request
*rq
)
1588 struct dbdma_cmd
*table
;
1590 ide_hwif_t
*hwif
= HWIF(drive
);
1591 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1592 volatile struct dbdma_regs __iomem
*dma
= pmif
->dma_regs
;
1593 struct scatterlist
*sg
;
1594 int wr
= (rq_data_dir(rq
) == WRITE
);
1596 /* DMA table is already aligned */
1597 table
= (struct dbdma_cmd
*) pmif
->dma_table_cpu
;
1599 /* Make sure DMA controller is stopped (necessary ?) */
1600 writel((RUN
|PAUSE
|FLUSH
|WAKE
|DEAD
) << 16, &dma
->control
);
1601 while (readl(&dma
->status
) & RUN
)
1604 hwif
->sg_nents
= i
= ide_build_sglist(drive
, rq
);
1609 /* Build DBDMA commands list */
1610 sg
= hwif
->sg_table
;
1611 while (i
&& sg_dma_len(sg
)) {
1615 cur_addr
= sg_dma_address(sg
);
1616 cur_len
= sg_dma_len(sg
);
1618 if (pmif
->broken_dma
&& cur_addr
& (L1_CACHE_BYTES
- 1)) {
1619 if (pmif
->broken_dma_warn
== 0) {
1620 printk(KERN_WARNING
"%s: DMA on non aligned address,"
1621 "switching to PIO on Ohare chipset\n", drive
->name
);
1622 pmif
->broken_dma_warn
= 1;
1624 goto use_pio_instead
;
1627 unsigned int tc
= (cur_len
< 0xfe00)? cur_len
: 0xfe00;
1629 if (count
++ >= MAX_DCMDS
) {
1630 printk(KERN_WARNING
"%s: DMA table too small\n",
1632 goto use_pio_instead
;
1634 st_le16(&table
->command
, wr
? OUTPUT_MORE
: INPUT_MORE
);
1635 st_le16(&table
->req_count
, tc
);
1636 st_le32(&table
->phy_addr
, cur_addr
);
1638 table
->xfer_status
= 0;
1639 table
->res_count
= 0;
1648 /* convert the last command to an input/output last command */
1650 st_le16(&table
[-1].command
, wr
? OUTPUT_LAST
: INPUT_LAST
);
1651 /* add the stop command to the end of the list */
1652 memset(table
, 0, sizeof(struct dbdma_cmd
));
1653 st_le16(&table
->command
, DBDMA_STOP
);
1655 writel(hwif
->dmatable_dma
, &dma
->cmdptr
);
1659 printk(KERN_DEBUG
"%s: empty DMA table?\n", drive
->name
);
1661 pci_unmap_sg(hwif
->pci_dev
,
1664 hwif
->sg_dma_direction
);
1665 return 0; /* revert to PIO for this request */
1668 /* Teardown mappings after DMA has completed. */
1670 pmac_ide_destroy_dmatable (ide_drive_t
*drive
)
1672 ide_hwif_t
*hwif
= drive
->hwif
;
1673 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
1674 struct scatterlist
*sg
= hwif
->sg_table
;
1675 int nents
= hwif
->sg_nents
;
1678 pci_unmap_sg(dev
, sg
, nents
, hwif
->sg_dma_direction
);
1684 * Pick up best MDMA timing for the drive and apply it
1687 pmac_ide_mdma_enable(ide_drive_t
*drive
, u16 mode
)
1689 ide_hwif_t
*hwif
= HWIF(drive
);
1690 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1691 int drive_cycle_time
;
1692 struct hd_driveid
*id
= drive
->id
;
1693 u32
*timings
, *timings2
;
1694 u32 timing_local
[2];
1697 /* which drive is it ? */
1698 timings
= &pmif
->timings
[drive
->select
.b
.unit
& 0x01];
1699 timings2
= &pmif
->timings
[(drive
->select
.b
.unit
& 0x01) + 2];
1701 /* Check if drive provide explicit cycle time */
1702 if ((id
->field_valid
& 2) && (id
->eide_dma_time
))
1703 drive_cycle_time
= id
->eide_dma_time
;
1705 drive_cycle_time
= 0;
1707 /* Copy timings to local image */
1708 timing_local
[0] = *timings
;
1709 timing_local
[1] = *timings2
;
1711 /* Calculate controller timings */
1712 ret
= set_timings_mdma( drive
, pmif
->kind
,
1720 /* Set feature on drive */
1721 printk(KERN_INFO
"%s: Enabling MultiWord DMA %d\n", drive
->name
, mode
& 0xf);
1722 ret
= pmac_ide_do_setfeature(drive
, mode
);
1724 printk(KERN_WARNING
"%s: Failed !\n", drive
->name
);
1728 /* Apply timings to controller */
1729 *timings
= timing_local
[0];
1730 *timings2
= timing_local
[1];
1736 * Pick up best UDMA timing for the drive and apply it
1739 pmac_ide_udma_enable(ide_drive_t
*drive
, u16 mode
)
1741 ide_hwif_t
*hwif
= HWIF(drive
);
1742 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1743 u32
*timings
, *timings2
;
1744 u32 timing_local
[2];
1747 /* which drive is it ? */
1748 timings
= &pmif
->timings
[drive
->select
.b
.unit
& 0x01];
1749 timings2
= &pmif
->timings
[(drive
->select
.b
.unit
& 0x01) + 2];
1751 /* Copy timings to local image */
1752 timing_local
[0] = *timings
;
1753 timing_local
[1] = *timings2
;
1755 /* Calculate timings for interface */
1756 if (pmif
->kind
== controller_un_ata6
1757 || pmif
->kind
== controller_k2_ata6
)
1758 ret
= set_timings_udma_ata6( &timing_local
[0],
1761 else if (pmif
->kind
== controller_sh_ata6
)
1762 ret
= set_timings_udma_shasta( &timing_local
[0],
1766 ret
= set_timings_udma_ata4(&timing_local
[0], mode
);
1770 /* Set feature on drive */
1771 printk(KERN_INFO
"%s: Enabling Ultra DMA %d\n", drive
->name
, mode
& 0x0f);
1772 ret
= pmac_ide_do_setfeature(drive
, mode
);
1774 printk(KERN_WARNING
"%s: Failed !\n", drive
->name
);
1778 /* Apply timings to controller */
1779 *timings
= timing_local
[0];
1780 *timings2
= timing_local
[1];
1786 * Check what is the best DMA timing setting for the drive and
1787 * call appropriate functions to apply it.
1790 pmac_ide_dma_check(ide_drive_t
*drive
)
1792 struct hd_driveid
*id
= drive
->id
;
1793 ide_hwif_t
*hwif
= HWIF(drive
);
1795 drive
->using_dma
= 0;
1797 if (drive
->media
== ide_floppy
)
1799 if (((id
->capability
& 1) == 0) && !__ide_dma_good_drive(drive
))
1801 if (__ide_dma_bad_drive(drive
))
1805 u8 mode
= ide_max_dma_mode(drive
);
1807 if (mode
>= XFER_UDMA_0
)
1808 drive
->using_dma
= pmac_ide_udma_enable(drive
, mode
);
1809 else if (mode
>= XFER_MW_DMA_0
)
1810 drive
->using_dma
= pmac_ide_mdma_enable(drive
, mode
);
1811 hwif
->OUTB(0, IDE_CONTROL_REG
);
1812 /* Apply settings to controller */
1813 pmac_ide_do_update_timings(drive
);
1819 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1820 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1823 pmac_ide_dma_setup(ide_drive_t
*drive
)
1825 ide_hwif_t
*hwif
= HWIF(drive
);
1826 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1827 struct request
*rq
= HWGROUP(drive
)->rq
;
1828 u8 unit
= (drive
->select
.b
.unit
& 0x01);
1833 ata4
= (pmif
->kind
== controller_kl_ata4
);
1835 if (!pmac_ide_build_dmatable(drive
, rq
)) {
1836 ide_map_sg(drive
, rq
);
1840 /* Apple adds 60ns to wrDataSetup on reads */
1841 if (ata4
&& (pmif
->timings
[unit
] & TR_66_UDMA_EN
)) {
1842 writel(pmif
->timings
[unit
] + (!rq_data_dir(rq
) ? 0x00800000UL
: 0),
1843 PMAC_IDE_REG(IDE_TIMING_CONFIG
));
1844 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
1847 drive
->waiting_for_dma
= 1;
1853 pmac_ide_dma_exec_cmd(ide_drive_t
*drive
, u8 command
)
1855 /* issue cmd to drive */
1856 ide_execute_command(drive
, command
, &ide_dma_intr
, 2*WAIT_CMD
, NULL
);
1860 * Kick the DMA controller into life after the DMA command has been issued
1864 pmac_ide_dma_start(ide_drive_t
*drive
)
1866 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1867 volatile struct dbdma_regs __iomem
*dma
;
1869 dma
= pmif
->dma_regs
;
1871 writel((RUN
<< 16) | RUN
, &dma
->control
);
1872 /* Make sure it gets to the controller right now */
1873 (void)readl(&dma
->control
);
1877 * After a DMA transfer, make sure the controller is stopped
1880 pmac_ide_dma_end (ide_drive_t
*drive
)
1882 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1883 volatile struct dbdma_regs __iomem
*dma
;
1888 dma
= pmif
->dma_regs
;
1890 drive
->waiting_for_dma
= 0;
1891 dstat
= readl(&dma
->status
);
1892 writel(((RUN
|WAKE
|DEAD
) << 16), &dma
->control
);
1893 pmac_ide_destroy_dmatable(drive
);
1894 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1895 * in theory, but with ATAPI decices doing buffer underruns, that would
1896 * cause us to disable DMA, which isn't what we want
1898 return (dstat
& (RUN
|DEAD
)) != RUN
;
1902 * Check out that the interrupt we got was for us. We can't always know this
1903 * for sure with those Apple interfaces (well, we could on the recent ones but
1904 * that's not implemented yet), on the other hand, we don't have shared interrupts
1905 * so it's not really a problem
1908 pmac_ide_dma_test_irq (ide_drive_t
*drive
)
1910 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1911 volatile struct dbdma_regs __iomem
*dma
;
1912 unsigned long status
, timeout
;
1916 dma
= pmif
->dma_regs
;
1918 /* We have to things to deal with here:
1920 * - The dbdma won't stop if the command was started
1921 * but completed with an error without transferring all
1922 * datas. This happens when bad blocks are met during
1923 * a multi-block transfer.
1925 * - The dbdma fifo hasn't yet finished flushing to
1926 * to system memory when the disk interrupt occurs.
1930 /* If ACTIVE is cleared, the STOP command have passed and
1931 * transfer is complete.
1933 status
= readl(&dma
->status
);
1934 if (!(status
& ACTIVE
))
1936 if (!drive
->waiting_for_dma
)
1937 printk(KERN_WARNING
"ide%d, ide_dma_test_irq \
1938 called while not waiting\n", HWIF(drive
)->index
);
1940 /* If dbdma didn't execute the STOP command yet, the
1941 * active bit is still set. We consider that we aren't
1942 * sharing interrupts (which is hopefully the case with
1943 * those controllers) and so we just try to flush the
1944 * channel for pending data in the fifo
1947 writel((FLUSH
<< 16) | FLUSH
, &dma
->control
);
1951 status
= readl(&dma
->status
);
1952 if ((status
& FLUSH
) == 0)
1954 if (++timeout
> 100) {
1955 printk(KERN_WARNING
"ide%d, ide_dma_test_irq \
1956 timeout flushing channel\n", HWIF(drive
)->index
);
1963 static void pmac_ide_dma_host_off(ide_drive_t
*drive
)
1967 static void pmac_ide_dma_host_on(ide_drive_t
*drive
)
1972 pmac_ide_dma_lost_irq (ide_drive_t
*drive
)
1974 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1975 volatile struct dbdma_regs __iomem
*dma
;
1976 unsigned long status
;
1980 dma
= pmif
->dma_regs
;
1982 status
= readl(&dma
->status
);
1983 printk(KERN_ERR
"ide-pmac lost interrupt, dma status: %lx\n", status
);
1987 * Allocate the data structures needed for using DMA with an interface
1988 * and fill the proper list of functions pointers
1991 pmac_ide_setup_dma(pmac_ide_hwif_t
*pmif
, ide_hwif_t
*hwif
)
1993 /* We won't need pci_dev if we switch to generic consistent
1996 if (hwif
->pci_dev
== NULL
)
1999 * Allocate space for the DBDMA commands.
2000 * The +2 is +1 for the stop command and +1 to allow for
2001 * aligning the start address to a multiple of 16 bytes.
2003 pmif
->dma_table_cpu
= (struct dbdma_cmd
*)pci_alloc_consistent(
2005 (MAX_DCMDS
+ 2) * sizeof(struct dbdma_cmd
),
2006 &hwif
->dmatable_dma
);
2007 if (pmif
->dma_table_cpu
== NULL
) {
2008 printk(KERN_ERR
"%s: unable to allocate DMA command list\n",
2013 hwif
->dma_off_quietly
= &ide_dma_off_quietly
;
2014 hwif
->ide_dma_on
= &__ide_dma_on
;
2015 hwif
->ide_dma_check
= &pmac_ide_dma_check
;
2016 hwif
->dma_setup
= &pmac_ide_dma_setup
;
2017 hwif
->dma_exec_cmd
= &pmac_ide_dma_exec_cmd
;
2018 hwif
->dma_start
= &pmac_ide_dma_start
;
2019 hwif
->ide_dma_end
= &pmac_ide_dma_end
;
2020 hwif
->ide_dma_test_irq
= &pmac_ide_dma_test_irq
;
2021 hwif
->dma_host_off
= &pmac_ide_dma_host_off
;
2022 hwif
->dma_host_on
= &pmac_ide_dma_host_on
;
2023 hwif
->dma_timeout
= &ide_dma_timeout
;
2024 hwif
->dma_lost_irq
= &pmac_ide_dma_lost_irq
;
2026 hwif
->atapi_dma
= 1;
2027 switch(pmif
->kind
) {
2028 case controller_sh_ata6
:
2029 hwif
->ultra_mask
= pmif
->cable_80
? 0x7f : 0x07;
2030 hwif
->mwdma_mask
= 0x07;
2031 hwif
->swdma_mask
= 0x00;
2033 case controller_un_ata6
:
2034 case controller_k2_ata6
:
2035 hwif
->ultra_mask
= pmif
->cable_80
? 0x3f : 0x07;
2036 hwif
->mwdma_mask
= 0x07;
2037 hwif
->swdma_mask
= 0x00;
2039 case controller_kl_ata4
:
2040 hwif
->ultra_mask
= pmif
->cable_80
? 0x1f : 0x07;
2041 hwif
->mwdma_mask
= 0x07;
2042 hwif
->swdma_mask
= 0x00;
2045 hwif
->ultra_mask
= 0x00;
2046 hwif
->mwdma_mask
= 0x07;
2047 hwif
->swdma_mask
= 0x00;
2052 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */