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ide: add missing ide_rate_filter() calls to ->speedproc()-s
[deliverable/linux.git] / drivers / ide / ppc / pmac.c
1 /*
2 * linux/drivers/ide/ppc/pmac.c
3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/pci.h>
33 #include <linux/adb.h>
34 #include <linux/pmu.h>
35 #include <linux/scatterlist.h>
36
37 #include <asm/prom.h>
38 #include <asm/io.h>
39 #include <asm/dbdma.h>
40 #include <asm/ide.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/machdep.h>
43 #include <asm/pmac_feature.h>
44 #include <asm/sections.h>
45 #include <asm/irq.h>
46
47 #ifndef CONFIG_PPC64
48 #include <asm/mediabay.h>
49 #endif
50
51 #include "../ide-timing.h"
52
53 #undef IDE_PMAC_DEBUG
54
55 #define DMA_WAIT_TIMEOUT 50
56
57 typedef struct pmac_ide_hwif {
58 unsigned long regbase;
59 int irq;
60 int kind;
61 int aapl_bus_id;
62 unsigned cable_80 : 1;
63 unsigned mediabay : 1;
64 unsigned broken_dma : 1;
65 unsigned broken_dma_warn : 1;
66 struct device_node* node;
67 struct macio_dev *mdev;
68 u32 timings[4];
69 volatile u32 __iomem * *kauai_fcr;
70 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
71 /* Those fields are duplicating what is in hwif. We currently
72 * can't use the hwif ones because of some assumptions that are
73 * beeing done by the generic code about the kind of dma controller
74 * and format of the dma table. This will have to be fixed though.
75 */
76 volatile struct dbdma_regs __iomem * dma_regs;
77 struct dbdma_cmd* dma_table_cpu;
78 #endif
79
80 } pmac_ide_hwif_t;
81
82 static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
83 static int pmac_ide_count;
84
85 enum {
86 controller_ohare, /* OHare based */
87 controller_heathrow, /* Heathrow/Paddington */
88 controller_kl_ata3, /* KeyLargo ATA-3 */
89 controller_kl_ata4, /* KeyLargo ATA-4 */
90 controller_un_ata6, /* UniNorth2 ATA-6 */
91 controller_k2_ata6, /* K2 ATA-6 */
92 controller_sh_ata6, /* Shasta ATA-6 */
93 };
94
95 static const char* model_name[] = {
96 "OHare ATA", /* OHare based */
97 "Heathrow ATA", /* Heathrow/Paddington */
98 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
99 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
100 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
101 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
102 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
103 };
104
105 /*
106 * Extra registers, both 32-bit little-endian
107 */
108 #define IDE_TIMING_CONFIG 0x200
109 #define IDE_INTERRUPT 0x300
110
111 /* Kauai (U2) ATA has different register setup */
112 #define IDE_KAUAI_PIO_CONFIG 0x200
113 #define IDE_KAUAI_ULTRA_CONFIG 0x210
114 #define IDE_KAUAI_POLL_CONFIG 0x220
115
116 /*
117 * Timing configuration register definitions
118 */
119
120 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
121 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
122 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
123 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
124 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
125
126 /* 133Mhz cell, found in shasta.
127 * See comments about 100 Mhz Uninorth 2...
128 * Note that PIO_MASK and MDMA_MASK seem to overlap
129 */
130 #define TR_133_PIOREG_PIO_MASK 0xff000fff
131 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
132 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
133 #define TR_133_UDMAREG_UDMA_EN 0x00000001
134
135 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
136 * this one yet, it appears as a pci device (106b/0033) on uninorth
137 * internal PCI bus and it's clock is controlled like gem or fw. It
138 * appears to be an evolution of keylargo ATA4 with a timing register
139 * extended to 2 32bits registers and a similar DBDMA channel. Other
140 * registers seem to exist but I can't tell much about them.
141 *
142 * So far, I'm using pre-calculated tables for this extracted from
143 * the values used by the MacOS X driver.
144 *
145 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
146 * register controls the UDMA timings. At least, it seems bit 0
147 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
148 * cycle time in units of 10ns. Bits 8..15 are used by I don't
149 * know their meaning yet
150 */
151 #define TR_100_PIOREG_PIO_MASK 0xff000fff
152 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
153 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
154 #define TR_100_UDMAREG_UDMA_EN 0x00000001
155
156
157 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
158 * 40 connector cable and to 4 on 80 connector one.
159 * Clock unit is 15ns (66Mhz)
160 *
161 * 3 Values can be programmed:
162 * - Write data setup, which appears to match the cycle time. They
163 * also call it DIOW setup.
164 * - Ready to pause time (from spec)
165 * - Address setup. That one is weird. I don't see where exactly
166 * it fits in UDMA cycles, I got it's name from an obscure piece
167 * of commented out code in Darwin. They leave it to 0, we do as
168 * well, despite a comment that would lead to think it has a
169 * min value of 45ns.
170 * Apple also add 60ns to the write data setup (or cycle time ?) on
171 * reads.
172 */
173 #define TR_66_UDMA_MASK 0xfff00000
174 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
175 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
176 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
177 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
178 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
179 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
180 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
181 #define TR_66_MDMA_MASK 0x000ffc00
182 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
183 #define TR_66_MDMA_RECOVERY_SHIFT 15
184 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
185 #define TR_66_MDMA_ACCESS_SHIFT 10
186 #define TR_66_PIO_MASK 0x000003ff
187 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
188 #define TR_66_PIO_RECOVERY_SHIFT 5
189 #define TR_66_PIO_ACCESS_MASK 0x0000001f
190 #define TR_66_PIO_ACCESS_SHIFT 0
191
192 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
193 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
194 *
195 * The access time and recovery time can be programmed. Some older
196 * Darwin code base limit OHare to 150ns cycle time. I decided to do
197 * the same here fore safety against broken old hardware ;)
198 * The HalfTick bit, when set, adds half a clock (15ns) to the access
199 * time and removes one from recovery. It's not supported on KeyLargo
200 * implementation afaik. The E bit appears to be set for PIO mode 0 and
201 * is used to reach long timings used in this mode.
202 */
203 #define TR_33_MDMA_MASK 0x003ff800
204 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
205 #define TR_33_MDMA_RECOVERY_SHIFT 16
206 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
207 #define TR_33_MDMA_ACCESS_SHIFT 11
208 #define TR_33_MDMA_HALFTICK 0x00200000
209 #define TR_33_PIO_MASK 0x000007ff
210 #define TR_33_PIO_E 0x00000400
211 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
212 #define TR_33_PIO_RECOVERY_SHIFT 5
213 #define TR_33_PIO_ACCESS_MASK 0x0000001f
214 #define TR_33_PIO_ACCESS_SHIFT 0
215
216 /*
217 * Interrupt register definitions
218 */
219 #define IDE_INTR_DMA 0x80000000
220 #define IDE_INTR_DEVICE 0x40000000
221
222 /*
223 * FCR Register on Kauai. Not sure what bit 0x4 is ...
224 */
225 #define KAUAI_FCR_UATA_MAGIC 0x00000004
226 #define KAUAI_FCR_UATA_RESET_N 0x00000002
227 #define KAUAI_FCR_UATA_ENABLE 0x00000001
228
229 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
230
231 /* Rounded Multiword DMA timings
232 *
233 * I gave up finding a generic formula for all controller
234 * types and instead, built tables based on timing values
235 * used by Apple in Darwin's implementation.
236 */
237 struct mdma_timings_t {
238 int accessTime;
239 int recoveryTime;
240 int cycleTime;
241 };
242
243 struct mdma_timings_t mdma_timings_33[] =
244 {
245 { 240, 240, 480 },
246 { 180, 180, 360 },
247 { 135, 135, 270 },
248 { 120, 120, 240 },
249 { 105, 105, 210 },
250 { 90, 90, 180 },
251 { 75, 75, 150 },
252 { 75, 45, 120 },
253 { 0, 0, 0 }
254 };
255
256 struct mdma_timings_t mdma_timings_33k[] =
257 {
258 { 240, 240, 480 },
259 { 180, 180, 360 },
260 { 150, 150, 300 },
261 { 120, 120, 240 },
262 { 90, 120, 210 },
263 { 90, 90, 180 },
264 { 90, 60, 150 },
265 { 90, 30, 120 },
266 { 0, 0, 0 }
267 };
268
269 struct mdma_timings_t mdma_timings_66[] =
270 {
271 { 240, 240, 480 },
272 { 180, 180, 360 },
273 { 135, 135, 270 },
274 { 120, 120, 240 },
275 { 105, 105, 210 },
276 { 90, 90, 180 },
277 { 90, 75, 165 },
278 { 75, 45, 120 },
279 { 0, 0, 0 }
280 };
281
282 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
283 struct {
284 int addrSetup; /* ??? */
285 int rdy2pause;
286 int wrDataSetup;
287 } kl66_udma_timings[] =
288 {
289 { 0, 180, 120 }, /* Mode 0 */
290 { 0, 150, 90 }, /* 1 */
291 { 0, 120, 60 }, /* 2 */
292 { 0, 90, 45 }, /* 3 */
293 { 0, 90, 30 } /* 4 */
294 };
295
296 /* UniNorth 2 ATA/100 timings */
297 struct kauai_timing {
298 int cycle_time;
299 u32 timing_reg;
300 };
301
302 static struct kauai_timing kauai_pio_timings[] =
303 {
304 { 930 , 0x08000fff },
305 { 600 , 0x08000a92 },
306 { 383 , 0x0800060f },
307 { 360 , 0x08000492 },
308 { 330 , 0x0800048f },
309 { 300 , 0x080003cf },
310 { 270 , 0x080003cc },
311 { 240 , 0x0800038b },
312 { 239 , 0x0800030c },
313 { 180 , 0x05000249 },
314 { 120 , 0x04000148 }
315 };
316
317 static struct kauai_timing kauai_mdma_timings[] =
318 {
319 { 1260 , 0x00fff000 },
320 { 480 , 0x00618000 },
321 { 360 , 0x00492000 },
322 { 270 , 0x0038e000 },
323 { 240 , 0x0030c000 },
324 { 210 , 0x002cb000 },
325 { 180 , 0x00249000 },
326 { 150 , 0x00209000 },
327 { 120 , 0x00148000 },
328 { 0 , 0 },
329 };
330
331 static struct kauai_timing kauai_udma_timings[] =
332 {
333 { 120 , 0x000070c0 },
334 { 90 , 0x00005d80 },
335 { 60 , 0x00004a60 },
336 { 45 , 0x00003a50 },
337 { 30 , 0x00002a30 },
338 { 20 , 0x00002921 },
339 { 0 , 0 },
340 };
341
342 static struct kauai_timing shasta_pio_timings[] =
343 {
344 { 930 , 0x08000fff },
345 { 600 , 0x0A000c97 },
346 { 383 , 0x07000712 },
347 { 360 , 0x040003cd },
348 { 330 , 0x040003cd },
349 { 300 , 0x040003cd },
350 { 270 , 0x040003cd },
351 { 240 , 0x040003cd },
352 { 239 , 0x040003cd },
353 { 180 , 0x0400028b },
354 { 120 , 0x0400010a }
355 };
356
357 static struct kauai_timing shasta_mdma_timings[] =
358 {
359 { 1260 , 0x00fff000 },
360 { 480 , 0x00820800 },
361 { 360 , 0x00820800 },
362 { 270 , 0x00820800 },
363 { 240 , 0x00820800 },
364 { 210 , 0x00820800 },
365 { 180 , 0x00820800 },
366 { 150 , 0x0028b000 },
367 { 120 , 0x001ca000 },
368 { 0 , 0 },
369 };
370
371 static struct kauai_timing shasta_udma133_timings[] =
372 {
373 { 120 , 0x00035901, },
374 { 90 , 0x000348b1, },
375 { 60 , 0x00033881, },
376 { 45 , 0x00033861, },
377 { 30 , 0x00033841, },
378 { 20 , 0x00033031, },
379 { 15 , 0x00033021, },
380 { 0 , 0 },
381 };
382
383
384 static inline u32
385 kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
386 {
387 int i;
388
389 for (i=0; table[i].cycle_time; i++)
390 if (cycle_time > table[i+1].cycle_time)
391 return table[i].timing_reg;
392 return 0;
393 }
394
395 /* allow up to 256 DBDMA commands per xfer */
396 #define MAX_DCMDS 256
397
398 /*
399 * Wait 1s for disk to answer on IDE bus after a hard reset
400 * of the device (via GPIO/FCR).
401 *
402 * Some devices seem to "pollute" the bus even after dropping
403 * the BSY bit (typically some combo drives slave on the UDMA
404 * bus) after a hard reset. Since we hard reset all drives on
405 * KeyLargo ATA66, we have to keep that delay around. I may end
406 * up not hard resetting anymore on these and keep the delay only
407 * for older interfaces instead (we have to reset when coming
408 * from MacOS...) --BenH.
409 */
410 #define IDE_WAKEUP_DELAY (1*HZ)
411
412 static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
413 static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
414 static int pmac_ide_tune_chipset(ide_drive_t *drive, u8 speed);
415 static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio);
416 static void pmac_ide_selectproc(ide_drive_t *drive);
417 static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
418
419 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
420
421 /*
422 * N.B. this can't be an initfunc, because the media-bay task can
423 * call ide_[un]register at any time.
424 */
425 void
426 pmac_ide_init_hwif_ports(hw_regs_t *hw,
427 unsigned long data_port, unsigned long ctrl_port,
428 int *irq)
429 {
430 int i, ix;
431
432 if (data_port == 0)
433 return;
434
435 for (ix = 0; ix < MAX_HWIFS; ++ix)
436 if (data_port == pmac_ide[ix].regbase)
437 break;
438
439 if (ix >= MAX_HWIFS) {
440 /* Probably a PCI interface... */
441 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
442 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
443 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
444 return;
445 }
446
447 for (i = 0; i < 8; ++i)
448 hw->io_ports[i] = data_port + i * 0x10;
449 hw->io_ports[8] = data_port + 0x160;
450
451 if (irq != NULL)
452 *irq = pmac_ide[ix].irq;
453
454 hw->dev = &pmac_ide[ix].mdev->ofdev.dev;
455 }
456
457 #define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
458
459 /*
460 * Apply the timings of the proper unit (master/slave) to the shared
461 * timing register when selecting that unit. This version is for
462 * ASICs with a single timing register
463 */
464 static void
465 pmac_ide_selectproc(ide_drive_t *drive)
466 {
467 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
468
469 if (pmif == NULL)
470 return;
471
472 if (drive->select.b.unit & 0x01)
473 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
474 else
475 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
476 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
477 }
478
479 /*
480 * Apply the timings of the proper unit (master/slave) to the shared
481 * timing register when selecting that unit. This version is for
482 * ASICs with a dual timing register (Kauai)
483 */
484 static void
485 pmac_ide_kauai_selectproc(ide_drive_t *drive)
486 {
487 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
488
489 if (pmif == NULL)
490 return;
491
492 if (drive->select.b.unit & 0x01) {
493 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
494 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
495 } else {
496 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
497 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
498 }
499 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
500 }
501
502 /*
503 * Force an update of controller timing values for a given drive
504 */
505 static void
506 pmac_ide_do_update_timings(ide_drive_t *drive)
507 {
508 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
509
510 if (pmif == NULL)
511 return;
512
513 if (pmif->kind == controller_sh_ata6 ||
514 pmif->kind == controller_un_ata6 ||
515 pmif->kind == controller_k2_ata6)
516 pmac_ide_kauai_selectproc(drive);
517 else
518 pmac_ide_selectproc(drive);
519 }
520
521 static void
522 pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
523 {
524 u32 tmp;
525
526 writeb(value, (void __iomem *) port);
527 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
528 }
529
530 /*
531 * Send the SET_FEATURE IDE command to the drive and update drive->id with
532 * the new state. We currently don't use the generic routine as it used to
533 * cause various trouble, especially with older mediabays.
534 * This code is sometimes triggering a spurrious interrupt though, I need
535 * to sort that out sooner or later and see if I can finally get the
536 * common version to work properly in all cases
537 */
538 static int
539 pmac_ide_do_setfeature(ide_drive_t *drive, u8 command)
540 {
541 ide_hwif_t *hwif = HWIF(drive);
542 int result = 1;
543
544 disable_irq_nosync(hwif->irq);
545 udelay(1);
546 SELECT_DRIVE(drive);
547 SELECT_MASK(drive, 0);
548 udelay(1);
549 /* Get rid of pending error state */
550 (void) hwif->INB(IDE_STATUS_REG);
551 /* Timeout bumped for some powerbooks */
552 if (wait_for_ready(drive, 2000)) {
553 /* Timeout bumped for some powerbooks */
554 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
555 "before SET_FEATURE!\n", drive->name);
556 goto out;
557 }
558 udelay(10);
559 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
560 hwif->OUTB(command, IDE_NSECTOR_REG);
561 hwif->OUTB(SETFEATURES_XFER, IDE_FEATURE_REG);
562 hwif->OUTBSYNC(drive, WIN_SETFEATURES, IDE_COMMAND_REG);
563 udelay(1);
564 /* Timeout bumped for some powerbooks */
565 result = wait_for_ready(drive, 2000);
566 hwif->OUTB(drive->ctl, IDE_CONTROL_REG);
567 if (result)
568 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
569 "after SET_FEATURE !\n", drive->name);
570 out:
571 SELECT_MASK(drive, 0);
572 if (result == 0) {
573 drive->id->dma_ultra &= ~0xFF00;
574 drive->id->dma_mword &= ~0x0F00;
575 drive->id->dma_1word &= ~0x0F00;
576 switch(command) {
577 case XFER_UDMA_7:
578 drive->id->dma_ultra |= 0x8080; break;
579 case XFER_UDMA_6:
580 drive->id->dma_ultra |= 0x4040; break;
581 case XFER_UDMA_5:
582 drive->id->dma_ultra |= 0x2020; break;
583 case XFER_UDMA_4:
584 drive->id->dma_ultra |= 0x1010; break;
585 case XFER_UDMA_3:
586 drive->id->dma_ultra |= 0x0808; break;
587 case XFER_UDMA_2:
588 drive->id->dma_ultra |= 0x0404; break;
589 case XFER_UDMA_1:
590 drive->id->dma_ultra |= 0x0202; break;
591 case XFER_UDMA_0:
592 drive->id->dma_ultra |= 0x0101; break;
593 case XFER_MW_DMA_2:
594 drive->id->dma_mword |= 0x0404; break;
595 case XFER_MW_DMA_1:
596 drive->id->dma_mword |= 0x0202; break;
597 case XFER_MW_DMA_0:
598 drive->id->dma_mword |= 0x0101; break;
599 case XFER_SW_DMA_2:
600 drive->id->dma_1word |= 0x0404; break;
601 case XFER_SW_DMA_1:
602 drive->id->dma_1word |= 0x0202; break;
603 case XFER_SW_DMA_0:
604 drive->id->dma_1word |= 0x0101; break;
605 default: break;
606 }
607 if (!drive->init_speed)
608 drive->init_speed = command;
609 drive->current_speed = command;
610 }
611 enable_irq(hwif->irq);
612 return result;
613 }
614
615 /*
616 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
617 */
618 static void
619 pmac_ide_tuneproc(ide_drive_t *drive, u8 pio)
620 {
621 u32 *timings;
622 unsigned accessTicks, recTicks;
623 unsigned accessTime, recTime;
624 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
625 unsigned int cycle_time;
626
627 if (pmif == NULL)
628 return;
629
630 /* which drive is it ? */
631 timings = &pmif->timings[drive->select.b.unit & 0x01];
632
633 pio = ide_get_best_pio_mode(drive, pio, 4);
634 cycle_time = ide_pio_cycle_time(drive, pio);
635
636 switch (pmif->kind) {
637 case controller_sh_ata6: {
638 /* 133Mhz cell */
639 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
640 if (tr == 0)
641 return;
642 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
643 break;
644 }
645 case controller_un_ata6:
646 case controller_k2_ata6: {
647 /* 100Mhz cell */
648 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
649 if (tr == 0)
650 return;
651 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
652 break;
653 }
654 case controller_kl_ata4:
655 /* 66Mhz cell */
656 recTime = cycle_time - ide_pio_timings[pio].active_time
657 - ide_pio_timings[pio].setup_time;
658 recTime = max(recTime, 150U);
659 accessTime = ide_pio_timings[pio].active_time;
660 accessTime = max(accessTime, 150U);
661 accessTicks = SYSCLK_TICKS_66(accessTime);
662 accessTicks = min(accessTicks, 0x1fU);
663 recTicks = SYSCLK_TICKS_66(recTime);
664 recTicks = min(recTicks, 0x1fU);
665 *timings = ((*timings) & ~TR_66_PIO_MASK) |
666 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
667 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
668 break;
669 default: {
670 /* 33Mhz cell */
671 int ebit = 0;
672 recTime = cycle_time - ide_pio_timings[pio].active_time
673 - ide_pio_timings[pio].setup_time;
674 recTime = max(recTime, 150U);
675 accessTime = ide_pio_timings[pio].active_time;
676 accessTime = max(accessTime, 150U);
677 accessTicks = SYSCLK_TICKS(accessTime);
678 accessTicks = min(accessTicks, 0x1fU);
679 accessTicks = max(accessTicks, 4U);
680 recTicks = SYSCLK_TICKS(recTime);
681 recTicks = min(recTicks, 0x1fU);
682 recTicks = max(recTicks, 5U) - 4;
683 if (recTicks > 9) {
684 recTicks--; /* guess, but it's only for PIO0, so... */
685 ebit = 1;
686 }
687 *timings = ((*timings) & ~TR_33_PIO_MASK) |
688 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
689 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
690 if (ebit)
691 *timings |= TR_33_PIO_E;
692 break;
693 }
694 }
695
696 #ifdef IDE_PMAC_DEBUG
697 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
698 drive->name, pio, *timings);
699 #endif
700
701 if (drive->select.all == HWIF(drive)->INB(IDE_SELECT_REG))
702 pmac_ide_do_update_timings(drive);
703 }
704
705 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
706
707 /*
708 * Calculate KeyLargo ATA/66 UDMA timings
709 */
710 static int
711 set_timings_udma_ata4(u32 *timings, u8 speed)
712 {
713 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
714
715 if (speed > XFER_UDMA_4)
716 return 1;
717
718 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
719 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
720 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
721
722 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
723 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
724 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
725 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
726 TR_66_UDMA_EN;
727 #ifdef IDE_PMAC_DEBUG
728 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
729 speed & 0xf, *timings);
730 #endif
731
732 return 0;
733 }
734
735 /*
736 * Calculate Kauai ATA/100 UDMA timings
737 */
738 static int
739 set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
740 {
741 struct ide_timing *t = ide_timing_find_mode(speed);
742 u32 tr;
743
744 if (speed > XFER_UDMA_5 || t == NULL)
745 return 1;
746 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
747 if (tr == 0)
748 return 1;
749 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
750 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
751
752 return 0;
753 }
754
755 /*
756 * Calculate Shasta ATA/133 UDMA timings
757 */
758 static int
759 set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
760 {
761 struct ide_timing *t = ide_timing_find_mode(speed);
762 u32 tr;
763
764 if (speed > XFER_UDMA_6 || t == NULL)
765 return 1;
766 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
767 if (tr == 0)
768 return 1;
769 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
770 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
771
772 return 0;
773 }
774
775 /*
776 * Calculate MDMA timings for all cells
777 */
778 static int
779 set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
780 u8 speed, int drive_cycle_time)
781 {
782 int cycleTime, accessTime = 0, recTime = 0;
783 unsigned accessTicks, recTicks;
784 struct mdma_timings_t* tm = NULL;
785 int i;
786
787 /* Get default cycle time for mode */
788 switch(speed & 0xf) {
789 case 0: cycleTime = 480; break;
790 case 1: cycleTime = 150; break;
791 case 2: cycleTime = 120; break;
792 default:
793 return 1;
794 }
795 /* Adjust for drive */
796 if (drive_cycle_time && drive_cycle_time > cycleTime)
797 cycleTime = drive_cycle_time;
798 /* OHare limits according to some old Apple sources */
799 if ((intf_type == controller_ohare) && (cycleTime < 150))
800 cycleTime = 150;
801 /* Get the proper timing array for this controller */
802 switch(intf_type) {
803 case controller_sh_ata6:
804 case controller_un_ata6:
805 case controller_k2_ata6:
806 break;
807 case controller_kl_ata4:
808 tm = mdma_timings_66;
809 break;
810 case controller_kl_ata3:
811 tm = mdma_timings_33k;
812 break;
813 default:
814 tm = mdma_timings_33;
815 break;
816 }
817 if (tm != NULL) {
818 /* Lookup matching access & recovery times */
819 i = -1;
820 for (;;) {
821 if (tm[i+1].cycleTime < cycleTime)
822 break;
823 i++;
824 }
825 if (i < 0)
826 return 1;
827 cycleTime = tm[i].cycleTime;
828 accessTime = tm[i].accessTime;
829 recTime = tm[i].recoveryTime;
830
831 #ifdef IDE_PMAC_DEBUG
832 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
833 drive->name, cycleTime, accessTime, recTime);
834 #endif
835 }
836 switch(intf_type) {
837 case controller_sh_ata6: {
838 /* 133Mhz cell */
839 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
840 if (tr == 0)
841 return 1;
842 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
843 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
844 }
845 case controller_un_ata6:
846 case controller_k2_ata6: {
847 /* 100Mhz cell */
848 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
849 if (tr == 0)
850 return 1;
851 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
852 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
853 }
854 break;
855 case controller_kl_ata4:
856 /* 66Mhz cell */
857 accessTicks = SYSCLK_TICKS_66(accessTime);
858 accessTicks = min(accessTicks, 0x1fU);
859 accessTicks = max(accessTicks, 0x1U);
860 recTicks = SYSCLK_TICKS_66(recTime);
861 recTicks = min(recTicks, 0x1fU);
862 recTicks = max(recTicks, 0x3U);
863 /* Clear out mdma bits and disable udma */
864 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
865 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
866 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
867 break;
868 case controller_kl_ata3:
869 /* 33Mhz cell on KeyLargo */
870 accessTicks = SYSCLK_TICKS(accessTime);
871 accessTicks = max(accessTicks, 1U);
872 accessTicks = min(accessTicks, 0x1fU);
873 accessTime = accessTicks * IDE_SYSCLK_NS;
874 recTicks = SYSCLK_TICKS(recTime);
875 recTicks = max(recTicks, 1U);
876 recTicks = min(recTicks, 0x1fU);
877 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
878 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
879 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
880 break;
881 default: {
882 /* 33Mhz cell on others */
883 int halfTick = 0;
884 int origAccessTime = accessTime;
885 int origRecTime = recTime;
886
887 accessTicks = SYSCLK_TICKS(accessTime);
888 accessTicks = max(accessTicks, 1U);
889 accessTicks = min(accessTicks, 0x1fU);
890 accessTime = accessTicks * IDE_SYSCLK_NS;
891 recTicks = SYSCLK_TICKS(recTime);
892 recTicks = max(recTicks, 2U) - 1;
893 recTicks = min(recTicks, 0x1fU);
894 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
895 if ((accessTicks > 1) &&
896 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
897 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
898 halfTick = 1;
899 accessTicks--;
900 }
901 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
902 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
903 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
904 if (halfTick)
905 *timings |= TR_33_MDMA_HALFTICK;
906 }
907 }
908 #ifdef IDE_PMAC_DEBUG
909 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
910 drive->name, speed & 0xf, *timings);
911 #endif
912 return 0;
913 }
914 #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
915
916 /*
917 * Speedproc. This function is called by the core to set any of the standard
918 * timing (PIO, MDMA or UDMA) to both the drive and the controller.
919 * You may notice we don't use this function on normal "dma check" operation,
920 * our dedicated function is more precise as it uses the drive provided
921 * cycle time value. We should probably fix this one to deal with that too...
922 */
923 static int
924 pmac_ide_tune_chipset (ide_drive_t *drive, byte speed)
925 {
926 int unit = (drive->select.b.unit & 0x01);
927 int ret = 0;
928 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
929 u32 *timings, *timings2;
930
931 speed = ide_rate_filter(drive, speed);
932
933 if (pmif == NULL)
934 return 1;
935
936 timings = &pmif->timings[unit];
937 timings2 = &pmif->timings[unit+2];
938
939 switch(speed) {
940 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
941 case XFER_UDMA_6:
942 case XFER_UDMA_5:
943 case XFER_UDMA_4:
944 case XFER_UDMA_3:
945 case XFER_UDMA_2:
946 case XFER_UDMA_1:
947 case XFER_UDMA_0:
948 if (pmif->kind == controller_kl_ata4)
949 ret = set_timings_udma_ata4(timings, speed);
950 else if (pmif->kind == controller_un_ata6
951 || pmif->kind == controller_k2_ata6)
952 ret = set_timings_udma_ata6(timings, timings2, speed);
953 else if (pmif->kind == controller_sh_ata6)
954 ret = set_timings_udma_shasta(timings, timings2, speed);
955 else
956 ret = 1;
957 break;
958 case XFER_MW_DMA_2:
959 case XFER_MW_DMA_1:
960 case XFER_MW_DMA_0:
961 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
962 break;
963 case XFER_SW_DMA_2:
964 case XFER_SW_DMA_1:
965 case XFER_SW_DMA_0:
966 return 1;
967 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
968 case XFER_PIO_4:
969 case XFER_PIO_3:
970 case XFER_PIO_2:
971 case XFER_PIO_1:
972 case XFER_PIO_0:
973 pmac_ide_tuneproc(drive, speed & 0x07);
974 break;
975 default:
976 ret = 1;
977 }
978 if (ret)
979 return ret;
980
981 ret = pmac_ide_do_setfeature(drive, speed);
982 if (ret)
983 return ret;
984
985 pmac_ide_do_update_timings(drive);
986
987 return 0;
988 }
989
990 /*
991 * Blast some well known "safe" values to the timing registers at init or
992 * wakeup from sleep time, before we do real calculation
993 */
994 static void
995 sanitize_timings(pmac_ide_hwif_t *pmif)
996 {
997 unsigned int value, value2 = 0;
998
999 switch(pmif->kind) {
1000 case controller_sh_ata6:
1001 value = 0x0a820c97;
1002 value2 = 0x00033031;
1003 break;
1004 case controller_un_ata6:
1005 case controller_k2_ata6:
1006 value = 0x08618a92;
1007 value2 = 0x00002921;
1008 break;
1009 case controller_kl_ata4:
1010 value = 0x0008438c;
1011 break;
1012 case controller_kl_ata3:
1013 value = 0x00084526;
1014 break;
1015 case controller_heathrow:
1016 case controller_ohare:
1017 default:
1018 value = 0x00074526;
1019 break;
1020 }
1021 pmif->timings[0] = pmif->timings[1] = value;
1022 pmif->timings[2] = pmif->timings[3] = value2;
1023 }
1024
1025 unsigned long
1026 pmac_ide_get_base(int index)
1027 {
1028 return pmac_ide[index].regbase;
1029 }
1030
1031 int
1032 pmac_ide_check_base(unsigned long base)
1033 {
1034 int ix;
1035
1036 for (ix = 0; ix < MAX_HWIFS; ++ix)
1037 if (base == pmac_ide[ix].regbase)
1038 return ix;
1039 return -1;
1040 }
1041
1042 int
1043 pmac_ide_get_irq(unsigned long base)
1044 {
1045 int ix;
1046
1047 for (ix = 0; ix < MAX_HWIFS; ++ix)
1048 if (base == pmac_ide[ix].regbase)
1049 return pmac_ide[ix].irq;
1050 return 0;
1051 }
1052
1053 static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
1054
1055 dev_t __init
1056 pmac_find_ide_boot(char *bootdevice, int n)
1057 {
1058 int i;
1059
1060 /*
1061 * Look through the list of IDE interfaces for this one.
1062 */
1063 for (i = 0; i < pmac_ide_count; ++i) {
1064 char *name;
1065 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
1066 continue;
1067 name = pmac_ide[i].node->full_name;
1068 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
1069 /* XXX should cope with the 2nd drive as well... */
1070 return MKDEV(ide_majors[i], 0);
1071 }
1072 }
1073
1074 return 0;
1075 }
1076
1077 /* Suspend call back, should be called after the child devices
1078 * have actually been suspended
1079 */
1080 static int
1081 pmac_ide_do_suspend(ide_hwif_t *hwif)
1082 {
1083 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1084
1085 /* We clear the timings */
1086 pmif->timings[0] = 0;
1087 pmif->timings[1] = 0;
1088
1089 disable_irq(pmif->irq);
1090
1091 /* The media bay will handle itself just fine */
1092 if (pmif->mediabay)
1093 return 0;
1094
1095 /* Kauai has bus control FCRs directly here */
1096 if (pmif->kauai_fcr) {
1097 u32 fcr = readl(pmif->kauai_fcr);
1098 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
1099 writel(fcr, pmif->kauai_fcr);
1100 }
1101
1102 /* Disable the bus on older machines and the cell on kauai */
1103 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
1104 0);
1105
1106 return 0;
1107 }
1108
1109 /* Resume call back, should be called before the child devices
1110 * are resumed
1111 */
1112 static int
1113 pmac_ide_do_resume(ide_hwif_t *hwif)
1114 {
1115 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1116
1117 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1118 if (!pmif->mediabay) {
1119 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1120 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1121 msleep(10);
1122 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1123
1124 /* Kauai has it different */
1125 if (pmif->kauai_fcr) {
1126 u32 fcr = readl(pmif->kauai_fcr);
1127 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1128 writel(fcr, pmif->kauai_fcr);
1129 }
1130
1131 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1132 }
1133
1134 /* Sanitize drive timings */
1135 sanitize_timings(pmif);
1136
1137 enable_irq(pmif->irq);
1138
1139 return 0;
1140 }
1141
1142 /*
1143 * Setup, register & probe an IDE channel driven by this driver, this is
1144 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1145 * that ends up beeing free of any device is not kept around by this driver
1146 * (it is kept in 2.4). This introduce an interface numbering change on some
1147 * rare machines unfortunately, but it's better this way.
1148 */
1149 static int
1150 pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1151 {
1152 struct device_node *np = pmif->node;
1153 const int *bidp;
1154
1155 pmif->cable_80 = 0;
1156 pmif->broken_dma = pmif->broken_dma_warn = 0;
1157 if (of_device_is_compatible(np, "shasta-ata"))
1158 pmif->kind = controller_sh_ata6;
1159 else if (of_device_is_compatible(np, "kauai-ata"))
1160 pmif->kind = controller_un_ata6;
1161 else if (of_device_is_compatible(np, "K2-UATA"))
1162 pmif->kind = controller_k2_ata6;
1163 else if (of_device_is_compatible(np, "keylargo-ata")) {
1164 if (strcmp(np->name, "ata-4") == 0)
1165 pmif->kind = controller_kl_ata4;
1166 else
1167 pmif->kind = controller_kl_ata3;
1168 } else if (of_device_is_compatible(np, "heathrow-ata"))
1169 pmif->kind = controller_heathrow;
1170 else {
1171 pmif->kind = controller_ohare;
1172 pmif->broken_dma = 1;
1173 }
1174
1175 bidp = of_get_property(np, "AAPL,bus-id", NULL);
1176 pmif->aapl_bus_id = bidp ? *bidp : 0;
1177
1178 /* Get cable type from device-tree */
1179 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1180 || pmif->kind == controller_k2_ata6
1181 || pmif->kind == controller_sh_ata6) {
1182 const char* cable = of_get_property(np, "cable-type", NULL);
1183 if (cable && !strncmp(cable, "80-", 3))
1184 pmif->cable_80 = 1;
1185 }
1186 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1187 * they have a 80 conductor cable, this seem to be always the case unless
1188 * the user mucked around
1189 */
1190 if (of_device_is_compatible(np, "K2-UATA") ||
1191 of_device_is_compatible(np, "shasta-ata"))
1192 pmif->cable_80 = 1;
1193
1194 /* On Kauai-type controllers, we make sure the FCR is correct */
1195 if (pmif->kauai_fcr)
1196 writel(KAUAI_FCR_UATA_MAGIC |
1197 KAUAI_FCR_UATA_RESET_N |
1198 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1199
1200 pmif->mediabay = 0;
1201
1202 /* Make sure we have sane timings */
1203 sanitize_timings(pmif);
1204
1205 #ifndef CONFIG_PPC64
1206 /* XXX FIXME: Media bay stuff need re-organizing */
1207 if (np->parent && np->parent->name
1208 && strcasecmp(np->parent->name, "media-bay") == 0) {
1209 #ifdef CONFIG_PMAC_MEDIABAY
1210 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
1211 #endif /* CONFIG_PMAC_MEDIABAY */
1212 pmif->mediabay = 1;
1213 if (!bidp)
1214 pmif->aapl_bus_id = 1;
1215 } else if (pmif->kind == controller_ohare) {
1216 /* The code below is having trouble on some ohare machines
1217 * (timing related ?). Until I can put my hand on one of these
1218 * units, I keep the old way
1219 */
1220 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1221 } else
1222 #endif
1223 {
1224 /* This is necessary to enable IDE when net-booting */
1225 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1226 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1227 msleep(10);
1228 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1229 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1230 }
1231
1232 /* Setup MMIO ops */
1233 default_hwif_mmiops(hwif);
1234 hwif->OUTBSYNC = pmac_outbsync;
1235
1236 /* Tell common code _not_ to mess with resources */
1237 hwif->mmio = 1;
1238 hwif->hwif_data = pmif;
1239 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1240 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1241 hwif->chipset = ide_pmac;
1242 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1243 hwif->hold = pmif->mediabay;
1244 hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
1245 hwif->drives[0].unmask = 1;
1246 hwif->drives[1].unmask = 1;
1247 hwif->pio_mask = ATA_PIO4;
1248 hwif->tuneproc = pmac_ide_tuneproc;
1249 if (pmif->kind == controller_un_ata6
1250 || pmif->kind == controller_k2_ata6
1251 || pmif->kind == controller_sh_ata6)
1252 hwif->selectproc = pmac_ide_kauai_selectproc;
1253 else
1254 hwif->selectproc = pmac_ide_selectproc;
1255 hwif->speedproc = pmac_ide_tune_chipset;
1256
1257 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1258 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1259 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1260
1261 #ifdef CONFIG_PMAC_MEDIABAY
1262 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1263 hwif->noprobe = 0;
1264 #endif /* CONFIG_PMAC_MEDIABAY */
1265
1266 hwif->sg_max_nents = MAX_DCMDS;
1267
1268 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1269 /* has a DBDMA controller channel */
1270 if (pmif->dma_regs)
1271 pmac_ide_setup_dma(pmif, hwif);
1272 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1273
1274 /* We probe the hwif now */
1275 probe_hwif_init(hwif);
1276
1277 ide_proc_register_port(hwif);
1278
1279 return 0;
1280 }
1281
1282 /*
1283 * Attach to a macio probed interface
1284 */
1285 static int __devinit
1286 pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1287 {
1288 void __iomem *base;
1289 unsigned long regbase;
1290 int irq;
1291 ide_hwif_t *hwif;
1292 pmac_ide_hwif_t *pmif;
1293 int i, rc;
1294
1295 i = 0;
1296 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1297 || pmac_ide[i].node != NULL))
1298 ++i;
1299 if (i >= MAX_HWIFS) {
1300 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1301 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1302 return -ENODEV;
1303 }
1304
1305 pmif = &pmac_ide[i];
1306 hwif = &ide_hwifs[i];
1307
1308 if (macio_resource_count(mdev) == 0) {
1309 printk(KERN_WARNING "ide%d: no address for %s\n",
1310 i, mdev->ofdev.node->full_name);
1311 return -ENXIO;
1312 }
1313
1314 /* Request memory resource for IO ports */
1315 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1316 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1317 return -EBUSY;
1318 }
1319
1320 /* XXX This is bogus. Should be fixed in the registry by checking
1321 * the kind of host interrupt controller, a bit like gatwick
1322 * fixes in irq.c. That works well enough for the single case
1323 * where that happens though...
1324 */
1325 if (macio_irq_count(mdev) == 0) {
1326 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1327 i, mdev->ofdev.node->full_name);
1328 irq = irq_create_mapping(NULL, 13);
1329 } else
1330 irq = macio_irq(mdev, 0);
1331
1332 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1333 regbase = (unsigned long) base;
1334
1335 hwif->pci_dev = mdev->bus->pdev;
1336 hwif->gendev.parent = &mdev->ofdev.dev;
1337
1338 pmif->mdev = mdev;
1339 pmif->node = mdev->ofdev.node;
1340 pmif->regbase = regbase;
1341 pmif->irq = irq;
1342 pmif->kauai_fcr = NULL;
1343 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1344 if (macio_resource_count(mdev) >= 2) {
1345 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1346 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1347 else
1348 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1349 } else
1350 pmif->dma_regs = NULL;
1351 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1352 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1353
1354 rc = pmac_ide_setup_device(pmif, hwif);
1355 if (rc != 0) {
1356 /* The inteface is released to the common IDE layer */
1357 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1358 iounmap(base);
1359 if (pmif->dma_regs)
1360 iounmap(pmif->dma_regs);
1361 memset(pmif, 0, sizeof(*pmif));
1362 macio_release_resource(mdev, 0);
1363 if (pmif->dma_regs)
1364 macio_release_resource(mdev, 1);
1365 }
1366
1367 return rc;
1368 }
1369
1370 static int
1371 pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1372 {
1373 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1374 int rc = 0;
1375
1376 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1377 && mesg.event == PM_EVENT_SUSPEND) {
1378 rc = pmac_ide_do_suspend(hwif);
1379 if (rc == 0)
1380 mdev->ofdev.dev.power.power_state = mesg;
1381 }
1382
1383 return rc;
1384 }
1385
1386 static int
1387 pmac_ide_macio_resume(struct macio_dev *mdev)
1388 {
1389 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1390 int rc = 0;
1391
1392 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1393 rc = pmac_ide_do_resume(hwif);
1394 if (rc == 0)
1395 mdev->ofdev.dev.power.power_state = PMSG_ON;
1396 }
1397
1398 return rc;
1399 }
1400
1401 /*
1402 * Attach to a PCI probed interface
1403 */
1404 static int __devinit
1405 pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1406 {
1407 ide_hwif_t *hwif;
1408 struct device_node *np;
1409 pmac_ide_hwif_t *pmif;
1410 void __iomem *base;
1411 unsigned long rbase, rlen;
1412 int i, rc;
1413
1414 np = pci_device_to_OF_node(pdev);
1415 if (np == NULL) {
1416 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1417 return -ENODEV;
1418 }
1419 i = 0;
1420 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1421 || pmac_ide[i].node != NULL))
1422 ++i;
1423 if (i >= MAX_HWIFS) {
1424 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1425 printk(KERN_ERR " %s\n", np->full_name);
1426 return -ENODEV;
1427 }
1428
1429 pmif = &pmac_ide[i];
1430 hwif = &ide_hwifs[i];
1431
1432 if (pci_enable_device(pdev)) {
1433 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1434 i, np->full_name);
1435 return -ENXIO;
1436 }
1437 pci_set_master(pdev);
1438
1439 if (pci_request_regions(pdev, "Kauai ATA")) {
1440 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1441 i, np->full_name);
1442 return -ENXIO;
1443 }
1444
1445 hwif->pci_dev = pdev;
1446 hwif->gendev.parent = &pdev->dev;
1447 pmif->mdev = NULL;
1448 pmif->node = np;
1449
1450 rbase = pci_resource_start(pdev, 0);
1451 rlen = pci_resource_len(pdev, 0);
1452
1453 base = ioremap(rbase, rlen);
1454 pmif->regbase = (unsigned long) base + 0x2000;
1455 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1456 pmif->dma_regs = base + 0x1000;
1457 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1458 pmif->kauai_fcr = base;
1459 pmif->irq = pdev->irq;
1460
1461 pci_set_drvdata(pdev, hwif);
1462
1463 rc = pmac_ide_setup_device(pmif, hwif);
1464 if (rc != 0) {
1465 /* The inteface is released to the common IDE layer */
1466 pci_set_drvdata(pdev, NULL);
1467 iounmap(base);
1468 memset(pmif, 0, sizeof(*pmif));
1469 pci_release_regions(pdev);
1470 }
1471
1472 return rc;
1473 }
1474
1475 static int
1476 pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1477 {
1478 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1479 int rc = 0;
1480
1481 if (mesg.event != pdev->dev.power.power_state.event
1482 && mesg.event == PM_EVENT_SUSPEND) {
1483 rc = pmac_ide_do_suspend(hwif);
1484 if (rc == 0)
1485 pdev->dev.power.power_state = mesg;
1486 }
1487
1488 return rc;
1489 }
1490
1491 static int
1492 pmac_ide_pci_resume(struct pci_dev *pdev)
1493 {
1494 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1495 int rc = 0;
1496
1497 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1498 rc = pmac_ide_do_resume(hwif);
1499 if (rc == 0)
1500 pdev->dev.power.power_state = PMSG_ON;
1501 }
1502
1503 return rc;
1504 }
1505
1506 static struct of_device_id pmac_ide_macio_match[] =
1507 {
1508 {
1509 .name = "IDE",
1510 },
1511 {
1512 .name = "ATA",
1513 },
1514 {
1515 .type = "ide",
1516 },
1517 {
1518 .type = "ata",
1519 },
1520 {},
1521 };
1522
1523 static struct macio_driver pmac_ide_macio_driver =
1524 {
1525 .name = "ide-pmac",
1526 .match_table = pmac_ide_macio_match,
1527 .probe = pmac_ide_macio_attach,
1528 .suspend = pmac_ide_macio_suspend,
1529 .resume = pmac_ide_macio_resume,
1530 };
1531
1532 static struct pci_device_id pmac_ide_pci_match[] = {
1533 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA,
1534 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1535 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100,
1536 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1537 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100,
1538 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1539 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1540 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1541 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA,
1542 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1543 {},
1544 };
1545
1546 static struct pci_driver pmac_ide_pci_driver = {
1547 .name = "ide-pmac",
1548 .id_table = pmac_ide_pci_match,
1549 .probe = pmac_ide_pci_attach,
1550 .suspend = pmac_ide_pci_suspend,
1551 .resume = pmac_ide_pci_resume,
1552 };
1553 MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1554
1555 int __init pmac_ide_probe(void)
1556 {
1557 int error;
1558
1559 if (!machine_is(powermac))
1560 return -ENODEV;
1561
1562 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1563 error = pci_register_driver(&pmac_ide_pci_driver);
1564 if (error)
1565 goto out;
1566 error = macio_register_driver(&pmac_ide_macio_driver);
1567 if (error) {
1568 pci_unregister_driver(&pmac_ide_pci_driver);
1569 goto out;
1570 }
1571 #else
1572 error = macio_register_driver(&pmac_ide_macio_driver);
1573 if (error)
1574 goto out;
1575 error = pci_register_driver(&pmac_ide_pci_driver);
1576 if (error) {
1577 macio_unregister_driver(&pmac_ide_macio_driver);
1578 goto out;
1579 }
1580 #endif
1581 out:
1582 return error;
1583 }
1584
1585 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1586
1587 /*
1588 * pmac_ide_build_dmatable builds the DBDMA command list
1589 * for a transfer and sets the DBDMA channel to point to it.
1590 */
1591 static int
1592 pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1593 {
1594 struct dbdma_cmd *table;
1595 int i, count = 0;
1596 ide_hwif_t *hwif = HWIF(drive);
1597 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1598 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1599 struct scatterlist *sg;
1600 int wr = (rq_data_dir(rq) == WRITE);
1601
1602 /* DMA table is already aligned */
1603 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1604
1605 /* Make sure DMA controller is stopped (necessary ?) */
1606 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1607 while (readl(&dma->status) & RUN)
1608 udelay(1);
1609
1610 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1611
1612 if (!i)
1613 return 0;
1614
1615 /* Build DBDMA commands list */
1616 sg = hwif->sg_table;
1617 while (i && sg_dma_len(sg)) {
1618 u32 cur_addr;
1619 u32 cur_len;
1620
1621 cur_addr = sg_dma_address(sg);
1622 cur_len = sg_dma_len(sg);
1623
1624 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1625 if (pmif->broken_dma_warn == 0) {
1626 printk(KERN_WARNING "%s: DMA on non aligned address,"
1627 "switching to PIO on Ohare chipset\n", drive->name);
1628 pmif->broken_dma_warn = 1;
1629 }
1630 goto use_pio_instead;
1631 }
1632 while (cur_len) {
1633 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1634
1635 if (count++ >= MAX_DCMDS) {
1636 printk(KERN_WARNING "%s: DMA table too small\n",
1637 drive->name);
1638 goto use_pio_instead;
1639 }
1640 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1641 st_le16(&table->req_count, tc);
1642 st_le32(&table->phy_addr, cur_addr);
1643 table->cmd_dep = 0;
1644 table->xfer_status = 0;
1645 table->res_count = 0;
1646 cur_addr += tc;
1647 cur_len -= tc;
1648 ++table;
1649 }
1650 sg++;
1651 i--;
1652 }
1653
1654 /* convert the last command to an input/output last command */
1655 if (count) {
1656 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1657 /* add the stop command to the end of the list */
1658 memset(table, 0, sizeof(struct dbdma_cmd));
1659 st_le16(&table->command, DBDMA_STOP);
1660 mb();
1661 writel(hwif->dmatable_dma, &dma->cmdptr);
1662 return 1;
1663 }
1664
1665 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1666 use_pio_instead:
1667 pci_unmap_sg(hwif->pci_dev,
1668 hwif->sg_table,
1669 hwif->sg_nents,
1670 hwif->sg_dma_direction);
1671 return 0; /* revert to PIO for this request */
1672 }
1673
1674 /* Teardown mappings after DMA has completed. */
1675 static void
1676 pmac_ide_destroy_dmatable (ide_drive_t *drive)
1677 {
1678 ide_hwif_t *hwif = drive->hwif;
1679 struct pci_dev *dev = HWIF(drive)->pci_dev;
1680 struct scatterlist *sg = hwif->sg_table;
1681 int nents = hwif->sg_nents;
1682
1683 if (nents) {
1684 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1685 hwif->sg_nents = 0;
1686 }
1687 }
1688
1689 /*
1690 * Pick up best MDMA timing for the drive and apply it
1691 */
1692 static int
1693 pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1694 {
1695 ide_hwif_t *hwif = HWIF(drive);
1696 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1697 int drive_cycle_time;
1698 struct hd_driveid *id = drive->id;
1699 u32 *timings, *timings2;
1700 u32 timing_local[2];
1701 int ret;
1702
1703 /* which drive is it ? */
1704 timings = &pmif->timings[drive->select.b.unit & 0x01];
1705 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1706
1707 /* Check if drive provide explicit cycle time */
1708 if ((id->field_valid & 2) && (id->eide_dma_time))
1709 drive_cycle_time = id->eide_dma_time;
1710 else
1711 drive_cycle_time = 0;
1712
1713 /* Copy timings to local image */
1714 timing_local[0] = *timings;
1715 timing_local[1] = *timings2;
1716
1717 /* Calculate controller timings */
1718 ret = set_timings_mdma( drive, pmif->kind,
1719 &timing_local[0],
1720 &timing_local[1],
1721 mode,
1722 drive_cycle_time);
1723 if (ret)
1724 return 0;
1725
1726 /* Set feature on drive */
1727 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
1728 ret = pmac_ide_do_setfeature(drive, mode);
1729 if (ret) {
1730 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1731 return 0;
1732 }
1733
1734 /* Apply timings to controller */
1735 *timings = timing_local[0];
1736 *timings2 = timing_local[1];
1737
1738 return 1;
1739 }
1740
1741 /*
1742 * Pick up best UDMA timing for the drive and apply it
1743 */
1744 static int
1745 pmac_ide_udma_enable(ide_drive_t *drive, u16 mode)
1746 {
1747 ide_hwif_t *hwif = HWIF(drive);
1748 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1749 u32 *timings, *timings2;
1750 u32 timing_local[2];
1751 int ret;
1752
1753 /* which drive is it ? */
1754 timings = &pmif->timings[drive->select.b.unit & 0x01];
1755 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1756
1757 /* Copy timings to local image */
1758 timing_local[0] = *timings;
1759 timing_local[1] = *timings2;
1760
1761 /* Calculate timings for interface */
1762 if (pmif->kind == controller_un_ata6
1763 || pmif->kind == controller_k2_ata6)
1764 ret = set_timings_udma_ata6( &timing_local[0],
1765 &timing_local[1],
1766 mode);
1767 else if (pmif->kind == controller_sh_ata6)
1768 ret = set_timings_udma_shasta( &timing_local[0],
1769 &timing_local[1],
1770 mode);
1771 else
1772 ret = set_timings_udma_ata4(&timing_local[0], mode);
1773 if (ret)
1774 return 0;
1775
1776 /* Set feature on drive */
1777 printk(KERN_INFO "%s: Enabling Ultra DMA %d\n", drive->name, mode & 0x0f);
1778 ret = pmac_ide_do_setfeature(drive, mode);
1779 if (ret) {
1780 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1781 return 0;
1782 }
1783
1784 /* Apply timings to controller */
1785 *timings = timing_local[0];
1786 *timings2 = timing_local[1];
1787
1788 return 1;
1789 }
1790
1791 /*
1792 * Check what is the best DMA timing setting for the drive and
1793 * call appropriate functions to apply it.
1794 */
1795 static int
1796 pmac_ide_dma_check(ide_drive_t *drive)
1797 {
1798 struct hd_driveid *id = drive->id;
1799 ide_hwif_t *hwif = HWIF(drive);
1800 int enable = 1;
1801 drive->using_dma = 0;
1802
1803 if (drive->media == ide_floppy)
1804 enable = 0;
1805 if (((id->capability & 1) == 0) && !__ide_dma_good_drive(drive))
1806 enable = 0;
1807 if (__ide_dma_bad_drive(drive))
1808 enable = 0;
1809
1810 if (enable) {
1811 u8 mode = ide_max_dma_mode(drive);
1812
1813 if (mode >= XFER_UDMA_0)
1814 drive->using_dma = pmac_ide_udma_enable(drive, mode);
1815 else if (mode >= XFER_MW_DMA_0)
1816 drive->using_dma = pmac_ide_mdma_enable(drive, mode);
1817 hwif->OUTB(0, IDE_CONTROL_REG);
1818 /* Apply settings to controller */
1819 pmac_ide_do_update_timings(drive);
1820 }
1821 return 0;
1822 }
1823
1824 /*
1825 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1826 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1827 */
1828 static int
1829 pmac_ide_dma_setup(ide_drive_t *drive)
1830 {
1831 ide_hwif_t *hwif = HWIF(drive);
1832 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1833 struct request *rq = HWGROUP(drive)->rq;
1834 u8 unit = (drive->select.b.unit & 0x01);
1835 u8 ata4;
1836
1837 if (pmif == NULL)
1838 return 1;
1839 ata4 = (pmif->kind == controller_kl_ata4);
1840
1841 if (!pmac_ide_build_dmatable(drive, rq)) {
1842 ide_map_sg(drive, rq);
1843 return 1;
1844 }
1845
1846 /* Apple adds 60ns to wrDataSetup on reads */
1847 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1848 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1849 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1850 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1851 }
1852
1853 drive->waiting_for_dma = 1;
1854
1855 return 0;
1856 }
1857
1858 static void
1859 pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1860 {
1861 /* issue cmd to drive */
1862 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1863 }
1864
1865 /*
1866 * Kick the DMA controller into life after the DMA command has been issued
1867 * to the drive.
1868 */
1869 static void
1870 pmac_ide_dma_start(ide_drive_t *drive)
1871 {
1872 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1873 volatile struct dbdma_regs __iomem *dma;
1874
1875 dma = pmif->dma_regs;
1876
1877 writel((RUN << 16) | RUN, &dma->control);
1878 /* Make sure it gets to the controller right now */
1879 (void)readl(&dma->control);
1880 }
1881
1882 /*
1883 * After a DMA transfer, make sure the controller is stopped
1884 */
1885 static int
1886 pmac_ide_dma_end (ide_drive_t *drive)
1887 {
1888 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1889 volatile struct dbdma_regs __iomem *dma;
1890 u32 dstat;
1891
1892 if (pmif == NULL)
1893 return 0;
1894 dma = pmif->dma_regs;
1895
1896 drive->waiting_for_dma = 0;
1897 dstat = readl(&dma->status);
1898 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1899 pmac_ide_destroy_dmatable(drive);
1900 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1901 * in theory, but with ATAPI decices doing buffer underruns, that would
1902 * cause us to disable DMA, which isn't what we want
1903 */
1904 return (dstat & (RUN|DEAD)) != RUN;
1905 }
1906
1907 /*
1908 * Check out that the interrupt we got was for us. We can't always know this
1909 * for sure with those Apple interfaces (well, we could on the recent ones but
1910 * that's not implemented yet), on the other hand, we don't have shared interrupts
1911 * so it's not really a problem
1912 */
1913 static int
1914 pmac_ide_dma_test_irq (ide_drive_t *drive)
1915 {
1916 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1917 volatile struct dbdma_regs __iomem *dma;
1918 unsigned long status, timeout;
1919
1920 if (pmif == NULL)
1921 return 0;
1922 dma = pmif->dma_regs;
1923
1924 /* We have to things to deal with here:
1925 *
1926 * - The dbdma won't stop if the command was started
1927 * but completed with an error without transferring all
1928 * datas. This happens when bad blocks are met during
1929 * a multi-block transfer.
1930 *
1931 * - The dbdma fifo hasn't yet finished flushing to
1932 * to system memory when the disk interrupt occurs.
1933 *
1934 */
1935
1936 /* If ACTIVE is cleared, the STOP command have passed and
1937 * transfer is complete.
1938 */
1939 status = readl(&dma->status);
1940 if (!(status & ACTIVE))
1941 return 1;
1942 if (!drive->waiting_for_dma)
1943 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1944 called while not waiting\n", HWIF(drive)->index);
1945
1946 /* If dbdma didn't execute the STOP command yet, the
1947 * active bit is still set. We consider that we aren't
1948 * sharing interrupts (which is hopefully the case with
1949 * those controllers) and so we just try to flush the
1950 * channel for pending data in the fifo
1951 */
1952 udelay(1);
1953 writel((FLUSH << 16) | FLUSH, &dma->control);
1954 timeout = 0;
1955 for (;;) {
1956 udelay(1);
1957 status = readl(&dma->status);
1958 if ((status & FLUSH) == 0)
1959 break;
1960 if (++timeout > 100) {
1961 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1962 timeout flushing channel\n", HWIF(drive)->index);
1963 break;
1964 }
1965 }
1966 return 1;
1967 }
1968
1969 static void pmac_ide_dma_host_off(ide_drive_t *drive)
1970 {
1971 }
1972
1973 static void pmac_ide_dma_host_on(ide_drive_t *drive)
1974 {
1975 }
1976
1977 static void
1978 pmac_ide_dma_lost_irq (ide_drive_t *drive)
1979 {
1980 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1981 volatile struct dbdma_regs __iomem *dma;
1982 unsigned long status;
1983
1984 if (pmif == NULL)
1985 return;
1986 dma = pmif->dma_regs;
1987
1988 status = readl(&dma->status);
1989 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1990 }
1991
1992 /*
1993 * Allocate the data structures needed for using DMA with an interface
1994 * and fill the proper list of functions pointers
1995 */
1996 static void __init
1997 pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1998 {
1999 /* We won't need pci_dev if we switch to generic consistent
2000 * DMA routines ...
2001 */
2002 if (hwif->pci_dev == NULL)
2003 return;
2004 /*
2005 * Allocate space for the DBDMA commands.
2006 * The +2 is +1 for the stop command and +1 to allow for
2007 * aligning the start address to a multiple of 16 bytes.
2008 */
2009 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
2010 hwif->pci_dev,
2011 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
2012 &hwif->dmatable_dma);
2013 if (pmif->dma_table_cpu == NULL) {
2014 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
2015 hwif->name);
2016 return;
2017 }
2018
2019 hwif->dma_off_quietly = &ide_dma_off_quietly;
2020 hwif->ide_dma_on = &__ide_dma_on;
2021 hwif->ide_dma_check = &pmac_ide_dma_check;
2022 hwif->dma_setup = &pmac_ide_dma_setup;
2023 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
2024 hwif->dma_start = &pmac_ide_dma_start;
2025 hwif->ide_dma_end = &pmac_ide_dma_end;
2026 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
2027 hwif->dma_host_off = &pmac_ide_dma_host_off;
2028 hwif->dma_host_on = &pmac_ide_dma_host_on;
2029 hwif->dma_timeout = &ide_dma_timeout;
2030 hwif->dma_lost_irq = &pmac_ide_dma_lost_irq;
2031
2032 hwif->atapi_dma = 1;
2033 switch(pmif->kind) {
2034 case controller_sh_ata6:
2035 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
2036 hwif->mwdma_mask = 0x07;
2037 hwif->swdma_mask = 0x00;
2038 break;
2039 case controller_un_ata6:
2040 case controller_k2_ata6:
2041 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
2042 hwif->mwdma_mask = 0x07;
2043 hwif->swdma_mask = 0x00;
2044 break;
2045 case controller_kl_ata4:
2046 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
2047 hwif->mwdma_mask = 0x07;
2048 hwif->swdma_mask = 0x00;
2049 break;
2050 default:
2051 hwif->ultra_mask = 0x00;
2052 hwif->mwdma_mask = 0x07;
2053 hwif->swdma_mask = 0x00;
2054 break;
2055 }
2056 }
2057
2058 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Linux kernel - Deliverables
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