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ide: move ide_rate_filter() calls to the upper layer (take 2)
[deliverable/linux.git] / drivers / ide / ppc / pmac.c
1 /*
2 * linux/drivers/ide/ppc/pmac.c
3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/pci.h>
33 #include <linux/adb.h>
34 #include <linux/pmu.h>
35 #include <linux/scatterlist.h>
36
37 #include <asm/prom.h>
38 #include <asm/io.h>
39 #include <asm/dbdma.h>
40 #include <asm/ide.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/machdep.h>
43 #include <asm/pmac_feature.h>
44 #include <asm/sections.h>
45 #include <asm/irq.h>
46
47 #ifndef CONFIG_PPC64
48 #include <asm/mediabay.h>
49 #endif
50
51 #include "../ide-timing.h"
52
53 #undef IDE_PMAC_DEBUG
54
55 #define DMA_WAIT_TIMEOUT 50
56
57 typedef struct pmac_ide_hwif {
58 unsigned long regbase;
59 int irq;
60 int kind;
61 int aapl_bus_id;
62 unsigned cable_80 : 1;
63 unsigned mediabay : 1;
64 unsigned broken_dma : 1;
65 unsigned broken_dma_warn : 1;
66 struct device_node* node;
67 struct macio_dev *mdev;
68 u32 timings[4];
69 volatile u32 __iomem * *kauai_fcr;
70 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
71 /* Those fields are duplicating what is in hwif. We currently
72 * can't use the hwif ones because of some assumptions that are
73 * beeing done by the generic code about the kind of dma controller
74 * and format of the dma table. This will have to be fixed though.
75 */
76 volatile struct dbdma_regs __iomem * dma_regs;
77 struct dbdma_cmd* dma_table_cpu;
78 #endif
79
80 } pmac_ide_hwif_t;
81
82 static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
83 static int pmac_ide_count;
84
85 enum {
86 controller_ohare, /* OHare based */
87 controller_heathrow, /* Heathrow/Paddington */
88 controller_kl_ata3, /* KeyLargo ATA-3 */
89 controller_kl_ata4, /* KeyLargo ATA-4 */
90 controller_un_ata6, /* UniNorth2 ATA-6 */
91 controller_k2_ata6, /* K2 ATA-6 */
92 controller_sh_ata6, /* Shasta ATA-6 */
93 };
94
95 static const char* model_name[] = {
96 "OHare ATA", /* OHare based */
97 "Heathrow ATA", /* Heathrow/Paddington */
98 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
99 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
100 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
101 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
102 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
103 };
104
105 /*
106 * Extra registers, both 32-bit little-endian
107 */
108 #define IDE_TIMING_CONFIG 0x200
109 #define IDE_INTERRUPT 0x300
110
111 /* Kauai (U2) ATA has different register setup */
112 #define IDE_KAUAI_PIO_CONFIG 0x200
113 #define IDE_KAUAI_ULTRA_CONFIG 0x210
114 #define IDE_KAUAI_POLL_CONFIG 0x220
115
116 /*
117 * Timing configuration register definitions
118 */
119
120 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
121 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
122 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
123 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
124 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
125
126 /* 133Mhz cell, found in shasta.
127 * See comments about 100 Mhz Uninorth 2...
128 * Note that PIO_MASK and MDMA_MASK seem to overlap
129 */
130 #define TR_133_PIOREG_PIO_MASK 0xff000fff
131 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
132 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
133 #define TR_133_UDMAREG_UDMA_EN 0x00000001
134
135 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
136 * this one yet, it appears as a pci device (106b/0033) on uninorth
137 * internal PCI bus and it's clock is controlled like gem or fw. It
138 * appears to be an evolution of keylargo ATA4 with a timing register
139 * extended to 2 32bits registers and a similar DBDMA channel. Other
140 * registers seem to exist but I can't tell much about them.
141 *
142 * So far, I'm using pre-calculated tables for this extracted from
143 * the values used by the MacOS X driver.
144 *
145 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
146 * register controls the UDMA timings. At least, it seems bit 0
147 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
148 * cycle time in units of 10ns. Bits 8..15 are used by I don't
149 * know their meaning yet
150 */
151 #define TR_100_PIOREG_PIO_MASK 0xff000fff
152 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
153 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
154 #define TR_100_UDMAREG_UDMA_EN 0x00000001
155
156
157 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
158 * 40 connector cable and to 4 on 80 connector one.
159 * Clock unit is 15ns (66Mhz)
160 *
161 * 3 Values can be programmed:
162 * - Write data setup, which appears to match the cycle time. They
163 * also call it DIOW setup.
164 * - Ready to pause time (from spec)
165 * - Address setup. That one is weird. I don't see where exactly
166 * it fits in UDMA cycles, I got it's name from an obscure piece
167 * of commented out code in Darwin. They leave it to 0, we do as
168 * well, despite a comment that would lead to think it has a
169 * min value of 45ns.
170 * Apple also add 60ns to the write data setup (or cycle time ?) on
171 * reads.
172 */
173 #define TR_66_UDMA_MASK 0xfff00000
174 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
175 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
176 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
177 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
178 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
179 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
180 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
181 #define TR_66_MDMA_MASK 0x000ffc00
182 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
183 #define TR_66_MDMA_RECOVERY_SHIFT 15
184 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
185 #define TR_66_MDMA_ACCESS_SHIFT 10
186 #define TR_66_PIO_MASK 0x000003ff
187 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
188 #define TR_66_PIO_RECOVERY_SHIFT 5
189 #define TR_66_PIO_ACCESS_MASK 0x0000001f
190 #define TR_66_PIO_ACCESS_SHIFT 0
191
192 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
193 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
194 *
195 * The access time and recovery time can be programmed. Some older
196 * Darwin code base limit OHare to 150ns cycle time. I decided to do
197 * the same here fore safety against broken old hardware ;)
198 * The HalfTick bit, when set, adds half a clock (15ns) to the access
199 * time and removes one from recovery. It's not supported on KeyLargo
200 * implementation afaik. The E bit appears to be set for PIO mode 0 and
201 * is used to reach long timings used in this mode.
202 */
203 #define TR_33_MDMA_MASK 0x003ff800
204 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
205 #define TR_33_MDMA_RECOVERY_SHIFT 16
206 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
207 #define TR_33_MDMA_ACCESS_SHIFT 11
208 #define TR_33_MDMA_HALFTICK 0x00200000
209 #define TR_33_PIO_MASK 0x000007ff
210 #define TR_33_PIO_E 0x00000400
211 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
212 #define TR_33_PIO_RECOVERY_SHIFT 5
213 #define TR_33_PIO_ACCESS_MASK 0x0000001f
214 #define TR_33_PIO_ACCESS_SHIFT 0
215
216 /*
217 * Interrupt register definitions
218 */
219 #define IDE_INTR_DMA 0x80000000
220 #define IDE_INTR_DEVICE 0x40000000
221
222 /*
223 * FCR Register on Kauai. Not sure what bit 0x4 is ...
224 */
225 #define KAUAI_FCR_UATA_MAGIC 0x00000004
226 #define KAUAI_FCR_UATA_RESET_N 0x00000002
227 #define KAUAI_FCR_UATA_ENABLE 0x00000001
228
229 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
230
231 /* Rounded Multiword DMA timings
232 *
233 * I gave up finding a generic formula for all controller
234 * types and instead, built tables based on timing values
235 * used by Apple in Darwin's implementation.
236 */
237 struct mdma_timings_t {
238 int accessTime;
239 int recoveryTime;
240 int cycleTime;
241 };
242
243 struct mdma_timings_t mdma_timings_33[] =
244 {
245 { 240, 240, 480 },
246 { 180, 180, 360 },
247 { 135, 135, 270 },
248 { 120, 120, 240 },
249 { 105, 105, 210 },
250 { 90, 90, 180 },
251 { 75, 75, 150 },
252 { 75, 45, 120 },
253 { 0, 0, 0 }
254 };
255
256 struct mdma_timings_t mdma_timings_33k[] =
257 {
258 { 240, 240, 480 },
259 { 180, 180, 360 },
260 { 150, 150, 300 },
261 { 120, 120, 240 },
262 { 90, 120, 210 },
263 { 90, 90, 180 },
264 { 90, 60, 150 },
265 { 90, 30, 120 },
266 { 0, 0, 0 }
267 };
268
269 struct mdma_timings_t mdma_timings_66[] =
270 {
271 { 240, 240, 480 },
272 { 180, 180, 360 },
273 { 135, 135, 270 },
274 { 120, 120, 240 },
275 { 105, 105, 210 },
276 { 90, 90, 180 },
277 { 90, 75, 165 },
278 { 75, 45, 120 },
279 { 0, 0, 0 }
280 };
281
282 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
283 struct {
284 int addrSetup; /* ??? */
285 int rdy2pause;
286 int wrDataSetup;
287 } kl66_udma_timings[] =
288 {
289 { 0, 180, 120 }, /* Mode 0 */
290 { 0, 150, 90 }, /* 1 */
291 { 0, 120, 60 }, /* 2 */
292 { 0, 90, 45 }, /* 3 */
293 { 0, 90, 30 } /* 4 */
294 };
295
296 /* UniNorth 2 ATA/100 timings */
297 struct kauai_timing {
298 int cycle_time;
299 u32 timing_reg;
300 };
301
302 static struct kauai_timing kauai_pio_timings[] =
303 {
304 { 930 , 0x08000fff },
305 { 600 , 0x08000a92 },
306 { 383 , 0x0800060f },
307 { 360 , 0x08000492 },
308 { 330 , 0x0800048f },
309 { 300 , 0x080003cf },
310 { 270 , 0x080003cc },
311 { 240 , 0x0800038b },
312 { 239 , 0x0800030c },
313 { 180 , 0x05000249 },
314 { 120 , 0x04000148 }
315 };
316
317 static struct kauai_timing kauai_mdma_timings[] =
318 {
319 { 1260 , 0x00fff000 },
320 { 480 , 0x00618000 },
321 { 360 , 0x00492000 },
322 { 270 , 0x0038e000 },
323 { 240 , 0x0030c000 },
324 { 210 , 0x002cb000 },
325 { 180 , 0x00249000 },
326 { 150 , 0x00209000 },
327 { 120 , 0x00148000 },
328 { 0 , 0 },
329 };
330
331 static struct kauai_timing kauai_udma_timings[] =
332 {
333 { 120 , 0x000070c0 },
334 { 90 , 0x00005d80 },
335 { 60 , 0x00004a60 },
336 { 45 , 0x00003a50 },
337 { 30 , 0x00002a30 },
338 { 20 , 0x00002921 },
339 { 0 , 0 },
340 };
341
342 static struct kauai_timing shasta_pio_timings[] =
343 {
344 { 930 , 0x08000fff },
345 { 600 , 0x0A000c97 },
346 { 383 , 0x07000712 },
347 { 360 , 0x040003cd },
348 { 330 , 0x040003cd },
349 { 300 , 0x040003cd },
350 { 270 , 0x040003cd },
351 { 240 , 0x040003cd },
352 { 239 , 0x040003cd },
353 { 180 , 0x0400028b },
354 { 120 , 0x0400010a }
355 };
356
357 static struct kauai_timing shasta_mdma_timings[] =
358 {
359 { 1260 , 0x00fff000 },
360 { 480 , 0x00820800 },
361 { 360 , 0x00820800 },
362 { 270 , 0x00820800 },
363 { 240 , 0x00820800 },
364 { 210 , 0x00820800 },
365 { 180 , 0x00820800 },
366 { 150 , 0x0028b000 },
367 { 120 , 0x001ca000 },
368 { 0 , 0 },
369 };
370
371 static struct kauai_timing shasta_udma133_timings[] =
372 {
373 { 120 , 0x00035901, },
374 { 90 , 0x000348b1, },
375 { 60 , 0x00033881, },
376 { 45 , 0x00033861, },
377 { 30 , 0x00033841, },
378 { 20 , 0x00033031, },
379 { 15 , 0x00033021, },
380 { 0 , 0 },
381 };
382
383
384 static inline u32
385 kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
386 {
387 int i;
388
389 for (i=0; table[i].cycle_time; i++)
390 if (cycle_time > table[i+1].cycle_time)
391 return table[i].timing_reg;
392 return 0;
393 }
394
395 /* allow up to 256 DBDMA commands per xfer */
396 #define MAX_DCMDS 256
397
398 /*
399 * Wait 1s for disk to answer on IDE bus after a hard reset
400 * of the device (via GPIO/FCR).
401 *
402 * Some devices seem to "pollute" the bus even after dropping
403 * the BSY bit (typically some combo drives slave on the UDMA
404 * bus) after a hard reset. Since we hard reset all drives on
405 * KeyLargo ATA66, we have to keep that delay around. I may end
406 * up not hard resetting anymore on these and keep the delay only
407 * for older interfaces instead (we have to reset when coming
408 * from MacOS...) --BenH.
409 */
410 #define IDE_WAKEUP_DELAY (1*HZ)
411
412 static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
413 static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
414 static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio);
415 static void pmac_ide_selectproc(ide_drive_t *drive);
416 static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
417
418 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
419
420 /*
421 * N.B. this can't be an initfunc, because the media-bay task can
422 * call ide_[un]register at any time.
423 */
424 void
425 pmac_ide_init_hwif_ports(hw_regs_t *hw,
426 unsigned long data_port, unsigned long ctrl_port,
427 int *irq)
428 {
429 int i, ix;
430
431 if (data_port == 0)
432 return;
433
434 for (ix = 0; ix < MAX_HWIFS; ++ix)
435 if (data_port == pmac_ide[ix].regbase)
436 break;
437
438 if (ix >= MAX_HWIFS) {
439 /* Probably a PCI interface... */
440 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
441 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
442 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
443 return;
444 }
445
446 for (i = 0; i < 8; ++i)
447 hw->io_ports[i] = data_port + i * 0x10;
448 hw->io_ports[8] = data_port + 0x160;
449
450 if (irq != NULL)
451 *irq = pmac_ide[ix].irq;
452
453 hw->dev = &pmac_ide[ix].mdev->ofdev.dev;
454 }
455
456 #define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
457
458 /*
459 * Apply the timings of the proper unit (master/slave) to the shared
460 * timing register when selecting that unit. This version is for
461 * ASICs with a single timing register
462 */
463 static void
464 pmac_ide_selectproc(ide_drive_t *drive)
465 {
466 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
467
468 if (pmif == NULL)
469 return;
470
471 if (drive->select.b.unit & 0x01)
472 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
473 else
474 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
475 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
476 }
477
478 /*
479 * Apply the timings of the proper unit (master/slave) to the shared
480 * timing register when selecting that unit. This version is for
481 * ASICs with a dual timing register (Kauai)
482 */
483 static void
484 pmac_ide_kauai_selectproc(ide_drive_t *drive)
485 {
486 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
487
488 if (pmif == NULL)
489 return;
490
491 if (drive->select.b.unit & 0x01) {
492 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
493 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
494 } else {
495 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
496 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
497 }
498 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
499 }
500
501 /*
502 * Force an update of controller timing values for a given drive
503 */
504 static void
505 pmac_ide_do_update_timings(ide_drive_t *drive)
506 {
507 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
508
509 if (pmif == NULL)
510 return;
511
512 if (pmif->kind == controller_sh_ata6 ||
513 pmif->kind == controller_un_ata6 ||
514 pmif->kind == controller_k2_ata6)
515 pmac_ide_kauai_selectproc(drive);
516 else
517 pmac_ide_selectproc(drive);
518 }
519
520 static void
521 pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
522 {
523 u32 tmp;
524
525 writeb(value, (void __iomem *) port);
526 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
527 }
528
529 /*
530 * Send the SET_FEATURE IDE command to the drive and update drive->id with
531 * the new state. We currently don't use the generic routine as it used to
532 * cause various trouble, especially with older mediabays.
533 * This code is sometimes triggering a spurrious interrupt though, I need
534 * to sort that out sooner or later and see if I can finally get the
535 * common version to work properly in all cases
536 */
537 static int
538 pmac_ide_do_setfeature(ide_drive_t *drive, u8 command)
539 {
540 ide_hwif_t *hwif = HWIF(drive);
541 int result = 1;
542
543 disable_irq_nosync(hwif->irq);
544 udelay(1);
545 SELECT_DRIVE(drive);
546 SELECT_MASK(drive, 0);
547 udelay(1);
548 /* Get rid of pending error state */
549 (void) hwif->INB(IDE_STATUS_REG);
550 /* Timeout bumped for some powerbooks */
551 if (wait_for_ready(drive, 2000)) {
552 /* Timeout bumped for some powerbooks */
553 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
554 "before SET_FEATURE!\n", drive->name);
555 goto out;
556 }
557 udelay(10);
558 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
559 hwif->OUTB(command, IDE_NSECTOR_REG);
560 hwif->OUTB(SETFEATURES_XFER, IDE_FEATURE_REG);
561 hwif->OUTBSYNC(drive, WIN_SETFEATURES, IDE_COMMAND_REG);
562 udelay(1);
563 /* Timeout bumped for some powerbooks */
564 result = wait_for_ready(drive, 2000);
565 hwif->OUTB(drive->ctl, IDE_CONTROL_REG);
566 if (result)
567 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
568 "after SET_FEATURE !\n", drive->name);
569 out:
570 SELECT_MASK(drive, 0);
571 if (result == 0) {
572 drive->id->dma_ultra &= ~0xFF00;
573 drive->id->dma_mword &= ~0x0F00;
574 drive->id->dma_1word &= ~0x0F00;
575 switch(command) {
576 case XFER_UDMA_7:
577 drive->id->dma_ultra |= 0x8080; break;
578 case XFER_UDMA_6:
579 drive->id->dma_ultra |= 0x4040; break;
580 case XFER_UDMA_5:
581 drive->id->dma_ultra |= 0x2020; break;
582 case XFER_UDMA_4:
583 drive->id->dma_ultra |= 0x1010; break;
584 case XFER_UDMA_3:
585 drive->id->dma_ultra |= 0x0808; break;
586 case XFER_UDMA_2:
587 drive->id->dma_ultra |= 0x0404; break;
588 case XFER_UDMA_1:
589 drive->id->dma_ultra |= 0x0202; break;
590 case XFER_UDMA_0:
591 drive->id->dma_ultra |= 0x0101; break;
592 case XFER_MW_DMA_2:
593 drive->id->dma_mword |= 0x0404; break;
594 case XFER_MW_DMA_1:
595 drive->id->dma_mword |= 0x0202; break;
596 case XFER_MW_DMA_0:
597 drive->id->dma_mword |= 0x0101; break;
598 case XFER_SW_DMA_2:
599 drive->id->dma_1word |= 0x0404; break;
600 case XFER_SW_DMA_1:
601 drive->id->dma_1word |= 0x0202; break;
602 case XFER_SW_DMA_0:
603 drive->id->dma_1word |= 0x0101; break;
604 default: break;
605 }
606 if (!drive->init_speed)
607 drive->init_speed = command;
608 drive->current_speed = command;
609 }
610 enable_irq(hwif->irq);
611 return result;
612 }
613
614 /*
615 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
616 */
617 static void
618 pmac_ide_tuneproc(ide_drive_t *drive, u8 pio)
619 {
620 u32 *timings;
621 unsigned accessTicks, recTicks;
622 unsigned accessTime, recTime;
623 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
624 unsigned int cycle_time;
625
626 if (pmif == NULL)
627 return;
628
629 /* which drive is it ? */
630 timings = &pmif->timings[drive->select.b.unit & 0x01];
631
632 pio = ide_get_best_pio_mode(drive, pio, 4);
633 cycle_time = ide_pio_cycle_time(drive, pio);
634
635 switch (pmif->kind) {
636 case controller_sh_ata6: {
637 /* 133Mhz cell */
638 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
639 if (tr == 0)
640 return;
641 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
642 break;
643 }
644 case controller_un_ata6:
645 case controller_k2_ata6: {
646 /* 100Mhz cell */
647 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
648 if (tr == 0)
649 return;
650 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
651 break;
652 }
653 case controller_kl_ata4:
654 /* 66Mhz cell */
655 recTime = cycle_time - ide_pio_timings[pio].active_time
656 - ide_pio_timings[pio].setup_time;
657 recTime = max(recTime, 150U);
658 accessTime = ide_pio_timings[pio].active_time;
659 accessTime = max(accessTime, 150U);
660 accessTicks = SYSCLK_TICKS_66(accessTime);
661 accessTicks = min(accessTicks, 0x1fU);
662 recTicks = SYSCLK_TICKS_66(recTime);
663 recTicks = min(recTicks, 0x1fU);
664 *timings = ((*timings) & ~TR_66_PIO_MASK) |
665 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
666 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
667 break;
668 default: {
669 /* 33Mhz cell */
670 int ebit = 0;
671 recTime = cycle_time - ide_pio_timings[pio].active_time
672 - ide_pio_timings[pio].setup_time;
673 recTime = max(recTime, 150U);
674 accessTime = ide_pio_timings[pio].active_time;
675 accessTime = max(accessTime, 150U);
676 accessTicks = SYSCLK_TICKS(accessTime);
677 accessTicks = min(accessTicks, 0x1fU);
678 accessTicks = max(accessTicks, 4U);
679 recTicks = SYSCLK_TICKS(recTime);
680 recTicks = min(recTicks, 0x1fU);
681 recTicks = max(recTicks, 5U) - 4;
682 if (recTicks > 9) {
683 recTicks--; /* guess, but it's only for PIO0, so... */
684 ebit = 1;
685 }
686 *timings = ((*timings) & ~TR_33_PIO_MASK) |
687 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
688 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
689 if (ebit)
690 *timings |= TR_33_PIO_E;
691 break;
692 }
693 }
694
695 #ifdef IDE_PMAC_DEBUG
696 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
697 drive->name, pio, *timings);
698 #endif
699
700 if (drive->select.all == HWIF(drive)->INB(IDE_SELECT_REG))
701 pmac_ide_do_update_timings(drive);
702 }
703
704 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
705
706 /*
707 * Calculate KeyLargo ATA/66 UDMA timings
708 */
709 static int
710 set_timings_udma_ata4(u32 *timings, u8 speed)
711 {
712 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
713
714 if (speed > XFER_UDMA_4)
715 return 1;
716
717 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
718 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
719 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
720
721 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
722 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
723 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
724 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
725 TR_66_UDMA_EN;
726 #ifdef IDE_PMAC_DEBUG
727 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
728 speed & 0xf, *timings);
729 #endif
730
731 return 0;
732 }
733
734 /*
735 * Calculate Kauai ATA/100 UDMA timings
736 */
737 static int
738 set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
739 {
740 struct ide_timing *t = ide_timing_find_mode(speed);
741 u32 tr;
742
743 if (speed > XFER_UDMA_5 || t == NULL)
744 return 1;
745 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
746 if (tr == 0)
747 return 1;
748 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
749 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
750
751 return 0;
752 }
753
754 /*
755 * Calculate Shasta ATA/133 UDMA timings
756 */
757 static int
758 set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
759 {
760 struct ide_timing *t = ide_timing_find_mode(speed);
761 u32 tr;
762
763 if (speed > XFER_UDMA_6 || t == NULL)
764 return 1;
765 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
766 if (tr == 0)
767 return 1;
768 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
769 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
770
771 return 0;
772 }
773
774 /*
775 * Calculate MDMA timings for all cells
776 */
777 static int
778 set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
779 u8 speed, int drive_cycle_time)
780 {
781 int cycleTime, accessTime = 0, recTime = 0;
782 unsigned accessTicks, recTicks;
783 struct mdma_timings_t* tm = NULL;
784 int i;
785
786 /* Get default cycle time for mode */
787 switch(speed & 0xf) {
788 case 0: cycleTime = 480; break;
789 case 1: cycleTime = 150; break;
790 case 2: cycleTime = 120; break;
791 default:
792 return 1;
793 }
794 /* Adjust for drive */
795 if (drive_cycle_time && drive_cycle_time > cycleTime)
796 cycleTime = drive_cycle_time;
797 /* OHare limits according to some old Apple sources */
798 if ((intf_type == controller_ohare) && (cycleTime < 150))
799 cycleTime = 150;
800 /* Get the proper timing array for this controller */
801 switch(intf_type) {
802 case controller_sh_ata6:
803 case controller_un_ata6:
804 case controller_k2_ata6:
805 break;
806 case controller_kl_ata4:
807 tm = mdma_timings_66;
808 break;
809 case controller_kl_ata3:
810 tm = mdma_timings_33k;
811 break;
812 default:
813 tm = mdma_timings_33;
814 break;
815 }
816 if (tm != NULL) {
817 /* Lookup matching access & recovery times */
818 i = -1;
819 for (;;) {
820 if (tm[i+1].cycleTime < cycleTime)
821 break;
822 i++;
823 }
824 if (i < 0)
825 return 1;
826 cycleTime = tm[i].cycleTime;
827 accessTime = tm[i].accessTime;
828 recTime = tm[i].recoveryTime;
829
830 #ifdef IDE_PMAC_DEBUG
831 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
832 drive->name, cycleTime, accessTime, recTime);
833 #endif
834 }
835 switch(intf_type) {
836 case controller_sh_ata6: {
837 /* 133Mhz cell */
838 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
839 if (tr == 0)
840 return 1;
841 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
842 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
843 }
844 case controller_un_ata6:
845 case controller_k2_ata6: {
846 /* 100Mhz cell */
847 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
848 if (tr == 0)
849 return 1;
850 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
851 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
852 }
853 break;
854 case controller_kl_ata4:
855 /* 66Mhz cell */
856 accessTicks = SYSCLK_TICKS_66(accessTime);
857 accessTicks = min(accessTicks, 0x1fU);
858 accessTicks = max(accessTicks, 0x1U);
859 recTicks = SYSCLK_TICKS_66(recTime);
860 recTicks = min(recTicks, 0x1fU);
861 recTicks = max(recTicks, 0x3U);
862 /* Clear out mdma bits and disable udma */
863 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
864 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
865 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
866 break;
867 case controller_kl_ata3:
868 /* 33Mhz cell on KeyLargo */
869 accessTicks = SYSCLK_TICKS(accessTime);
870 accessTicks = max(accessTicks, 1U);
871 accessTicks = min(accessTicks, 0x1fU);
872 accessTime = accessTicks * IDE_SYSCLK_NS;
873 recTicks = SYSCLK_TICKS(recTime);
874 recTicks = max(recTicks, 1U);
875 recTicks = min(recTicks, 0x1fU);
876 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
877 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
878 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
879 break;
880 default: {
881 /* 33Mhz cell on others */
882 int halfTick = 0;
883 int origAccessTime = accessTime;
884 int origRecTime = recTime;
885
886 accessTicks = SYSCLK_TICKS(accessTime);
887 accessTicks = max(accessTicks, 1U);
888 accessTicks = min(accessTicks, 0x1fU);
889 accessTime = accessTicks * IDE_SYSCLK_NS;
890 recTicks = SYSCLK_TICKS(recTime);
891 recTicks = max(recTicks, 2U) - 1;
892 recTicks = min(recTicks, 0x1fU);
893 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
894 if ((accessTicks > 1) &&
895 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
896 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
897 halfTick = 1;
898 accessTicks--;
899 }
900 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
901 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
902 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
903 if (halfTick)
904 *timings |= TR_33_MDMA_HALFTICK;
905 }
906 }
907 #ifdef IDE_PMAC_DEBUG
908 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
909 drive->name, speed & 0xf, *timings);
910 #endif
911 return 0;
912 }
913 #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
914
915 /*
916 * Speedproc. This function is called by the core to set any of the standard
917 * timing (PIO, MDMA or UDMA) to both the drive and the controller.
918 * You may notice we don't use this function on normal "dma check" operation,
919 * our dedicated function is more precise as it uses the drive provided
920 * cycle time value. We should probably fix this one to deal with that too...
921 */
922 static int pmac_ide_tune_chipset(ide_drive_t *drive, const u8 speed)
923 {
924 int unit = (drive->select.b.unit & 0x01);
925 int ret = 0;
926 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
927 u32 *timings, *timings2;
928
929 if (pmif == NULL)
930 return 1;
931
932 timings = &pmif->timings[unit];
933 timings2 = &pmif->timings[unit+2];
934
935 switch(speed) {
936 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
937 case XFER_UDMA_6:
938 case XFER_UDMA_5:
939 case XFER_UDMA_4:
940 case XFER_UDMA_3:
941 case XFER_UDMA_2:
942 case XFER_UDMA_1:
943 case XFER_UDMA_0:
944 if (pmif->kind == controller_kl_ata4)
945 ret = set_timings_udma_ata4(timings, speed);
946 else if (pmif->kind == controller_un_ata6
947 || pmif->kind == controller_k2_ata6)
948 ret = set_timings_udma_ata6(timings, timings2, speed);
949 else if (pmif->kind == controller_sh_ata6)
950 ret = set_timings_udma_shasta(timings, timings2, speed);
951 else
952 ret = 1;
953 break;
954 case XFER_MW_DMA_2:
955 case XFER_MW_DMA_1:
956 case XFER_MW_DMA_0:
957 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
958 break;
959 case XFER_SW_DMA_2:
960 case XFER_SW_DMA_1:
961 case XFER_SW_DMA_0:
962 return 1;
963 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
964 case XFER_PIO_4:
965 case XFER_PIO_3:
966 case XFER_PIO_2:
967 case XFER_PIO_1:
968 case XFER_PIO_0:
969 pmac_ide_tuneproc(drive, speed & 0x07);
970 break;
971 default:
972 ret = 1;
973 }
974 if (ret)
975 return ret;
976
977 ret = pmac_ide_do_setfeature(drive, speed);
978 if (ret)
979 return ret;
980
981 pmac_ide_do_update_timings(drive);
982
983 return 0;
984 }
985
986 /*
987 * Blast some well known "safe" values to the timing registers at init or
988 * wakeup from sleep time, before we do real calculation
989 */
990 static void
991 sanitize_timings(pmac_ide_hwif_t *pmif)
992 {
993 unsigned int value, value2 = 0;
994
995 switch(pmif->kind) {
996 case controller_sh_ata6:
997 value = 0x0a820c97;
998 value2 = 0x00033031;
999 break;
1000 case controller_un_ata6:
1001 case controller_k2_ata6:
1002 value = 0x08618a92;
1003 value2 = 0x00002921;
1004 break;
1005 case controller_kl_ata4:
1006 value = 0x0008438c;
1007 break;
1008 case controller_kl_ata3:
1009 value = 0x00084526;
1010 break;
1011 case controller_heathrow:
1012 case controller_ohare:
1013 default:
1014 value = 0x00074526;
1015 break;
1016 }
1017 pmif->timings[0] = pmif->timings[1] = value;
1018 pmif->timings[2] = pmif->timings[3] = value2;
1019 }
1020
1021 unsigned long
1022 pmac_ide_get_base(int index)
1023 {
1024 return pmac_ide[index].regbase;
1025 }
1026
1027 int
1028 pmac_ide_check_base(unsigned long base)
1029 {
1030 int ix;
1031
1032 for (ix = 0; ix < MAX_HWIFS; ++ix)
1033 if (base == pmac_ide[ix].regbase)
1034 return ix;
1035 return -1;
1036 }
1037
1038 int
1039 pmac_ide_get_irq(unsigned long base)
1040 {
1041 int ix;
1042
1043 for (ix = 0; ix < MAX_HWIFS; ++ix)
1044 if (base == pmac_ide[ix].regbase)
1045 return pmac_ide[ix].irq;
1046 return 0;
1047 }
1048
1049 static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
1050
1051 dev_t __init
1052 pmac_find_ide_boot(char *bootdevice, int n)
1053 {
1054 int i;
1055
1056 /*
1057 * Look through the list of IDE interfaces for this one.
1058 */
1059 for (i = 0; i < pmac_ide_count; ++i) {
1060 char *name;
1061 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
1062 continue;
1063 name = pmac_ide[i].node->full_name;
1064 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
1065 /* XXX should cope with the 2nd drive as well... */
1066 return MKDEV(ide_majors[i], 0);
1067 }
1068 }
1069
1070 return 0;
1071 }
1072
1073 /* Suspend call back, should be called after the child devices
1074 * have actually been suspended
1075 */
1076 static int
1077 pmac_ide_do_suspend(ide_hwif_t *hwif)
1078 {
1079 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1080
1081 /* We clear the timings */
1082 pmif->timings[0] = 0;
1083 pmif->timings[1] = 0;
1084
1085 disable_irq(pmif->irq);
1086
1087 /* The media bay will handle itself just fine */
1088 if (pmif->mediabay)
1089 return 0;
1090
1091 /* Kauai has bus control FCRs directly here */
1092 if (pmif->kauai_fcr) {
1093 u32 fcr = readl(pmif->kauai_fcr);
1094 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
1095 writel(fcr, pmif->kauai_fcr);
1096 }
1097
1098 /* Disable the bus on older machines and the cell on kauai */
1099 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
1100 0);
1101
1102 return 0;
1103 }
1104
1105 /* Resume call back, should be called before the child devices
1106 * are resumed
1107 */
1108 static int
1109 pmac_ide_do_resume(ide_hwif_t *hwif)
1110 {
1111 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1112
1113 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1114 if (!pmif->mediabay) {
1115 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1116 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1117 msleep(10);
1118 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1119
1120 /* Kauai has it different */
1121 if (pmif->kauai_fcr) {
1122 u32 fcr = readl(pmif->kauai_fcr);
1123 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1124 writel(fcr, pmif->kauai_fcr);
1125 }
1126
1127 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1128 }
1129
1130 /* Sanitize drive timings */
1131 sanitize_timings(pmif);
1132
1133 enable_irq(pmif->irq);
1134
1135 return 0;
1136 }
1137
1138 /*
1139 * Setup, register & probe an IDE channel driven by this driver, this is
1140 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1141 * that ends up beeing free of any device is not kept around by this driver
1142 * (it is kept in 2.4). This introduce an interface numbering change on some
1143 * rare machines unfortunately, but it's better this way.
1144 */
1145 static int
1146 pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1147 {
1148 struct device_node *np = pmif->node;
1149 const int *bidp;
1150
1151 pmif->cable_80 = 0;
1152 pmif->broken_dma = pmif->broken_dma_warn = 0;
1153 if (of_device_is_compatible(np, "shasta-ata"))
1154 pmif->kind = controller_sh_ata6;
1155 else if (of_device_is_compatible(np, "kauai-ata"))
1156 pmif->kind = controller_un_ata6;
1157 else if (of_device_is_compatible(np, "K2-UATA"))
1158 pmif->kind = controller_k2_ata6;
1159 else if (of_device_is_compatible(np, "keylargo-ata")) {
1160 if (strcmp(np->name, "ata-4") == 0)
1161 pmif->kind = controller_kl_ata4;
1162 else
1163 pmif->kind = controller_kl_ata3;
1164 } else if (of_device_is_compatible(np, "heathrow-ata"))
1165 pmif->kind = controller_heathrow;
1166 else {
1167 pmif->kind = controller_ohare;
1168 pmif->broken_dma = 1;
1169 }
1170
1171 bidp = of_get_property(np, "AAPL,bus-id", NULL);
1172 pmif->aapl_bus_id = bidp ? *bidp : 0;
1173
1174 /* Get cable type from device-tree */
1175 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1176 || pmif->kind == controller_k2_ata6
1177 || pmif->kind == controller_sh_ata6) {
1178 const char* cable = of_get_property(np, "cable-type", NULL);
1179 if (cable && !strncmp(cable, "80-", 3))
1180 pmif->cable_80 = 1;
1181 }
1182 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1183 * they have a 80 conductor cable, this seem to be always the case unless
1184 * the user mucked around
1185 */
1186 if (of_device_is_compatible(np, "K2-UATA") ||
1187 of_device_is_compatible(np, "shasta-ata"))
1188 pmif->cable_80 = 1;
1189
1190 /* On Kauai-type controllers, we make sure the FCR is correct */
1191 if (pmif->kauai_fcr)
1192 writel(KAUAI_FCR_UATA_MAGIC |
1193 KAUAI_FCR_UATA_RESET_N |
1194 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1195
1196 pmif->mediabay = 0;
1197
1198 /* Make sure we have sane timings */
1199 sanitize_timings(pmif);
1200
1201 #ifndef CONFIG_PPC64
1202 /* XXX FIXME: Media bay stuff need re-organizing */
1203 if (np->parent && np->parent->name
1204 && strcasecmp(np->parent->name, "media-bay") == 0) {
1205 #ifdef CONFIG_PMAC_MEDIABAY
1206 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
1207 #endif /* CONFIG_PMAC_MEDIABAY */
1208 pmif->mediabay = 1;
1209 if (!bidp)
1210 pmif->aapl_bus_id = 1;
1211 } else if (pmif->kind == controller_ohare) {
1212 /* The code below is having trouble on some ohare machines
1213 * (timing related ?). Until I can put my hand on one of these
1214 * units, I keep the old way
1215 */
1216 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1217 } else
1218 #endif
1219 {
1220 /* This is necessary to enable IDE when net-booting */
1221 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1222 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1223 msleep(10);
1224 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1225 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1226 }
1227
1228 /* Setup MMIO ops */
1229 default_hwif_mmiops(hwif);
1230 hwif->OUTBSYNC = pmac_outbsync;
1231
1232 /* Tell common code _not_ to mess with resources */
1233 hwif->mmio = 1;
1234 hwif->hwif_data = pmif;
1235 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1236 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1237 hwif->chipset = ide_pmac;
1238 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1239 hwif->hold = pmif->mediabay;
1240 hwif->cbl = pmif->cable_80 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
1241 hwif->drives[0].unmask = 1;
1242 hwif->drives[1].unmask = 1;
1243 hwif->pio_mask = ATA_PIO4;
1244 hwif->tuneproc = pmac_ide_tuneproc;
1245 if (pmif->kind == controller_un_ata6
1246 || pmif->kind == controller_k2_ata6
1247 || pmif->kind == controller_sh_ata6)
1248 hwif->selectproc = pmac_ide_kauai_selectproc;
1249 else
1250 hwif->selectproc = pmac_ide_selectproc;
1251 hwif->speedproc = pmac_ide_tune_chipset;
1252
1253 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1254 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1255 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1256
1257 #ifdef CONFIG_PMAC_MEDIABAY
1258 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1259 hwif->noprobe = 0;
1260 #endif /* CONFIG_PMAC_MEDIABAY */
1261
1262 hwif->sg_max_nents = MAX_DCMDS;
1263
1264 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1265 /* has a DBDMA controller channel */
1266 if (pmif->dma_regs)
1267 pmac_ide_setup_dma(pmif, hwif);
1268 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1269
1270 /* We probe the hwif now */
1271 probe_hwif_init(hwif);
1272
1273 ide_proc_register_port(hwif);
1274
1275 return 0;
1276 }
1277
1278 /*
1279 * Attach to a macio probed interface
1280 */
1281 static int __devinit
1282 pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1283 {
1284 void __iomem *base;
1285 unsigned long regbase;
1286 int irq;
1287 ide_hwif_t *hwif;
1288 pmac_ide_hwif_t *pmif;
1289 int i, rc;
1290
1291 i = 0;
1292 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1293 || pmac_ide[i].node != NULL))
1294 ++i;
1295 if (i >= MAX_HWIFS) {
1296 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1297 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1298 return -ENODEV;
1299 }
1300
1301 pmif = &pmac_ide[i];
1302 hwif = &ide_hwifs[i];
1303
1304 if (macio_resource_count(mdev) == 0) {
1305 printk(KERN_WARNING "ide%d: no address for %s\n",
1306 i, mdev->ofdev.node->full_name);
1307 return -ENXIO;
1308 }
1309
1310 /* Request memory resource for IO ports */
1311 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1312 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1313 return -EBUSY;
1314 }
1315
1316 /* XXX This is bogus. Should be fixed in the registry by checking
1317 * the kind of host interrupt controller, a bit like gatwick
1318 * fixes in irq.c. That works well enough for the single case
1319 * where that happens though...
1320 */
1321 if (macio_irq_count(mdev) == 0) {
1322 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1323 i, mdev->ofdev.node->full_name);
1324 irq = irq_create_mapping(NULL, 13);
1325 } else
1326 irq = macio_irq(mdev, 0);
1327
1328 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1329 regbase = (unsigned long) base;
1330
1331 hwif->pci_dev = mdev->bus->pdev;
1332 hwif->gendev.parent = &mdev->ofdev.dev;
1333
1334 pmif->mdev = mdev;
1335 pmif->node = mdev->ofdev.node;
1336 pmif->regbase = regbase;
1337 pmif->irq = irq;
1338 pmif->kauai_fcr = NULL;
1339 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1340 if (macio_resource_count(mdev) >= 2) {
1341 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1342 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1343 else
1344 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1345 } else
1346 pmif->dma_regs = NULL;
1347 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1348 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1349
1350 rc = pmac_ide_setup_device(pmif, hwif);
1351 if (rc != 0) {
1352 /* The inteface is released to the common IDE layer */
1353 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1354 iounmap(base);
1355 if (pmif->dma_regs)
1356 iounmap(pmif->dma_regs);
1357 memset(pmif, 0, sizeof(*pmif));
1358 macio_release_resource(mdev, 0);
1359 if (pmif->dma_regs)
1360 macio_release_resource(mdev, 1);
1361 }
1362
1363 return rc;
1364 }
1365
1366 static int
1367 pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1368 {
1369 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1370 int rc = 0;
1371
1372 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1373 && mesg.event == PM_EVENT_SUSPEND) {
1374 rc = pmac_ide_do_suspend(hwif);
1375 if (rc == 0)
1376 mdev->ofdev.dev.power.power_state = mesg;
1377 }
1378
1379 return rc;
1380 }
1381
1382 static int
1383 pmac_ide_macio_resume(struct macio_dev *mdev)
1384 {
1385 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1386 int rc = 0;
1387
1388 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1389 rc = pmac_ide_do_resume(hwif);
1390 if (rc == 0)
1391 mdev->ofdev.dev.power.power_state = PMSG_ON;
1392 }
1393
1394 return rc;
1395 }
1396
1397 /*
1398 * Attach to a PCI probed interface
1399 */
1400 static int __devinit
1401 pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1402 {
1403 ide_hwif_t *hwif;
1404 struct device_node *np;
1405 pmac_ide_hwif_t *pmif;
1406 void __iomem *base;
1407 unsigned long rbase, rlen;
1408 int i, rc;
1409
1410 np = pci_device_to_OF_node(pdev);
1411 if (np == NULL) {
1412 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1413 return -ENODEV;
1414 }
1415 i = 0;
1416 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1417 || pmac_ide[i].node != NULL))
1418 ++i;
1419 if (i >= MAX_HWIFS) {
1420 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1421 printk(KERN_ERR " %s\n", np->full_name);
1422 return -ENODEV;
1423 }
1424
1425 pmif = &pmac_ide[i];
1426 hwif = &ide_hwifs[i];
1427
1428 if (pci_enable_device(pdev)) {
1429 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1430 i, np->full_name);
1431 return -ENXIO;
1432 }
1433 pci_set_master(pdev);
1434
1435 if (pci_request_regions(pdev, "Kauai ATA")) {
1436 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1437 i, np->full_name);
1438 return -ENXIO;
1439 }
1440
1441 hwif->pci_dev = pdev;
1442 hwif->gendev.parent = &pdev->dev;
1443 pmif->mdev = NULL;
1444 pmif->node = np;
1445
1446 rbase = pci_resource_start(pdev, 0);
1447 rlen = pci_resource_len(pdev, 0);
1448
1449 base = ioremap(rbase, rlen);
1450 pmif->regbase = (unsigned long) base + 0x2000;
1451 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1452 pmif->dma_regs = base + 0x1000;
1453 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1454 pmif->kauai_fcr = base;
1455 pmif->irq = pdev->irq;
1456
1457 pci_set_drvdata(pdev, hwif);
1458
1459 rc = pmac_ide_setup_device(pmif, hwif);
1460 if (rc != 0) {
1461 /* The inteface is released to the common IDE layer */
1462 pci_set_drvdata(pdev, NULL);
1463 iounmap(base);
1464 memset(pmif, 0, sizeof(*pmif));
1465 pci_release_regions(pdev);
1466 }
1467
1468 return rc;
1469 }
1470
1471 static int
1472 pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1473 {
1474 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1475 int rc = 0;
1476
1477 if (mesg.event != pdev->dev.power.power_state.event
1478 && mesg.event == PM_EVENT_SUSPEND) {
1479 rc = pmac_ide_do_suspend(hwif);
1480 if (rc == 0)
1481 pdev->dev.power.power_state = mesg;
1482 }
1483
1484 return rc;
1485 }
1486
1487 static int
1488 pmac_ide_pci_resume(struct pci_dev *pdev)
1489 {
1490 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1491 int rc = 0;
1492
1493 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1494 rc = pmac_ide_do_resume(hwif);
1495 if (rc == 0)
1496 pdev->dev.power.power_state = PMSG_ON;
1497 }
1498
1499 return rc;
1500 }
1501
1502 static struct of_device_id pmac_ide_macio_match[] =
1503 {
1504 {
1505 .name = "IDE",
1506 },
1507 {
1508 .name = "ATA",
1509 },
1510 {
1511 .type = "ide",
1512 },
1513 {
1514 .type = "ata",
1515 },
1516 {},
1517 };
1518
1519 static struct macio_driver pmac_ide_macio_driver =
1520 {
1521 .name = "ide-pmac",
1522 .match_table = pmac_ide_macio_match,
1523 .probe = pmac_ide_macio_attach,
1524 .suspend = pmac_ide_macio_suspend,
1525 .resume = pmac_ide_macio_resume,
1526 };
1527
1528 static struct pci_device_id pmac_ide_pci_match[] = {
1529 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA,
1530 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1531 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100,
1532 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1533 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100,
1534 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1535 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1536 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1537 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA,
1538 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1539 {},
1540 };
1541
1542 static struct pci_driver pmac_ide_pci_driver = {
1543 .name = "ide-pmac",
1544 .id_table = pmac_ide_pci_match,
1545 .probe = pmac_ide_pci_attach,
1546 .suspend = pmac_ide_pci_suspend,
1547 .resume = pmac_ide_pci_resume,
1548 };
1549 MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1550
1551 int __init pmac_ide_probe(void)
1552 {
1553 int error;
1554
1555 if (!machine_is(powermac))
1556 return -ENODEV;
1557
1558 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1559 error = pci_register_driver(&pmac_ide_pci_driver);
1560 if (error)
1561 goto out;
1562 error = macio_register_driver(&pmac_ide_macio_driver);
1563 if (error) {
1564 pci_unregister_driver(&pmac_ide_pci_driver);
1565 goto out;
1566 }
1567 #else
1568 error = macio_register_driver(&pmac_ide_macio_driver);
1569 if (error)
1570 goto out;
1571 error = pci_register_driver(&pmac_ide_pci_driver);
1572 if (error) {
1573 macio_unregister_driver(&pmac_ide_macio_driver);
1574 goto out;
1575 }
1576 #endif
1577 out:
1578 return error;
1579 }
1580
1581 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1582
1583 /*
1584 * pmac_ide_build_dmatable builds the DBDMA command list
1585 * for a transfer and sets the DBDMA channel to point to it.
1586 */
1587 static int
1588 pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1589 {
1590 struct dbdma_cmd *table;
1591 int i, count = 0;
1592 ide_hwif_t *hwif = HWIF(drive);
1593 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1594 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1595 struct scatterlist *sg;
1596 int wr = (rq_data_dir(rq) == WRITE);
1597
1598 /* DMA table is already aligned */
1599 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1600
1601 /* Make sure DMA controller is stopped (necessary ?) */
1602 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1603 while (readl(&dma->status) & RUN)
1604 udelay(1);
1605
1606 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1607
1608 if (!i)
1609 return 0;
1610
1611 /* Build DBDMA commands list */
1612 sg = hwif->sg_table;
1613 while (i && sg_dma_len(sg)) {
1614 u32 cur_addr;
1615 u32 cur_len;
1616
1617 cur_addr = sg_dma_address(sg);
1618 cur_len = sg_dma_len(sg);
1619
1620 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1621 if (pmif->broken_dma_warn == 0) {
1622 printk(KERN_WARNING "%s: DMA on non aligned address,"
1623 "switching to PIO on Ohare chipset\n", drive->name);
1624 pmif->broken_dma_warn = 1;
1625 }
1626 goto use_pio_instead;
1627 }
1628 while (cur_len) {
1629 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1630
1631 if (count++ >= MAX_DCMDS) {
1632 printk(KERN_WARNING "%s: DMA table too small\n",
1633 drive->name);
1634 goto use_pio_instead;
1635 }
1636 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1637 st_le16(&table->req_count, tc);
1638 st_le32(&table->phy_addr, cur_addr);
1639 table->cmd_dep = 0;
1640 table->xfer_status = 0;
1641 table->res_count = 0;
1642 cur_addr += tc;
1643 cur_len -= tc;
1644 ++table;
1645 }
1646 sg++;
1647 i--;
1648 }
1649
1650 /* convert the last command to an input/output last command */
1651 if (count) {
1652 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1653 /* add the stop command to the end of the list */
1654 memset(table, 0, sizeof(struct dbdma_cmd));
1655 st_le16(&table->command, DBDMA_STOP);
1656 mb();
1657 writel(hwif->dmatable_dma, &dma->cmdptr);
1658 return 1;
1659 }
1660
1661 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1662 use_pio_instead:
1663 pci_unmap_sg(hwif->pci_dev,
1664 hwif->sg_table,
1665 hwif->sg_nents,
1666 hwif->sg_dma_direction);
1667 return 0; /* revert to PIO for this request */
1668 }
1669
1670 /* Teardown mappings after DMA has completed. */
1671 static void
1672 pmac_ide_destroy_dmatable (ide_drive_t *drive)
1673 {
1674 ide_hwif_t *hwif = drive->hwif;
1675 struct pci_dev *dev = HWIF(drive)->pci_dev;
1676 struct scatterlist *sg = hwif->sg_table;
1677 int nents = hwif->sg_nents;
1678
1679 if (nents) {
1680 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1681 hwif->sg_nents = 0;
1682 }
1683 }
1684
1685 /*
1686 * Pick up best MDMA timing for the drive and apply it
1687 */
1688 static int
1689 pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1690 {
1691 ide_hwif_t *hwif = HWIF(drive);
1692 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1693 int drive_cycle_time;
1694 struct hd_driveid *id = drive->id;
1695 u32 *timings, *timings2;
1696 u32 timing_local[2];
1697 int ret;
1698
1699 /* which drive is it ? */
1700 timings = &pmif->timings[drive->select.b.unit & 0x01];
1701 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1702
1703 /* Check if drive provide explicit cycle time */
1704 if ((id->field_valid & 2) && (id->eide_dma_time))
1705 drive_cycle_time = id->eide_dma_time;
1706 else
1707 drive_cycle_time = 0;
1708
1709 /* Copy timings to local image */
1710 timing_local[0] = *timings;
1711 timing_local[1] = *timings2;
1712
1713 /* Calculate controller timings */
1714 ret = set_timings_mdma( drive, pmif->kind,
1715 &timing_local[0],
1716 &timing_local[1],
1717 mode,
1718 drive_cycle_time);
1719 if (ret)
1720 return 0;
1721
1722 /* Set feature on drive */
1723 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
1724 ret = pmac_ide_do_setfeature(drive, mode);
1725 if (ret) {
1726 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1727 return 0;
1728 }
1729
1730 /* Apply timings to controller */
1731 *timings = timing_local[0];
1732 *timings2 = timing_local[1];
1733
1734 return 1;
1735 }
1736
1737 /*
1738 * Pick up best UDMA timing for the drive and apply it
1739 */
1740 static int
1741 pmac_ide_udma_enable(ide_drive_t *drive, u16 mode)
1742 {
1743 ide_hwif_t *hwif = HWIF(drive);
1744 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1745 u32 *timings, *timings2;
1746 u32 timing_local[2];
1747 int ret;
1748
1749 /* which drive is it ? */
1750 timings = &pmif->timings[drive->select.b.unit & 0x01];
1751 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1752
1753 /* Copy timings to local image */
1754 timing_local[0] = *timings;
1755 timing_local[1] = *timings2;
1756
1757 /* Calculate timings for interface */
1758 if (pmif->kind == controller_un_ata6
1759 || pmif->kind == controller_k2_ata6)
1760 ret = set_timings_udma_ata6( &timing_local[0],
1761 &timing_local[1],
1762 mode);
1763 else if (pmif->kind == controller_sh_ata6)
1764 ret = set_timings_udma_shasta( &timing_local[0],
1765 &timing_local[1],
1766 mode);
1767 else
1768 ret = set_timings_udma_ata4(&timing_local[0], mode);
1769 if (ret)
1770 return 0;
1771
1772 /* Set feature on drive */
1773 printk(KERN_INFO "%s: Enabling Ultra DMA %d\n", drive->name, mode & 0x0f);
1774 ret = pmac_ide_do_setfeature(drive, mode);
1775 if (ret) {
1776 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1777 return 0;
1778 }
1779
1780 /* Apply timings to controller */
1781 *timings = timing_local[0];
1782 *timings2 = timing_local[1];
1783
1784 return 1;
1785 }
1786
1787 /*
1788 * Check what is the best DMA timing setting for the drive and
1789 * call appropriate functions to apply it.
1790 */
1791 static int
1792 pmac_ide_dma_check(ide_drive_t *drive)
1793 {
1794 struct hd_driveid *id = drive->id;
1795 ide_hwif_t *hwif = HWIF(drive);
1796 int enable = 1;
1797 drive->using_dma = 0;
1798
1799 if (drive->media == ide_floppy)
1800 enable = 0;
1801 if (((id->capability & 1) == 0) && !__ide_dma_good_drive(drive))
1802 enable = 0;
1803 if (__ide_dma_bad_drive(drive))
1804 enable = 0;
1805
1806 if (enable) {
1807 u8 mode = ide_max_dma_mode(drive);
1808
1809 if (mode >= XFER_UDMA_0)
1810 drive->using_dma = pmac_ide_udma_enable(drive, mode);
1811 else if (mode >= XFER_MW_DMA_0)
1812 drive->using_dma = pmac_ide_mdma_enable(drive, mode);
1813 hwif->OUTB(0, IDE_CONTROL_REG);
1814 /* Apply settings to controller */
1815 pmac_ide_do_update_timings(drive);
1816 }
1817 return 0;
1818 }
1819
1820 /*
1821 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1822 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1823 */
1824 static int
1825 pmac_ide_dma_setup(ide_drive_t *drive)
1826 {
1827 ide_hwif_t *hwif = HWIF(drive);
1828 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1829 struct request *rq = HWGROUP(drive)->rq;
1830 u8 unit = (drive->select.b.unit & 0x01);
1831 u8 ata4;
1832
1833 if (pmif == NULL)
1834 return 1;
1835 ata4 = (pmif->kind == controller_kl_ata4);
1836
1837 if (!pmac_ide_build_dmatable(drive, rq)) {
1838 ide_map_sg(drive, rq);
1839 return 1;
1840 }
1841
1842 /* Apple adds 60ns to wrDataSetup on reads */
1843 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1844 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1845 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1846 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1847 }
1848
1849 drive->waiting_for_dma = 1;
1850
1851 return 0;
1852 }
1853
1854 static void
1855 pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1856 {
1857 /* issue cmd to drive */
1858 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1859 }
1860
1861 /*
1862 * Kick the DMA controller into life after the DMA command has been issued
1863 * to the drive.
1864 */
1865 static void
1866 pmac_ide_dma_start(ide_drive_t *drive)
1867 {
1868 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1869 volatile struct dbdma_regs __iomem *dma;
1870
1871 dma = pmif->dma_regs;
1872
1873 writel((RUN << 16) | RUN, &dma->control);
1874 /* Make sure it gets to the controller right now */
1875 (void)readl(&dma->control);
1876 }
1877
1878 /*
1879 * After a DMA transfer, make sure the controller is stopped
1880 */
1881 static int
1882 pmac_ide_dma_end (ide_drive_t *drive)
1883 {
1884 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1885 volatile struct dbdma_regs __iomem *dma;
1886 u32 dstat;
1887
1888 if (pmif == NULL)
1889 return 0;
1890 dma = pmif->dma_regs;
1891
1892 drive->waiting_for_dma = 0;
1893 dstat = readl(&dma->status);
1894 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1895 pmac_ide_destroy_dmatable(drive);
1896 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1897 * in theory, but with ATAPI decices doing buffer underruns, that would
1898 * cause us to disable DMA, which isn't what we want
1899 */
1900 return (dstat & (RUN|DEAD)) != RUN;
1901 }
1902
1903 /*
1904 * Check out that the interrupt we got was for us. We can't always know this
1905 * for sure with those Apple interfaces (well, we could on the recent ones but
1906 * that's not implemented yet), on the other hand, we don't have shared interrupts
1907 * so it's not really a problem
1908 */
1909 static int
1910 pmac_ide_dma_test_irq (ide_drive_t *drive)
1911 {
1912 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1913 volatile struct dbdma_regs __iomem *dma;
1914 unsigned long status, timeout;
1915
1916 if (pmif == NULL)
1917 return 0;
1918 dma = pmif->dma_regs;
1919
1920 /* We have to things to deal with here:
1921 *
1922 * - The dbdma won't stop if the command was started
1923 * but completed with an error without transferring all
1924 * datas. This happens when bad blocks are met during
1925 * a multi-block transfer.
1926 *
1927 * - The dbdma fifo hasn't yet finished flushing to
1928 * to system memory when the disk interrupt occurs.
1929 *
1930 */
1931
1932 /* If ACTIVE is cleared, the STOP command have passed and
1933 * transfer is complete.
1934 */
1935 status = readl(&dma->status);
1936 if (!(status & ACTIVE))
1937 return 1;
1938 if (!drive->waiting_for_dma)
1939 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1940 called while not waiting\n", HWIF(drive)->index);
1941
1942 /* If dbdma didn't execute the STOP command yet, the
1943 * active bit is still set. We consider that we aren't
1944 * sharing interrupts (which is hopefully the case with
1945 * those controllers) and so we just try to flush the
1946 * channel for pending data in the fifo
1947 */
1948 udelay(1);
1949 writel((FLUSH << 16) | FLUSH, &dma->control);
1950 timeout = 0;
1951 for (;;) {
1952 udelay(1);
1953 status = readl(&dma->status);
1954 if ((status & FLUSH) == 0)
1955 break;
1956 if (++timeout > 100) {
1957 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1958 timeout flushing channel\n", HWIF(drive)->index);
1959 break;
1960 }
1961 }
1962 return 1;
1963 }
1964
1965 static void pmac_ide_dma_host_off(ide_drive_t *drive)
1966 {
1967 }
1968
1969 static void pmac_ide_dma_host_on(ide_drive_t *drive)
1970 {
1971 }
1972
1973 static void
1974 pmac_ide_dma_lost_irq (ide_drive_t *drive)
1975 {
1976 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1977 volatile struct dbdma_regs __iomem *dma;
1978 unsigned long status;
1979
1980 if (pmif == NULL)
1981 return;
1982 dma = pmif->dma_regs;
1983
1984 status = readl(&dma->status);
1985 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1986 }
1987
1988 /*
1989 * Allocate the data structures needed for using DMA with an interface
1990 * and fill the proper list of functions pointers
1991 */
1992 static void __init
1993 pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1994 {
1995 /* We won't need pci_dev if we switch to generic consistent
1996 * DMA routines ...
1997 */
1998 if (hwif->pci_dev == NULL)
1999 return;
2000 /*
2001 * Allocate space for the DBDMA commands.
2002 * The +2 is +1 for the stop command and +1 to allow for
2003 * aligning the start address to a multiple of 16 bytes.
2004 */
2005 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
2006 hwif->pci_dev,
2007 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
2008 &hwif->dmatable_dma);
2009 if (pmif->dma_table_cpu == NULL) {
2010 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
2011 hwif->name);
2012 return;
2013 }
2014
2015 hwif->dma_off_quietly = &ide_dma_off_quietly;
2016 hwif->ide_dma_on = &__ide_dma_on;
2017 hwif->ide_dma_check = &pmac_ide_dma_check;
2018 hwif->dma_setup = &pmac_ide_dma_setup;
2019 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
2020 hwif->dma_start = &pmac_ide_dma_start;
2021 hwif->ide_dma_end = &pmac_ide_dma_end;
2022 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
2023 hwif->dma_host_off = &pmac_ide_dma_host_off;
2024 hwif->dma_host_on = &pmac_ide_dma_host_on;
2025 hwif->dma_timeout = &ide_dma_timeout;
2026 hwif->dma_lost_irq = &pmac_ide_dma_lost_irq;
2027
2028 hwif->atapi_dma = 1;
2029 switch(pmif->kind) {
2030 case controller_sh_ata6:
2031 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
2032 hwif->mwdma_mask = 0x07;
2033 hwif->swdma_mask = 0x00;
2034 break;
2035 case controller_un_ata6:
2036 case controller_k2_ata6:
2037 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
2038 hwif->mwdma_mask = 0x07;
2039 hwif->swdma_mask = 0x00;
2040 break;
2041 case controller_kl_ata4:
2042 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
2043 hwif->mwdma_mask = 0x07;
2044 hwif->swdma_mask = 0x00;
2045 break;
2046 default:
2047 hwif->ultra_mask = 0x00;
2048 hwif->mwdma_mask = 0x07;
2049 hwif->swdma_mask = 0x00;
2050 break;
2051 }
2052 }
2053
2054 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
Linux kernel - Deliverables
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