2 * linux/drivers/ide/ppc/pmac.c
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
16 * Some code taken from drivers/ide/ide-dma.c:
18 * Copyright (c) 1995-1998 Mark Lord
20 * TODO: - Use pre-calculated (kauai) timing tables all the time and
21 * get rid of the "rounded" tables used previously, so we have the
22 * same table format for all controllers and can then just have one
26 #include <linux/types.h>
27 #include <linux/kernel.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
30 #include <linux/ide.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
33 #include <linux/pci.h>
34 #include <linux/adb.h>
35 #include <linux/pmu.h>
36 #include <linux/scatterlist.h>
40 #include <asm/dbdma.h>
42 #include <asm/pci-bridge.h>
43 #include <asm/machdep.h>
44 #include <asm/pmac_feature.h>
45 #include <asm/sections.h>
49 #include <asm/mediabay.h>
52 #include "../ide-timing.h"
56 #define DMA_WAIT_TIMEOUT 50
58 typedef struct pmac_ide_hwif
{
59 unsigned long regbase
;
63 unsigned cable_80
: 1;
64 unsigned mediabay
: 1;
65 unsigned broken_dma
: 1;
66 unsigned broken_dma_warn
: 1;
67 struct device_node
* node
;
68 struct macio_dev
*mdev
;
70 volatile u32 __iomem
* *kauai_fcr
;
71 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
72 /* Those fields are duplicating what is in hwif. We currently
73 * can't use the hwif ones because of some assumptions that are
74 * beeing done by the generic code about the kind of dma controller
75 * and format of the dma table. This will have to be fixed though.
77 volatile struct dbdma_regs __iomem
* dma_regs
;
78 struct dbdma_cmd
* dma_table_cpu
;
83 static pmac_ide_hwif_t pmac_ide
[MAX_HWIFS
];
84 static int pmac_ide_count
;
87 controller_ohare
, /* OHare based */
88 controller_heathrow
, /* Heathrow/Paddington */
89 controller_kl_ata3
, /* KeyLargo ATA-3 */
90 controller_kl_ata4
, /* KeyLargo ATA-4 */
91 controller_un_ata6
, /* UniNorth2 ATA-6 */
92 controller_k2_ata6
, /* K2 ATA-6 */
93 controller_sh_ata6
, /* Shasta ATA-6 */
96 static const char* model_name
[] = {
97 "OHare ATA", /* OHare based */
98 "Heathrow ATA", /* Heathrow/Paddington */
99 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
100 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
101 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
102 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
103 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
107 * Extra registers, both 32-bit little-endian
109 #define IDE_TIMING_CONFIG 0x200
110 #define IDE_INTERRUPT 0x300
112 /* Kauai (U2) ATA has different register setup */
113 #define IDE_KAUAI_PIO_CONFIG 0x200
114 #define IDE_KAUAI_ULTRA_CONFIG 0x210
115 #define IDE_KAUAI_POLL_CONFIG 0x220
118 * Timing configuration register definitions
121 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
122 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
123 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
124 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
125 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
127 /* 133Mhz cell, found in shasta.
128 * See comments about 100 Mhz Uninorth 2...
129 * Note that PIO_MASK and MDMA_MASK seem to overlap
131 #define TR_133_PIOREG_PIO_MASK 0xff000fff
132 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
133 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
134 #define TR_133_UDMAREG_UDMA_EN 0x00000001
136 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
137 * this one yet, it appears as a pci device (106b/0033) on uninorth
138 * internal PCI bus and it's clock is controlled like gem or fw. It
139 * appears to be an evolution of keylargo ATA4 with a timing register
140 * extended to 2 32bits registers and a similar DBDMA channel. Other
141 * registers seem to exist but I can't tell much about them.
143 * So far, I'm using pre-calculated tables for this extracted from
144 * the values used by the MacOS X driver.
146 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
147 * register controls the UDMA timings. At least, it seems bit 0
148 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
149 * cycle time in units of 10ns. Bits 8..15 are used by I don't
150 * know their meaning yet
152 #define TR_100_PIOREG_PIO_MASK 0xff000fff
153 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
154 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
155 #define TR_100_UDMAREG_UDMA_EN 0x00000001
158 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
159 * 40 connector cable and to 4 on 80 connector one.
160 * Clock unit is 15ns (66Mhz)
162 * 3 Values can be programmed:
163 * - Write data setup, which appears to match the cycle time. They
164 * also call it DIOW setup.
165 * - Ready to pause time (from spec)
166 * - Address setup. That one is weird. I don't see where exactly
167 * it fits in UDMA cycles, I got it's name from an obscure piece
168 * of commented out code in Darwin. They leave it to 0, we do as
169 * well, despite a comment that would lead to think it has a
171 * Apple also add 60ns to the write data setup (or cycle time ?) on
174 #define TR_66_UDMA_MASK 0xfff00000
175 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
176 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
177 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
178 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
179 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
180 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
181 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
182 #define TR_66_MDMA_MASK 0x000ffc00
183 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
184 #define TR_66_MDMA_RECOVERY_SHIFT 15
185 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
186 #define TR_66_MDMA_ACCESS_SHIFT 10
187 #define TR_66_PIO_MASK 0x000003ff
188 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
189 #define TR_66_PIO_RECOVERY_SHIFT 5
190 #define TR_66_PIO_ACCESS_MASK 0x0000001f
191 #define TR_66_PIO_ACCESS_SHIFT 0
193 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
194 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
196 * The access time and recovery time can be programmed. Some older
197 * Darwin code base limit OHare to 150ns cycle time. I decided to do
198 * the same here fore safety against broken old hardware ;)
199 * The HalfTick bit, when set, adds half a clock (15ns) to the access
200 * time and removes one from recovery. It's not supported on KeyLargo
201 * implementation afaik. The E bit appears to be set for PIO mode 0 and
202 * is used to reach long timings used in this mode.
204 #define TR_33_MDMA_MASK 0x003ff800
205 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
206 #define TR_33_MDMA_RECOVERY_SHIFT 16
207 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
208 #define TR_33_MDMA_ACCESS_SHIFT 11
209 #define TR_33_MDMA_HALFTICK 0x00200000
210 #define TR_33_PIO_MASK 0x000007ff
211 #define TR_33_PIO_E 0x00000400
212 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
213 #define TR_33_PIO_RECOVERY_SHIFT 5
214 #define TR_33_PIO_ACCESS_MASK 0x0000001f
215 #define TR_33_PIO_ACCESS_SHIFT 0
218 * Interrupt register definitions
220 #define IDE_INTR_DMA 0x80000000
221 #define IDE_INTR_DEVICE 0x40000000
224 * FCR Register on Kauai. Not sure what bit 0x4 is ...
226 #define KAUAI_FCR_UATA_MAGIC 0x00000004
227 #define KAUAI_FCR_UATA_RESET_N 0x00000002
228 #define KAUAI_FCR_UATA_ENABLE 0x00000001
230 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
232 /* Rounded Multiword DMA timings
234 * I gave up finding a generic formula for all controller
235 * types and instead, built tables based on timing values
236 * used by Apple in Darwin's implementation.
238 struct mdma_timings_t
{
244 struct mdma_timings_t mdma_timings_33
[] =
257 struct mdma_timings_t mdma_timings_33k
[] =
270 struct mdma_timings_t mdma_timings_66
[] =
283 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
285 int addrSetup
; /* ??? */
288 } kl66_udma_timings
[] =
290 { 0, 180, 120 }, /* Mode 0 */
291 { 0, 150, 90 }, /* 1 */
292 { 0, 120, 60 }, /* 2 */
293 { 0, 90, 45 }, /* 3 */
294 { 0, 90, 30 } /* 4 */
297 /* UniNorth 2 ATA/100 timings */
298 struct kauai_timing
{
303 static struct kauai_timing kauai_pio_timings
[] =
305 { 930 , 0x08000fff },
306 { 600 , 0x08000a92 },
307 { 383 , 0x0800060f },
308 { 360 , 0x08000492 },
309 { 330 , 0x0800048f },
310 { 300 , 0x080003cf },
311 { 270 , 0x080003cc },
312 { 240 , 0x0800038b },
313 { 239 , 0x0800030c },
314 { 180 , 0x05000249 },
315 { 120 , 0x04000148 },
319 static struct kauai_timing kauai_mdma_timings
[] =
321 { 1260 , 0x00fff000 },
322 { 480 , 0x00618000 },
323 { 360 , 0x00492000 },
324 { 270 , 0x0038e000 },
325 { 240 , 0x0030c000 },
326 { 210 , 0x002cb000 },
327 { 180 , 0x00249000 },
328 { 150 , 0x00209000 },
329 { 120 , 0x00148000 },
333 static struct kauai_timing kauai_udma_timings
[] =
335 { 120 , 0x000070c0 },
344 static struct kauai_timing shasta_pio_timings
[] =
346 { 930 , 0x08000fff },
347 { 600 , 0x0A000c97 },
348 { 383 , 0x07000712 },
349 { 360 , 0x040003cd },
350 { 330 , 0x040003cd },
351 { 300 , 0x040003cd },
352 { 270 , 0x040003cd },
353 { 240 , 0x040003cd },
354 { 239 , 0x040003cd },
355 { 180 , 0x0400028b },
356 { 120 , 0x0400010a },
360 static struct kauai_timing shasta_mdma_timings
[] =
362 { 1260 , 0x00fff000 },
363 { 480 , 0x00820800 },
364 { 360 , 0x00820800 },
365 { 270 , 0x00820800 },
366 { 240 , 0x00820800 },
367 { 210 , 0x00820800 },
368 { 180 , 0x00820800 },
369 { 150 , 0x0028b000 },
370 { 120 , 0x001ca000 },
374 static struct kauai_timing shasta_udma133_timings
[] =
376 { 120 , 0x00035901, },
377 { 90 , 0x000348b1, },
378 { 60 , 0x00033881, },
379 { 45 , 0x00033861, },
380 { 30 , 0x00033841, },
381 { 20 , 0x00033031, },
382 { 15 , 0x00033021, },
388 kauai_lookup_timing(struct kauai_timing
* table
, int cycle_time
)
392 for (i
=0; table
[i
].cycle_time
; i
++)
393 if (cycle_time
> table
[i
+1].cycle_time
)
394 return table
[i
].timing_reg
;
399 /* allow up to 256 DBDMA commands per xfer */
400 #define MAX_DCMDS 256
403 * Wait 1s for disk to answer on IDE bus after a hard reset
404 * of the device (via GPIO/FCR).
406 * Some devices seem to "pollute" the bus even after dropping
407 * the BSY bit (typically some combo drives slave on the UDMA
408 * bus) after a hard reset. Since we hard reset all drives on
409 * KeyLargo ATA66, we have to keep that delay around. I may end
410 * up not hard resetting anymore on these and keep the delay only
411 * for older interfaces instead (we have to reset when coming
412 * from MacOS...) --BenH.
414 #define IDE_WAKEUP_DELAY (1*HZ)
416 static void pmac_ide_setup_dma(pmac_ide_hwif_t
*pmif
, ide_hwif_t
*hwif
);
417 static int pmac_ide_build_dmatable(ide_drive_t
*drive
, struct request
*rq
);
418 static void pmac_ide_selectproc(ide_drive_t
*drive
);
419 static void pmac_ide_kauai_selectproc(ide_drive_t
*drive
);
421 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
424 * N.B. this can't be an initfunc, because the media-bay task can
425 * call ide_[un]register at any time.
428 pmac_ide_init_hwif_ports(hw_regs_t
*hw
,
429 unsigned long data_port
, unsigned long ctrl_port
,
437 for (ix
= 0; ix
< MAX_HWIFS
; ++ix
)
438 if (data_port
== pmac_ide
[ix
].regbase
)
441 if (ix
>= MAX_HWIFS
) {
442 /* Probably a PCI interface... */
443 for (i
= IDE_DATA_OFFSET
; i
<= IDE_STATUS_OFFSET
; ++i
)
444 hw
->io_ports
[i
] = data_port
+ i
- IDE_DATA_OFFSET
;
445 hw
->io_ports
[IDE_CONTROL_OFFSET
] = ctrl_port
;
449 for (i
= 0; i
< 8; ++i
)
450 hw
->io_ports
[i
] = data_port
+ i
* 0x10;
451 hw
->io_ports
[8] = data_port
+ 0x160;
454 *irq
= pmac_ide
[ix
].irq
;
456 hw
->dev
= &pmac_ide
[ix
].mdev
->ofdev
.dev
;
459 #define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
462 * Apply the timings of the proper unit (master/slave) to the shared
463 * timing register when selecting that unit. This version is for
464 * ASICs with a single timing register
467 pmac_ide_selectproc(ide_drive_t
*drive
)
469 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
474 if (drive
->select
.b
.unit
& 0x01)
475 writel(pmif
->timings
[1], PMAC_IDE_REG(IDE_TIMING_CONFIG
));
477 writel(pmif
->timings
[0], PMAC_IDE_REG(IDE_TIMING_CONFIG
));
478 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
482 * Apply the timings of the proper unit (master/slave) to the shared
483 * timing register when selecting that unit. This version is for
484 * ASICs with a dual timing register (Kauai)
487 pmac_ide_kauai_selectproc(ide_drive_t
*drive
)
489 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
494 if (drive
->select
.b
.unit
& 0x01) {
495 writel(pmif
->timings
[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
496 writel(pmif
->timings
[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG
));
498 writel(pmif
->timings
[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
499 writel(pmif
->timings
[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG
));
501 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
505 * Force an update of controller timing values for a given drive
508 pmac_ide_do_update_timings(ide_drive_t
*drive
)
510 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
515 if (pmif
->kind
== controller_sh_ata6
||
516 pmif
->kind
== controller_un_ata6
||
517 pmif
->kind
== controller_k2_ata6
)
518 pmac_ide_kauai_selectproc(drive
);
520 pmac_ide_selectproc(drive
);
524 pmac_outbsync(ide_drive_t
*drive
, u8 value
, unsigned long port
)
528 writeb(value
, (void __iomem
*) port
);
529 tmp
= readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
533 * Send the SET_FEATURE IDE command to the drive and update drive->id with
534 * the new state. We currently don't use the generic routine as it used to
535 * cause various trouble, especially with older mediabays.
536 * This code is sometimes triggering a spurrious interrupt though, I need
537 * to sort that out sooner or later and see if I can finally get the
538 * common version to work properly in all cases
541 pmac_ide_do_setfeature(ide_drive_t
*drive
, u8 command
)
543 ide_hwif_t
*hwif
= HWIF(drive
);
546 disable_irq_nosync(hwif
->irq
);
549 SELECT_MASK(drive
, 0);
551 /* Get rid of pending error state */
552 (void) hwif
->INB(IDE_STATUS_REG
);
553 /* Timeout bumped for some powerbooks */
554 if (wait_for_ready(drive
, 2000)) {
555 /* Timeout bumped for some powerbooks */
556 printk(KERN_ERR
"%s: pmac_ide_do_setfeature disk not ready "
557 "before SET_FEATURE!\n", drive
->name
);
561 hwif
->OUTB(drive
->ctl
| 2, IDE_CONTROL_REG
);
562 hwif
->OUTB(command
, IDE_NSECTOR_REG
);
563 hwif
->OUTB(SETFEATURES_XFER
, IDE_FEATURE_REG
);
564 hwif
->OUTBSYNC(drive
, WIN_SETFEATURES
, IDE_COMMAND_REG
);
566 /* Timeout bumped for some powerbooks */
567 result
= wait_for_ready(drive
, 2000);
568 hwif
->OUTB(drive
->ctl
, IDE_CONTROL_REG
);
570 printk(KERN_ERR
"%s: pmac_ide_do_setfeature disk not ready "
571 "after SET_FEATURE !\n", drive
->name
);
573 SELECT_MASK(drive
, 0);
575 drive
->id
->dma_ultra
&= ~0xFF00;
576 drive
->id
->dma_mword
&= ~0x0F00;
577 drive
->id
->dma_1word
&= ~0x0F00;
580 drive
->id
->dma_ultra
|= 0x8080; break;
582 drive
->id
->dma_ultra
|= 0x4040; break;
584 drive
->id
->dma_ultra
|= 0x2020; break;
586 drive
->id
->dma_ultra
|= 0x1010; break;
588 drive
->id
->dma_ultra
|= 0x0808; break;
590 drive
->id
->dma_ultra
|= 0x0404; break;
592 drive
->id
->dma_ultra
|= 0x0202; break;
594 drive
->id
->dma_ultra
|= 0x0101; break;
596 drive
->id
->dma_mword
|= 0x0404; break;
598 drive
->id
->dma_mword
|= 0x0202; break;
600 drive
->id
->dma_mword
|= 0x0101; break;
602 drive
->id
->dma_1word
|= 0x0404; break;
604 drive
->id
->dma_1word
|= 0x0202; break;
606 drive
->id
->dma_1word
|= 0x0101; break;
609 if (!drive
->init_speed
)
610 drive
->init_speed
= command
;
611 drive
->current_speed
= command
;
613 enable_irq(hwif
->irq
);
618 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
621 pmac_ide_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
624 unsigned accessTicks
, recTicks
;
625 unsigned accessTime
, recTime
;
626 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
627 unsigned int cycle_time
;
632 /* which drive is it ? */
633 timings
= &pmif
->timings
[drive
->select
.b
.unit
& 0x01];
635 cycle_time
= ide_pio_cycle_time(drive
, pio
);
637 switch (pmif
->kind
) {
638 case controller_sh_ata6
: {
640 u32 tr
= kauai_lookup_timing(shasta_pio_timings
, cycle_time
);
641 *timings
= ((*timings
) & ~TR_133_PIOREG_PIO_MASK
) | tr
;
644 case controller_un_ata6
:
645 case controller_k2_ata6
: {
647 u32 tr
= kauai_lookup_timing(kauai_pio_timings
, cycle_time
);
648 *timings
= ((*timings
) & ~TR_100_PIOREG_PIO_MASK
) | tr
;
651 case controller_kl_ata4
:
653 recTime
= cycle_time
- ide_pio_timings
[pio
].active_time
654 - ide_pio_timings
[pio
].setup_time
;
655 recTime
= max(recTime
, 150U);
656 accessTime
= ide_pio_timings
[pio
].active_time
;
657 accessTime
= max(accessTime
, 150U);
658 accessTicks
= SYSCLK_TICKS_66(accessTime
);
659 accessTicks
= min(accessTicks
, 0x1fU
);
660 recTicks
= SYSCLK_TICKS_66(recTime
);
661 recTicks
= min(recTicks
, 0x1fU
);
662 *timings
= ((*timings
) & ~TR_66_PIO_MASK
) |
663 (accessTicks
<< TR_66_PIO_ACCESS_SHIFT
) |
664 (recTicks
<< TR_66_PIO_RECOVERY_SHIFT
);
669 recTime
= cycle_time
- ide_pio_timings
[pio
].active_time
670 - ide_pio_timings
[pio
].setup_time
;
671 recTime
= max(recTime
, 150U);
672 accessTime
= ide_pio_timings
[pio
].active_time
;
673 accessTime
= max(accessTime
, 150U);
674 accessTicks
= SYSCLK_TICKS(accessTime
);
675 accessTicks
= min(accessTicks
, 0x1fU
);
676 accessTicks
= max(accessTicks
, 4U);
677 recTicks
= SYSCLK_TICKS(recTime
);
678 recTicks
= min(recTicks
, 0x1fU
);
679 recTicks
= max(recTicks
, 5U) - 4;
681 recTicks
--; /* guess, but it's only for PIO0, so... */
684 *timings
= ((*timings
) & ~TR_33_PIO_MASK
) |
685 (accessTicks
<< TR_33_PIO_ACCESS_SHIFT
) |
686 (recTicks
<< TR_33_PIO_RECOVERY_SHIFT
);
688 *timings
|= TR_33_PIO_E
;
693 #ifdef IDE_PMAC_DEBUG
694 printk(KERN_ERR
"%s: Set PIO timing for mode %d, reg: 0x%08x\n",
695 drive
->name
, pio
, *timings
);
698 if (pmac_ide_do_setfeature(drive
, XFER_PIO_0
+ pio
))
701 pmac_ide_do_update_timings(drive
);
704 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
707 * Calculate KeyLargo ATA/66 UDMA timings
710 set_timings_udma_ata4(u32
*timings
, u8 speed
)
712 unsigned rdyToPauseTicks
, wrDataSetupTicks
, addrTicks
;
714 if (speed
> XFER_UDMA_4
)
717 rdyToPauseTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].rdy2pause
);
718 wrDataSetupTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].wrDataSetup
);
719 addrTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].addrSetup
);
721 *timings
= ((*timings
) & ~(TR_66_UDMA_MASK
| TR_66_MDMA_MASK
)) |
722 (wrDataSetupTicks
<< TR_66_UDMA_WRDATASETUP_SHIFT
) |
723 (rdyToPauseTicks
<< TR_66_UDMA_RDY2PAUS_SHIFT
) |
724 (addrTicks
<<TR_66_UDMA_ADDRSETUP_SHIFT
) |
726 #ifdef IDE_PMAC_DEBUG
727 printk(KERN_ERR
"ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
728 speed
& 0xf, *timings
);
735 * Calculate Kauai ATA/100 UDMA timings
738 set_timings_udma_ata6(u32
*pio_timings
, u32
*ultra_timings
, u8 speed
)
740 struct ide_timing
*t
= ide_timing_find_mode(speed
);
743 if (speed
> XFER_UDMA_5
|| t
== NULL
)
745 tr
= kauai_lookup_timing(kauai_udma_timings
, (int)t
->udma
);
746 *ultra_timings
= ((*ultra_timings
) & ~TR_100_UDMAREG_UDMA_MASK
) | tr
;
747 *ultra_timings
= (*ultra_timings
) | TR_100_UDMAREG_UDMA_EN
;
753 * Calculate Shasta ATA/133 UDMA timings
756 set_timings_udma_shasta(u32
*pio_timings
, u32
*ultra_timings
, u8 speed
)
758 struct ide_timing
*t
= ide_timing_find_mode(speed
);
761 if (speed
> XFER_UDMA_6
|| t
== NULL
)
763 tr
= kauai_lookup_timing(shasta_udma133_timings
, (int)t
->udma
);
764 *ultra_timings
= ((*ultra_timings
) & ~TR_133_UDMAREG_UDMA_MASK
) | tr
;
765 *ultra_timings
= (*ultra_timings
) | TR_133_UDMAREG_UDMA_EN
;
771 * Calculate MDMA timings for all cells
774 set_timings_mdma(ide_drive_t
*drive
, int intf_type
, u32
*timings
, u32
*timings2
,
777 int cycleTime
, accessTime
= 0, recTime
= 0;
778 unsigned accessTicks
, recTicks
;
779 struct hd_driveid
*id
= drive
->id
;
780 struct mdma_timings_t
* tm
= NULL
;
783 /* Get default cycle time for mode */
784 switch(speed
& 0xf) {
785 case 0: cycleTime
= 480; break;
786 case 1: cycleTime
= 150; break;
787 case 2: cycleTime
= 120; break;
793 /* Check if drive provides explicit DMA cycle time */
794 if ((id
->field_valid
& 2) && id
->eide_dma_time
)
795 cycleTime
= max_t(int, id
->eide_dma_time
, cycleTime
);
797 /* OHare limits according to some old Apple sources */
798 if ((intf_type
== controller_ohare
) && (cycleTime
< 150))
800 /* Get the proper timing array for this controller */
802 case controller_sh_ata6
:
803 case controller_un_ata6
:
804 case controller_k2_ata6
:
806 case controller_kl_ata4
:
807 tm
= mdma_timings_66
;
809 case controller_kl_ata3
:
810 tm
= mdma_timings_33k
;
813 tm
= mdma_timings_33
;
817 /* Lookup matching access & recovery times */
820 if (tm
[i
+1].cycleTime
< cycleTime
)
824 cycleTime
= tm
[i
].cycleTime
;
825 accessTime
= tm
[i
].accessTime
;
826 recTime
= tm
[i
].recoveryTime
;
828 #ifdef IDE_PMAC_DEBUG
829 printk(KERN_ERR
"%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
830 drive
->name
, cycleTime
, accessTime
, recTime
);
834 case controller_sh_ata6
: {
836 u32 tr
= kauai_lookup_timing(shasta_mdma_timings
, cycleTime
);
837 *timings
= ((*timings
) & ~TR_133_PIOREG_MDMA_MASK
) | tr
;
838 *timings2
= (*timings2
) & ~TR_133_UDMAREG_UDMA_EN
;
840 case controller_un_ata6
:
841 case controller_k2_ata6
: {
843 u32 tr
= kauai_lookup_timing(kauai_mdma_timings
, cycleTime
);
844 *timings
= ((*timings
) & ~TR_100_PIOREG_MDMA_MASK
) | tr
;
845 *timings2
= (*timings2
) & ~TR_100_UDMAREG_UDMA_EN
;
848 case controller_kl_ata4
:
850 accessTicks
= SYSCLK_TICKS_66(accessTime
);
851 accessTicks
= min(accessTicks
, 0x1fU
);
852 accessTicks
= max(accessTicks
, 0x1U
);
853 recTicks
= SYSCLK_TICKS_66(recTime
);
854 recTicks
= min(recTicks
, 0x1fU
);
855 recTicks
= max(recTicks
, 0x3U
);
856 /* Clear out mdma bits and disable udma */
857 *timings
= ((*timings
) & ~(TR_66_MDMA_MASK
| TR_66_UDMA_MASK
)) |
858 (accessTicks
<< TR_66_MDMA_ACCESS_SHIFT
) |
859 (recTicks
<< TR_66_MDMA_RECOVERY_SHIFT
);
861 case controller_kl_ata3
:
862 /* 33Mhz cell on KeyLargo */
863 accessTicks
= SYSCLK_TICKS(accessTime
);
864 accessTicks
= max(accessTicks
, 1U);
865 accessTicks
= min(accessTicks
, 0x1fU
);
866 accessTime
= accessTicks
* IDE_SYSCLK_NS
;
867 recTicks
= SYSCLK_TICKS(recTime
);
868 recTicks
= max(recTicks
, 1U);
869 recTicks
= min(recTicks
, 0x1fU
);
870 *timings
= ((*timings
) & ~TR_33_MDMA_MASK
) |
871 (accessTicks
<< TR_33_MDMA_ACCESS_SHIFT
) |
872 (recTicks
<< TR_33_MDMA_RECOVERY_SHIFT
);
875 /* 33Mhz cell on others */
877 int origAccessTime
= accessTime
;
878 int origRecTime
= recTime
;
880 accessTicks
= SYSCLK_TICKS(accessTime
);
881 accessTicks
= max(accessTicks
, 1U);
882 accessTicks
= min(accessTicks
, 0x1fU
);
883 accessTime
= accessTicks
* IDE_SYSCLK_NS
;
884 recTicks
= SYSCLK_TICKS(recTime
);
885 recTicks
= max(recTicks
, 2U) - 1;
886 recTicks
= min(recTicks
, 0x1fU
);
887 recTime
= (recTicks
+ 1) * IDE_SYSCLK_NS
;
888 if ((accessTicks
> 1) &&
889 ((accessTime
- IDE_SYSCLK_NS
/2) >= origAccessTime
) &&
890 ((recTime
- IDE_SYSCLK_NS
/2) >= origRecTime
)) {
894 *timings
= ((*timings
) & ~TR_33_MDMA_MASK
) |
895 (accessTicks
<< TR_33_MDMA_ACCESS_SHIFT
) |
896 (recTicks
<< TR_33_MDMA_RECOVERY_SHIFT
);
898 *timings
|= TR_33_MDMA_HALFTICK
;
901 #ifdef IDE_PMAC_DEBUG
902 printk(KERN_ERR
"%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
903 drive
->name
, speed
& 0xf, *timings
);
906 #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
909 * Speedproc. This function is called by the core to set any of the standard
910 * DMA timing (MDMA or UDMA) to both the drive and the controller.
912 static int pmac_ide_tune_chipset(ide_drive_t
*drive
, const u8 speed
)
914 int unit
= (drive
->select
.b
.unit
& 0x01);
916 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
917 u32
*timings
, *timings2
, tl
[2];
919 timings
= &pmif
->timings
[unit
];
920 timings2
= &pmif
->timings
[unit
+2];
922 /* Copy timings to local image */
927 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
935 if (pmif
->kind
== controller_kl_ata4
)
936 ret
= set_timings_udma_ata4(&tl
[0], speed
);
937 else if (pmif
->kind
== controller_un_ata6
938 || pmif
->kind
== controller_k2_ata6
)
939 ret
= set_timings_udma_ata6(&tl
[0], &tl
[1], speed
);
940 else if (pmif
->kind
== controller_sh_ata6
)
941 ret
= set_timings_udma_shasta(&tl
[0], &tl
[1], speed
);
948 set_timings_mdma(drive
, pmif
->kind
, &tl
[0], &tl
[1], speed
);
954 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
961 ret
= pmac_ide_do_setfeature(drive
, speed
);
965 /* Apply timings to controller */
969 pmac_ide_do_update_timings(drive
);
975 * Blast some well known "safe" values to the timing registers at init or
976 * wakeup from sleep time, before we do real calculation
979 sanitize_timings(pmac_ide_hwif_t
*pmif
)
981 unsigned int value
, value2
= 0;
984 case controller_sh_ata6
:
988 case controller_un_ata6
:
989 case controller_k2_ata6
:
993 case controller_kl_ata4
:
996 case controller_kl_ata3
:
999 case controller_heathrow
:
1000 case controller_ohare
:
1005 pmif
->timings
[0] = pmif
->timings
[1] = value
;
1006 pmif
->timings
[2] = pmif
->timings
[3] = value2
;
1010 pmac_ide_get_base(int index
)
1012 return pmac_ide
[index
].regbase
;
1016 pmac_ide_check_base(unsigned long base
)
1020 for (ix
= 0; ix
< MAX_HWIFS
; ++ix
)
1021 if (base
== pmac_ide
[ix
].regbase
)
1027 pmac_ide_get_irq(unsigned long base
)
1031 for (ix
= 0; ix
< MAX_HWIFS
; ++ix
)
1032 if (base
== pmac_ide
[ix
].regbase
)
1033 return pmac_ide
[ix
].irq
;
1037 static int ide_majors
[] = { 3, 22, 33, 34, 56, 57 };
1040 pmac_find_ide_boot(char *bootdevice
, int n
)
1045 * Look through the list of IDE interfaces for this one.
1047 for (i
= 0; i
< pmac_ide_count
; ++i
) {
1049 if (!pmac_ide
[i
].node
|| !pmac_ide
[i
].node
->full_name
)
1051 name
= pmac_ide
[i
].node
->full_name
;
1052 if (memcmp(name
, bootdevice
, n
) == 0 && name
[n
] == 0) {
1053 /* XXX should cope with the 2nd drive as well... */
1054 return MKDEV(ide_majors
[i
], 0);
1061 /* Suspend call back, should be called after the child devices
1062 * have actually been suspended
1065 pmac_ide_do_suspend(ide_hwif_t
*hwif
)
1067 pmac_ide_hwif_t
*pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1069 /* We clear the timings */
1070 pmif
->timings
[0] = 0;
1071 pmif
->timings
[1] = 0;
1073 disable_irq(pmif
->irq
);
1075 /* The media bay will handle itself just fine */
1079 /* Kauai has bus control FCRs directly here */
1080 if (pmif
->kauai_fcr
) {
1081 u32 fcr
= readl(pmif
->kauai_fcr
);
1082 fcr
&= ~(KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
);
1083 writel(fcr
, pmif
->kauai_fcr
);
1086 /* Disable the bus on older machines and the cell on kauai */
1087 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, pmif
->node
, pmif
->aapl_bus_id
,
1093 /* Resume call back, should be called before the child devices
1097 pmac_ide_do_resume(ide_hwif_t
*hwif
)
1099 pmac_ide_hwif_t
*pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1101 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1102 if (!pmif
->mediabay
) {
1103 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, pmif
->node
, pmif
->aapl_bus_id
, 1);
1104 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, pmif
->node
, pmif
->aapl_bus_id
, 1);
1106 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, pmif
->node
, pmif
->aapl_bus_id
, 0);
1108 /* Kauai has it different */
1109 if (pmif
->kauai_fcr
) {
1110 u32 fcr
= readl(pmif
->kauai_fcr
);
1111 fcr
|= KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
;
1112 writel(fcr
, pmif
->kauai_fcr
);
1115 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY
));
1118 /* Sanitize drive timings */
1119 sanitize_timings(pmif
);
1121 enable_irq(pmif
->irq
);
1127 * Setup, register & probe an IDE channel driven by this driver, this is
1128 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1129 * that ends up beeing free of any device is not kept around by this driver
1130 * (it is kept in 2.4). This introduce an interface numbering change on some
1131 * rare machines unfortunately, but it's better this way.
1134 pmac_ide_setup_device(pmac_ide_hwif_t
*pmif
, ide_hwif_t
*hwif
)
1136 struct device_node
*np
= pmif
->node
;
1140 pmif
->broken_dma
= pmif
->broken_dma_warn
= 0;
1141 if (of_device_is_compatible(np
, "shasta-ata"))
1142 pmif
->kind
= controller_sh_ata6
;
1143 else if (of_device_is_compatible(np
, "kauai-ata"))
1144 pmif
->kind
= controller_un_ata6
;
1145 else if (of_device_is_compatible(np
, "K2-UATA"))
1146 pmif
->kind
= controller_k2_ata6
;
1147 else if (of_device_is_compatible(np
, "keylargo-ata")) {
1148 if (strcmp(np
->name
, "ata-4") == 0)
1149 pmif
->kind
= controller_kl_ata4
;
1151 pmif
->kind
= controller_kl_ata3
;
1152 } else if (of_device_is_compatible(np
, "heathrow-ata"))
1153 pmif
->kind
= controller_heathrow
;
1155 pmif
->kind
= controller_ohare
;
1156 pmif
->broken_dma
= 1;
1159 bidp
= of_get_property(np
, "AAPL,bus-id", NULL
);
1160 pmif
->aapl_bus_id
= bidp
? *bidp
: 0;
1162 /* Get cable type from device-tree */
1163 if (pmif
->kind
== controller_kl_ata4
|| pmif
->kind
== controller_un_ata6
1164 || pmif
->kind
== controller_k2_ata6
1165 || pmif
->kind
== controller_sh_ata6
) {
1166 const char* cable
= of_get_property(np
, "cable-type", NULL
);
1167 if (cable
&& !strncmp(cable
, "80-", 3))
1170 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1171 * they have a 80 conductor cable, this seem to be always the case unless
1172 * the user mucked around
1174 if (of_device_is_compatible(np
, "K2-UATA") ||
1175 of_device_is_compatible(np
, "shasta-ata"))
1178 /* On Kauai-type controllers, we make sure the FCR is correct */
1179 if (pmif
->kauai_fcr
)
1180 writel(KAUAI_FCR_UATA_MAGIC
|
1181 KAUAI_FCR_UATA_RESET_N
|
1182 KAUAI_FCR_UATA_ENABLE
, pmif
->kauai_fcr
);
1186 /* Make sure we have sane timings */
1187 sanitize_timings(pmif
);
1189 #ifndef CONFIG_PPC64
1190 /* XXX FIXME: Media bay stuff need re-organizing */
1191 if (np
->parent
&& np
->parent
->name
1192 && strcasecmp(np
->parent
->name
, "media-bay") == 0) {
1193 #ifdef CONFIG_PMAC_MEDIABAY
1194 media_bay_set_ide_infos(np
->parent
, pmif
->regbase
, pmif
->irq
, hwif
->index
);
1195 #endif /* CONFIG_PMAC_MEDIABAY */
1198 pmif
->aapl_bus_id
= 1;
1199 } else if (pmif
->kind
== controller_ohare
) {
1200 /* The code below is having trouble on some ohare machines
1201 * (timing related ?). Until I can put my hand on one of these
1202 * units, I keep the old way
1204 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, np
, 0, 1);
1208 /* This is necessary to enable IDE when net-booting */
1209 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, np
, pmif
->aapl_bus_id
, 1);
1210 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, np
, pmif
->aapl_bus_id
, 1);
1212 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, np
, pmif
->aapl_bus_id
, 0);
1213 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY
));
1216 /* Setup MMIO ops */
1217 default_hwif_mmiops(hwif
);
1218 hwif
->OUTBSYNC
= pmac_outbsync
;
1220 /* Tell common code _not_ to mess with resources */
1222 hwif
->hwif_data
= pmif
;
1223 pmac_ide_init_hwif_ports(&hwif
->hw
, pmif
->regbase
, 0, &hwif
->irq
);
1224 memcpy(hwif
->io_ports
, hwif
->hw
.io_ports
, sizeof(hwif
->io_ports
));
1225 hwif
->chipset
= ide_pmac
;
1226 hwif
->noprobe
= !hwif
->io_ports
[IDE_DATA_OFFSET
] || pmif
->mediabay
;
1227 hwif
->hold
= pmif
->mediabay
;
1228 hwif
->cbl
= pmif
->cable_80
? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
1229 hwif
->drives
[0].unmask
= 1;
1230 hwif
->drives
[1].unmask
= 1;
1231 hwif
->pio_mask
= ATA_PIO4
;
1232 hwif
->set_pio_mode
= pmac_ide_set_pio_mode
;
1233 if (pmif
->kind
== controller_un_ata6
1234 || pmif
->kind
== controller_k2_ata6
1235 || pmif
->kind
== controller_sh_ata6
)
1236 hwif
->selectproc
= pmac_ide_kauai_selectproc
;
1238 hwif
->selectproc
= pmac_ide_selectproc
;
1239 hwif
->speedproc
= pmac_ide_tune_chipset
;
1241 printk(KERN_INFO
"ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1242 hwif
->index
, model_name
[pmif
->kind
], pmif
->aapl_bus_id
,
1243 pmif
->mediabay
? " (mediabay)" : "", hwif
->irq
);
1245 #ifdef CONFIG_PMAC_MEDIABAY
1246 if (pmif
->mediabay
&& check_media_bay_by_base(pmif
->regbase
, MB_CD
) == 0)
1248 #endif /* CONFIG_PMAC_MEDIABAY */
1250 hwif
->sg_max_nents
= MAX_DCMDS
;
1252 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1253 /* has a DBDMA controller channel */
1255 pmac_ide_setup_dma(pmif
, hwif
);
1256 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1258 /* We probe the hwif now */
1259 probe_hwif_init(hwif
);
1261 ide_proc_register_port(hwif
);
1267 * Attach to a macio probed interface
1269 static int __devinit
1270 pmac_ide_macio_attach(struct macio_dev
*mdev
, const struct of_device_id
*match
)
1273 unsigned long regbase
;
1276 pmac_ide_hwif_t
*pmif
;
1280 while (i
< MAX_HWIFS
&& (ide_hwifs
[i
].io_ports
[IDE_DATA_OFFSET
] != 0
1281 || pmac_ide
[i
].node
!= NULL
))
1283 if (i
>= MAX_HWIFS
) {
1284 printk(KERN_ERR
"ide-pmac: MacIO interface attach with no slot\n");
1285 printk(KERN_ERR
" %s\n", mdev
->ofdev
.node
->full_name
);
1289 pmif
= &pmac_ide
[i
];
1290 hwif
= &ide_hwifs
[i
];
1292 if (macio_resource_count(mdev
) == 0) {
1293 printk(KERN_WARNING
"ide%d: no address for %s\n",
1294 i
, mdev
->ofdev
.node
->full_name
);
1298 /* Request memory resource for IO ports */
1299 if (macio_request_resource(mdev
, 0, "ide-pmac (ports)")) {
1300 printk(KERN_ERR
"ide%d: can't request mmio resource !\n", i
);
1304 /* XXX This is bogus. Should be fixed in the registry by checking
1305 * the kind of host interrupt controller, a bit like gatwick
1306 * fixes in irq.c. That works well enough for the single case
1307 * where that happens though...
1309 if (macio_irq_count(mdev
) == 0) {
1310 printk(KERN_WARNING
"ide%d: no intrs for device %s, using 13\n",
1311 i
, mdev
->ofdev
.node
->full_name
);
1312 irq
= irq_create_mapping(NULL
, 13);
1314 irq
= macio_irq(mdev
, 0);
1316 base
= ioremap(macio_resource_start(mdev
, 0), 0x400);
1317 regbase
= (unsigned long) base
;
1319 hwif
->pci_dev
= mdev
->bus
->pdev
;
1320 hwif
->gendev
.parent
= &mdev
->ofdev
.dev
;
1323 pmif
->node
= mdev
->ofdev
.node
;
1324 pmif
->regbase
= regbase
;
1326 pmif
->kauai_fcr
= NULL
;
1327 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1328 if (macio_resource_count(mdev
) >= 2) {
1329 if (macio_request_resource(mdev
, 1, "ide-pmac (dma)"))
1330 printk(KERN_WARNING
"ide%d: can't request DMA resource !\n", i
);
1332 pmif
->dma_regs
= ioremap(macio_resource_start(mdev
, 1), 0x1000);
1334 pmif
->dma_regs
= NULL
;
1335 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1336 dev_set_drvdata(&mdev
->ofdev
.dev
, hwif
);
1338 rc
= pmac_ide_setup_device(pmif
, hwif
);
1340 /* The inteface is released to the common IDE layer */
1341 dev_set_drvdata(&mdev
->ofdev
.dev
, NULL
);
1344 iounmap(pmif
->dma_regs
);
1345 memset(pmif
, 0, sizeof(*pmif
));
1346 macio_release_resource(mdev
, 0);
1348 macio_release_resource(mdev
, 1);
1355 pmac_ide_macio_suspend(struct macio_dev
*mdev
, pm_message_t mesg
)
1357 ide_hwif_t
*hwif
= (ide_hwif_t
*)dev_get_drvdata(&mdev
->ofdev
.dev
);
1360 if (mesg
.event
!= mdev
->ofdev
.dev
.power
.power_state
.event
1361 && mesg
.event
== PM_EVENT_SUSPEND
) {
1362 rc
= pmac_ide_do_suspend(hwif
);
1364 mdev
->ofdev
.dev
.power
.power_state
= mesg
;
1371 pmac_ide_macio_resume(struct macio_dev
*mdev
)
1373 ide_hwif_t
*hwif
= (ide_hwif_t
*)dev_get_drvdata(&mdev
->ofdev
.dev
);
1376 if (mdev
->ofdev
.dev
.power
.power_state
.event
!= PM_EVENT_ON
) {
1377 rc
= pmac_ide_do_resume(hwif
);
1379 mdev
->ofdev
.dev
.power
.power_state
= PMSG_ON
;
1386 * Attach to a PCI probed interface
1388 static int __devinit
1389 pmac_ide_pci_attach(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1392 struct device_node
*np
;
1393 pmac_ide_hwif_t
*pmif
;
1395 unsigned long rbase
, rlen
;
1398 np
= pci_device_to_OF_node(pdev
);
1400 printk(KERN_ERR
"ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1404 while (i
< MAX_HWIFS
&& (ide_hwifs
[i
].io_ports
[IDE_DATA_OFFSET
] != 0
1405 || pmac_ide
[i
].node
!= NULL
))
1407 if (i
>= MAX_HWIFS
) {
1408 printk(KERN_ERR
"ide-pmac: PCI interface attach with no slot\n");
1409 printk(KERN_ERR
" %s\n", np
->full_name
);
1413 pmif
= &pmac_ide
[i
];
1414 hwif
= &ide_hwifs
[i
];
1416 if (pci_enable_device(pdev
)) {
1417 printk(KERN_WARNING
"ide%i: Can't enable PCI device for %s\n",
1421 pci_set_master(pdev
);
1423 if (pci_request_regions(pdev
, "Kauai ATA")) {
1424 printk(KERN_ERR
"ide%d: Cannot obtain PCI resources for %s\n",
1429 hwif
->pci_dev
= pdev
;
1430 hwif
->gendev
.parent
= &pdev
->dev
;
1434 rbase
= pci_resource_start(pdev
, 0);
1435 rlen
= pci_resource_len(pdev
, 0);
1437 base
= ioremap(rbase
, rlen
);
1438 pmif
->regbase
= (unsigned long) base
+ 0x2000;
1439 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1440 pmif
->dma_regs
= base
+ 0x1000;
1441 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1442 pmif
->kauai_fcr
= base
;
1443 pmif
->irq
= pdev
->irq
;
1445 pci_set_drvdata(pdev
, hwif
);
1447 rc
= pmac_ide_setup_device(pmif
, hwif
);
1449 /* The inteface is released to the common IDE layer */
1450 pci_set_drvdata(pdev
, NULL
);
1452 memset(pmif
, 0, sizeof(*pmif
));
1453 pci_release_regions(pdev
);
1460 pmac_ide_pci_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1462 ide_hwif_t
*hwif
= (ide_hwif_t
*)pci_get_drvdata(pdev
);
1465 if (mesg
.event
!= pdev
->dev
.power
.power_state
.event
1466 && mesg
.event
== PM_EVENT_SUSPEND
) {
1467 rc
= pmac_ide_do_suspend(hwif
);
1469 pdev
->dev
.power
.power_state
= mesg
;
1476 pmac_ide_pci_resume(struct pci_dev
*pdev
)
1478 ide_hwif_t
*hwif
= (ide_hwif_t
*)pci_get_drvdata(pdev
);
1481 if (pdev
->dev
.power
.power_state
.event
!= PM_EVENT_ON
) {
1482 rc
= pmac_ide_do_resume(hwif
);
1484 pdev
->dev
.power
.power_state
= PMSG_ON
;
1490 static struct of_device_id pmac_ide_macio_match
[] =
1507 static struct macio_driver pmac_ide_macio_driver
=
1510 .match_table
= pmac_ide_macio_match
,
1511 .probe
= pmac_ide_macio_attach
,
1512 .suspend
= pmac_ide_macio_suspend
,
1513 .resume
= pmac_ide_macio_resume
,
1516 static struct pci_device_id pmac_ide_pci_match
[] = {
1517 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_ATA
,
1518 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1519 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_IPID_ATA100
,
1520 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1521 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_K2_ATA100
,
1522 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1523 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_SH_ATA
,
1524 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1525 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_IPID2_ATA
,
1526 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1530 static struct pci_driver pmac_ide_pci_driver
= {
1532 .id_table
= pmac_ide_pci_match
,
1533 .probe
= pmac_ide_pci_attach
,
1534 .suspend
= pmac_ide_pci_suspend
,
1535 .resume
= pmac_ide_pci_resume
,
1537 MODULE_DEVICE_TABLE(pci
, pmac_ide_pci_match
);
1539 int __init
pmac_ide_probe(void)
1543 if (!machine_is(powermac
))
1546 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1547 error
= pci_register_driver(&pmac_ide_pci_driver
);
1550 error
= macio_register_driver(&pmac_ide_macio_driver
);
1552 pci_unregister_driver(&pmac_ide_pci_driver
);
1556 error
= macio_register_driver(&pmac_ide_macio_driver
);
1559 error
= pci_register_driver(&pmac_ide_pci_driver
);
1561 macio_unregister_driver(&pmac_ide_macio_driver
);
1569 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1572 * pmac_ide_build_dmatable builds the DBDMA command list
1573 * for a transfer and sets the DBDMA channel to point to it.
1576 pmac_ide_build_dmatable(ide_drive_t
*drive
, struct request
*rq
)
1578 struct dbdma_cmd
*table
;
1580 ide_hwif_t
*hwif
= HWIF(drive
);
1581 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1582 volatile struct dbdma_regs __iomem
*dma
= pmif
->dma_regs
;
1583 struct scatterlist
*sg
;
1584 int wr
= (rq_data_dir(rq
) == WRITE
);
1586 /* DMA table is already aligned */
1587 table
= (struct dbdma_cmd
*) pmif
->dma_table_cpu
;
1589 /* Make sure DMA controller is stopped (necessary ?) */
1590 writel((RUN
|PAUSE
|FLUSH
|WAKE
|DEAD
) << 16, &dma
->control
);
1591 while (readl(&dma
->status
) & RUN
)
1594 hwif
->sg_nents
= i
= ide_build_sglist(drive
, rq
);
1599 /* Build DBDMA commands list */
1600 sg
= hwif
->sg_table
;
1601 while (i
&& sg_dma_len(sg
)) {
1605 cur_addr
= sg_dma_address(sg
);
1606 cur_len
= sg_dma_len(sg
);
1608 if (pmif
->broken_dma
&& cur_addr
& (L1_CACHE_BYTES
- 1)) {
1609 if (pmif
->broken_dma_warn
== 0) {
1610 printk(KERN_WARNING
"%s: DMA on non aligned address,"
1611 "switching to PIO on Ohare chipset\n", drive
->name
);
1612 pmif
->broken_dma_warn
= 1;
1614 goto use_pio_instead
;
1617 unsigned int tc
= (cur_len
< 0xfe00)? cur_len
: 0xfe00;
1619 if (count
++ >= MAX_DCMDS
) {
1620 printk(KERN_WARNING
"%s: DMA table too small\n",
1622 goto use_pio_instead
;
1624 st_le16(&table
->command
, wr
? OUTPUT_MORE
: INPUT_MORE
);
1625 st_le16(&table
->req_count
, tc
);
1626 st_le32(&table
->phy_addr
, cur_addr
);
1628 table
->xfer_status
= 0;
1629 table
->res_count
= 0;
1638 /* convert the last command to an input/output last command */
1640 st_le16(&table
[-1].command
, wr
? OUTPUT_LAST
: INPUT_LAST
);
1641 /* add the stop command to the end of the list */
1642 memset(table
, 0, sizeof(struct dbdma_cmd
));
1643 st_le16(&table
->command
, DBDMA_STOP
);
1645 writel(hwif
->dmatable_dma
, &dma
->cmdptr
);
1649 printk(KERN_DEBUG
"%s: empty DMA table?\n", drive
->name
);
1651 pci_unmap_sg(hwif
->pci_dev
,
1654 hwif
->sg_dma_direction
);
1655 return 0; /* revert to PIO for this request */
1658 /* Teardown mappings after DMA has completed. */
1660 pmac_ide_destroy_dmatable (ide_drive_t
*drive
)
1662 ide_hwif_t
*hwif
= drive
->hwif
;
1663 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
1664 struct scatterlist
*sg
= hwif
->sg_table
;
1665 int nents
= hwif
->sg_nents
;
1668 pci_unmap_sg(dev
, sg
, nents
, hwif
->sg_dma_direction
);
1674 * Check what is the best DMA timing setting for the drive and
1675 * call appropriate functions to apply it.
1678 pmac_ide_dma_check(ide_drive_t
*drive
)
1682 drive
->using_dma
= 0;
1684 if (drive
->media
== ide_floppy
)
1686 if ((drive
->id
->capability
& 1) == 0 && !__ide_dma_good_drive(drive
))
1688 if (__ide_dma_bad_drive(drive
))
1692 u8 mode
= ide_max_dma_mode(drive
);
1694 if (mode
&& pmac_ide_tune_chipset(drive
, mode
) == 0)
1695 drive
->using_dma
= 1;
1701 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1702 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1705 pmac_ide_dma_setup(ide_drive_t
*drive
)
1707 ide_hwif_t
*hwif
= HWIF(drive
);
1708 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1709 struct request
*rq
= HWGROUP(drive
)->rq
;
1710 u8 unit
= (drive
->select
.b
.unit
& 0x01);
1715 ata4
= (pmif
->kind
== controller_kl_ata4
);
1717 if (!pmac_ide_build_dmatable(drive
, rq
)) {
1718 ide_map_sg(drive
, rq
);
1722 /* Apple adds 60ns to wrDataSetup on reads */
1723 if (ata4
&& (pmif
->timings
[unit
] & TR_66_UDMA_EN
)) {
1724 writel(pmif
->timings
[unit
] + (!rq_data_dir(rq
) ? 0x00800000UL
: 0),
1725 PMAC_IDE_REG(IDE_TIMING_CONFIG
));
1726 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
1729 drive
->waiting_for_dma
= 1;
1735 pmac_ide_dma_exec_cmd(ide_drive_t
*drive
, u8 command
)
1737 /* issue cmd to drive */
1738 ide_execute_command(drive
, command
, &ide_dma_intr
, 2*WAIT_CMD
, NULL
);
1742 * Kick the DMA controller into life after the DMA command has been issued
1746 pmac_ide_dma_start(ide_drive_t
*drive
)
1748 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1749 volatile struct dbdma_regs __iomem
*dma
;
1751 dma
= pmif
->dma_regs
;
1753 writel((RUN
<< 16) | RUN
, &dma
->control
);
1754 /* Make sure it gets to the controller right now */
1755 (void)readl(&dma
->control
);
1759 * After a DMA transfer, make sure the controller is stopped
1762 pmac_ide_dma_end (ide_drive_t
*drive
)
1764 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1765 volatile struct dbdma_regs __iomem
*dma
;
1770 dma
= pmif
->dma_regs
;
1772 drive
->waiting_for_dma
= 0;
1773 dstat
= readl(&dma
->status
);
1774 writel(((RUN
|WAKE
|DEAD
) << 16), &dma
->control
);
1775 pmac_ide_destroy_dmatable(drive
);
1776 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1777 * in theory, but with ATAPI decices doing buffer underruns, that would
1778 * cause us to disable DMA, which isn't what we want
1780 return (dstat
& (RUN
|DEAD
)) != RUN
;
1784 * Check out that the interrupt we got was for us. We can't always know this
1785 * for sure with those Apple interfaces (well, we could on the recent ones but
1786 * that's not implemented yet), on the other hand, we don't have shared interrupts
1787 * so it's not really a problem
1790 pmac_ide_dma_test_irq (ide_drive_t
*drive
)
1792 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1793 volatile struct dbdma_regs __iomem
*dma
;
1794 unsigned long status
, timeout
;
1798 dma
= pmif
->dma_regs
;
1800 /* We have to things to deal with here:
1802 * - The dbdma won't stop if the command was started
1803 * but completed with an error without transferring all
1804 * datas. This happens when bad blocks are met during
1805 * a multi-block transfer.
1807 * - The dbdma fifo hasn't yet finished flushing to
1808 * to system memory when the disk interrupt occurs.
1812 /* If ACTIVE is cleared, the STOP command have passed and
1813 * transfer is complete.
1815 status
= readl(&dma
->status
);
1816 if (!(status
& ACTIVE
))
1818 if (!drive
->waiting_for_dma
)
1819 printk(KERN_WARNING
"ide%d, ide_dma_test_irq \
1820 called while not waiting\n", HWIF(drive
)->index
);
1822 /* If dbdma didn't execute the STOP command yet, the
1823 * active bit is still set. We consider that we aren't
1824 * sharing interrupts (which is hopefully the case with
1825 * those controllers) and so we just try to flush the
1826 * channel for pending data in the fifo
1829 writel((FLUSH
<< 16) | FLUSH
, &dma
->control
);
1833 status
= readl(&dma
->status
);
1834 if ((status
& FLUSH
) == 0)
1836 if (++timeout
> 100) {
1837 printk(KERN_WARNING
"ide%d, ide_dma_test_irq \
1838 timeout flushing channel\n", HWIF(drive
)->index
);
1845 static void pmac_ide_dma_host_off(ide_drive_t
*drive
)
1849 static void pmac_ide_dma_host_on(ide_drive_t
*drive
)
1854 pmac_ide_dma_lost_irq (ide_drive_t
*drive
)
1856 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1857 volatile struct dbdma_regs __iomem
*dma
;
1858 unsigned long status
;
1862 dma
= pmif
->dma_regs
;
1864 status
= readl(&dma
->status
);
1865 printk(KERN_ERR
"ide-pmac lost interrupt, dma status: %lx\n", status
);
1869 * Allocate the data structures needed for using DMA with an interface
1870 * and fill the proper list of functions pointers
1873 pmac_ide_setup_dma(pmac_ide_hwif_t
*pmif
, ide_hwif_t
*hwif
)
1875 /* We won't need pci_dev if we switch to generic consistent
1878 if (hwif
->pci_dev
== NULL
)
1881 * Allocate space for the DBDMA commands.
1882 * The +2 is +1 for the stop command and +1 to allow for
1883 * aligning the start address to a multiple of 16 bytes.
1885 pmif
->dma_table_cpu
= (struct dbdma_cmd
*)pci_alloc_consistent(
1887 (MAX_DCMDS
+ 2) * sizeof(struct dbdma_cmd
),
1888 &hwif
->dmatable_dma
);
1889 if (pmif
->dma_table_cpu
== NULL
) {
1890 printk(KERN_ERR
"%s: unable to allocate DMA command list\n",
1895 hwif
->dma_off_quietly
= &ide_dma_off_quietly
;
1896 hwif
->ide_dma_on
= &__ide_dma_on
;
1897 hwif
->ide_dma_check
= &pmac_ide_dma_check
;
1898 hwif
->dma_setup
= &pmac_ide_dma_setup
;
1899 hwif
->dma_exec_cmd
= &pmac_ide_dma_exec_cmd
;
1900 hwif
->dma_start
= &pmac_ide_dma_start
;
1901 hwif
->ide_dma_end
= &pmac_ide_dma_end
;
1902 hwif
->ide_dma_test_irq
= &pmac_ide_dma_test_irq
;
1903 hwif
->dma_host_off
= &pmac_ide_dma_host_off
;
1904 hwif
->dma_host_on
= &pmac_ide_dma_host_on
;
1905 hwif
->dma_timeout
= &ide_dma_timeout
;
1906 hwif
->dma_lost_irq
= &pmac_ide_dma_lost_irq
;
1908 hwif
->atapi_dma
= 1;
1909 switch(pmif
->kind
) {
1910 case controller_sh_ata6
:
1911 hwif
->ultra_mask
= pmif
->cable_80
? 0x7f : 0x07;
1912 hwif
->mwdma_mask
= 0x07;
1913 hwif
->swdma_mask
= 0x00;
1915 case controller_un_ata6
:
1916 case controller_k2_ata6
:
1917 hwif
->ultra_mask
= pmif
->cable_80
? 0x3f : 0x07;
1918 hwif
->mwdma_mask
= 0x07;
1919 hwif
->swdma_mask
= 0x00;
1921 case controller_kl_ata4
:
1922 hwif
->ultra_mask
= pmif
->cable_80
? 0x1f : 0x07;
1923 hwif
->mwdma_mask
= 0x07;
1924 hwif
->swdma_mask
= 0x00;
1927 hwif
->ultra_mask
= 0x00;
1928 hwif
->mwdma_mask
= 0x07;
1929 hwif
->swdma_mask
= 0x00;
1934 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */