drivers/ide/scc_pata.c

   1 /*
   2  * Support for IDE interfaces on Celleb platform
   3  *
   4  * (C) Copyright 2006 TOSHIBA CORPORATION
   5  *
   6  * This code is based on drivers/ide/pci/siimage.c:
   7  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   8  * Copyright (C) 2003           Red Hat
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, write to the Free Software Foundation, Inc.,
  22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23  */
  24
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/delay.h>
  29 #include <linux/ide.h>
  30 #include <linux/init.h>
  31
  32 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA            0x01b4
  33
  34 #define SCC_PATA_NAME           "scc IDE"
  35
  36 #define TDVHSEL_MASTER          0x00000001
  37 #define TDVHSEL_SLAVE           0x00000004
  38
  39 #define MODE_JCUSFEN            0x00000080
  40
  41 #define CCKCTRL_ATARESET        0x00040000
  42 #define CCKCTRL_BUFCNT          0x00020000
  43 #define CCKCTRL_CRST            0x00010000
  44 #define CCKCTRL_OCLKEN          0x00000100
  45 #define CCKCTRL_ATACLKOEN       0x00000002
  46 #define CCKCTRL_LCLKEN          0x00000001
  47
  48 #define QCHCD_IOS_SS            0x00000001
  49
  50 #define QCHSD_STPDIAG           0x00020000
  51
  52 #define INTMASK_MSK             0xD1000012
  53 #define INTSTS_SERROR           0x80000000
  54 #define INTSTS_PRERR            0x40000000
  55 #define INTSTS_RERR             0x10000000
  56 #define INTSTS_ICERR            0x01000000
  57 #define INTSTS_BMSINT           0x00000010
  58 #define INTSTS_BMHE             0x00000008
  59 #define INTSTS_IOIRQS           0x00000004
  60 #define INTSTS_INTRQ            0x00000002
  61 #define INTSTS_ACTEINT          0x00000001
  62
  63 #define ECMODE_VALUE 0x01
  64
  65 static struct scc_ports {
  66         unsigned long ctl, dma;
  67         struct ide_host *host;  /* for removing port from system */
  68 } scc_ports[MAX_HWIFS];
  69
  70 /* PIO transfer mode  table */
  71 /* JCHST */
  72 static unsigned long JCHSTtbl[2][7] = {
  73         {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00},   /* 100MHz */
  74         {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00}    /* 133MHz */
  75 };
  76
  77 /* JCHHT */
  78 static unsigned long JCHHTtbl[2][7] = {
  79         {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00},   /* 100MHz */
  80         {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}    /* 133MHz */
  81 };
  82
  83 /* JCHCT */
  84 static unsigned long JCHCTtbl[2][7] = {
  85         {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00},   /* 100MHz */
  86         {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00}    /* 133MHz */
  87 };
  88
  89
  90 /* DMA transfer mode  table */
  91 /* JCHDCTM/JCHDCTS */
  92 static unsigned long JCHDCTxtbl[2][7] = {
  93         {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00},   /* 100MHz */
  94         {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00}    /* 133MHz */
  95 };
  96
  97 /* JCSTWTM/JCSTWTS  */
  98 static unsigned long JCSTWTxtbl[2][7] = {
  99         {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00},   /* 100MHz */
 100         {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 101 };
 102
 103 /* JCTSS */
 104 static unsigned long JCTSStbl[2][7] = {
 105         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00},   /* 100MHz */
 106         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05}    /* 133MHz */
 107 };
 108
 109 /* JCENVT */
 110 static unsigned long JCENVTtbl[2][7] = {
 111         {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},   /* 100MHz */
 112         {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 113 };
 114
 115 /* JCACTSELS/JCACTSELM */
 116 static unsigned long JCACTSELtbl[2][7] = {
 117         {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00},   /* 100MHz */
 118         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}    /* 133MHz */
 119 };
 120
 121
 122 static u8 scc_ide_inb(unsigned long port)
 123 {
 124         u32 data = in_be32((void*)port);
 125         return (u8)data;
 126 }
 127
 128 static void scc_exec_command(ide_hwif_t *hwif, u8 cmd)
 129 {
 130         out_be32((void *)hwif->io_ports.command_addr, cmd);
 131         eieio();
 132         in_be32((void *)(hwif->dma_base + 0x01c));
 133         eieio();
 134 }
 135
 136 static u8 scc_read_status(ide_hwif_t *hwif)
 137 {
 138         return (u8)in_be32((void *)hwif->io_ports.status_addr);
 139 }
 140
 141 static u8 scc_read_altstatus(ide_hwif_t *hwif)
 142 {
 143         return (u8)in_be32((void *)hwif->io_ports.ctl_addr);
 144 }
 145
 146 static u8 scc_read_sff_dma_status(ide_hwif_t *hwif)
 147 {
 148         return (u8)in_be32((void *)(hwif->dma_base + 4));
 149 }
 150
 151 static void scc_set_irq(ide_hwif_t *hwif, int on)
 152 {
 153         u8 ctl = ATA_DEVCTL_OBS;
 154
 155         if (on == 4) { /* hack for SRST */
 156                 ctl |= 4;
 157                 on &= ~4;
 158         }
 159
 160         ctl |= on ? 0 : 2;
 161
 162         out_be32((void *)hwif->io_ports.ctl_addr, ctl);
 163         eieio();
 164         in_be32((void *)(hwif->dma_base + 0x01c));
 165         eieio();
 166 }
 167
 168 static void scc_ide_insw(unsigned long port, void *addr, u32 count)
 169 {
 170         u16 *ptr = (u16 *)addr;
 171         while (count--) {
 172                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 173         }
 174 }
 175
 176 static void scc_ide_insl(unsigned long port, void *addr, u32 count)
 177 {
 178         u16 *ptr = (u16 *)addr;
 179         while (count--) {
 180                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 181                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 182         }
 183 }
 184
 185 static void scc_ide_outb(u8 addr, unsigned long port)
 186 {
 187         out_be32((void*)port, addr);
 188 }
 189
 190 static void
 191 scc_ide_outsw(unsigned long port, void *addr, u32 count)
 192 {
 193         u16 *ptr = (u16 *)addr;
 194         while (count--) {
 195                 out_be32((void*)port, cpu_to_le16(*ptr++));
 196         }
 197 }
 198
 199 static void
 200 scc_ide_outsl(unsigned long port, void *addr, u32 count)
 201 {
 202         u16 *ptr = (u16 *)addr;
 203         while (count--) {
 204                 out_be32((void*)port, cpu_to_le16(*ptr++));
 205                 out_be32((void*)port, cpu_to_le16(*ptr++));
 206         }
 207 }
 208
 209 /**
 210  *      scc_set_pio_mode        -       set host controller for PIO mode
 211  *      @drive: drive
 212  *      @pio: PIO mode number
 213  *
 214  *      Load the timing settings for this device mode into the
 215  *      controller.
 216  */
 217
 218 static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
 219 {
 220         ide_hwif_t *hwif = HWIF(drive);
 221         struct scc_ports *ports = ide_get_hwifdata(hwif);
 222         unsigned long ctl_base = ports->ctl;
 223         unsigned long cckctrl_port = ctl_base + 0xff0;
 224         unsigned long piosht_port = ctl_base + 0x000;
 225         unsigned long pioct_port = ctl_base + 0x004;
 226         unsigned long reg;
 227         int offset;
 228
 229         reg = in_be32((void __iomem *)cckctrl_port);
 230         if (reg & CCKCTRL_ATACLKOEN) {
 231                 offset = 1; /* 133MHz */
 232         } else {
 233                 offset = 0; /* 100MHz */
 234         }
 235         reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
 236         out_be32((void __iomem *)piosht_port, reg);
 237         reg = JCHCTtbl[offset][pio];
 238         out_be32((void __iomem *)pioct_port, reg);
 239 }
 240
 241 /**
 242  *      scc_set_dma_mode        -       set host controller for DMA mode
 243  *      @drive: drive
 244  *      @speed: DMA mode
 245  *
 246  *      Load the timing settings for this device mode into the
 247  *      controller.
 248  */
 249
 250 static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
 251 {
 252         ide_hwif_t *hwif = HWIF(drive);
 253         struct scc_ports *ports = ide_get_hwifdata(hwif);
 254         unsigned long ctl_base = ports->ctl;
 255         unsigned long cckctrl_port = ctl_base + 0xff0;
 256         unsigned long mdmact_port = ctl_base + 0x008;
 257         unsigned long mcrcst_port = ctl_base + 0x00c;
 258         unsigned long sdmact_port = ctl_base + 0x010;
 259         unsigned long scrcst_port = ctl_base + 0x014;
 260         unsigned long udenvt_port = ctl_base + 0x018;
 261         unsigned long tdvhsel_port   = ctl_base + 0x020;
 262         int is_slave = (&hwif->drives[1] == drive);
 263         int offset, idx;
 264         unsigned long reg;
 265         unsigned long jcactsel;
 266
 267         reg = in_be32((void __iomem *)cckctrl_port);
 268         if (reg & CCKCTRL_ATACLKOEN) {
 269                 offset = 1; /* 133MHz */
 270         } else {
 271                 offset = 0; /* 100MHz */
 272         }
 273
 274         idx = speed - XFER_UDMA_0;
 275
 276         jcactsel = JCACTSELtbl[offset][idx];
 277         if (is_slave) {
 278                 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
 279                 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
 280                 jcactsel = jcactsel << 2;
 281                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
 282         } else {
 283                 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
 284                 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
 285                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
 286         }
 287         reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
 288         out_be32((void __iomem *)udenvt_port, reg);
 289 }
 290
 291 static void scc_dma_host_set(ide_drive_t *drive, int on)
 292 {
 293         ide_hwif_t *hwif = drive->hwif;
 294         u8 unit = drive->dn & 1;
 295         u8 dma_stat = scc_ide_inb(hwif->dma_base + 4);
 296
 297         if (on)
 298                 dma_stat |= (1 << (5 + unit));
 299         else
 300                 dma_stat &= ~(1 << (5 + unit));
 301
 302         scc_ide_outb(dma_stat, hwif->dma_base + 4);
 303 }
 304
 305 /**
 306  *      scc_ide_dma_setup       -       begin a DMA phase
 307  *      @drive: target device
 308  *
 309  *      Build an IDE DMA PRD (IDE speak for scatter gather table)
 310  *      and then set up the DMA transfer registers.
 311  *
 312  *      Returns 0 on success. If a PIO fallback is required then 1
 313  *      is returned.
 314  */
 315
 316 static int scc_dma_setup(ide_drive_t *drive)
 317 {
 318         ide_hwif_t *hwif = drive->hwif;
 319         struct request *rq = HWGROUP(drive)->rq;
 320         unsigned int reading;
 321         u8 dma_stat;
 322
 323         if (rq_data_dir(rq))
 324                 reading = 0;
 325         else
 326                 reading = 1 << 3;
 327
 328         /* fall back to pio! */
 329         if (!ide_build_dmatable(drive, rq)) {
 330                 ide_map_sg(drive, rq);
 331                 return 1;
 332         }
 333
 334         /* PRD table */
 335         out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);
 336
 337         /* specify r/w */
 338         out_be32((void __iomem *)hwif->dma_base, reading);
 339
 340         /* read DMA status for INTR & ERROR flags */
 341         dma_stat = in_be32((void __iomem *)(hwif->dma_base + 4));
 342
 343         /* clear INTR & ERROR flags */
 344         out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6);
 345         drive->waiting_for_dma = 1;
 346         return 0;
 347 }
 348
 349 static void scc_dma_start(ide_drive_t *drive)
 350 {
 351         ide_hwif_t *hwif = drive->hwif;
 352         u8 dma_cmd = scc_ide_inb(hwif->dma_base);
 353
 354         /* start DMA */
 355         scc_ide_outb(dma_cmd | 1, hwif->dma_base);
 356         wmb();
 357 }
 358
 359 static int __scc_dma_end(ide_drive_t *drive)
 360 {
 361         ide_hwif_t *hwif = drive->hwif;
 362         u8 dma_stat, dma_cmd;
 363
 364         drive->waiting_for_dma = 0;
 365         /* get DMA command mode */
 366         dma_cmd = scc_ide_inb(hwif->dma_base);
 367         /* stop DMA */
 368         scc_ide_outb(dma_cmd & ~1, hwif->dma_base);
 369         /* get DMA status */
 370         dma_stat = scc_ide_inb(hwif->dma_base + 4);
 371         /* clear the INTR & ERROR bits */
 372         scc_ide_outb(dma_stat | 6, hwif->dma_base + 4);
 373         /* purge DMA mappings */
 374         ide_destroy_dmatable(drive);
 375         /* verify good DMA status */
 376         wmb();
 377         return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
 378 }
 379
 380 /**
 381  *      scc_dma_end     -       Stop DMA
 382  *      @drive: IDE drive
 383  *
 384  *      Check and clear INT Status register.
 385  *      Then call __scc_dma_end().
 386  */
 387
 388 static int scc_dma_end(ide_drive_t *drive)
 389 {
 390         ide_hwif_t *hwif = HWIF(drive);
 391         void __iomem *dma_base = (void __iomem *)hwif->dma_base;
 392         unsigned long intsts_port = hwif->dma_base + 0x014;
 393         u32 reg;
 394         int dma_stat, data_loss = 0;
 395         static int retry = 0;
 396
 397         /* errata A308 workaround: Step5 (check data loss) */
 398         /* We don't check non ide_disk because it is limited to UDMA4 */
 399         if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)
 400               & ATA_ERR) &&
 401             drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
 402                 reg = in_be32((void __iomem *)intsts_port);
 403                 if (!(reg & INTSTS_ACTEINT)) {
 404                         printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
 405                                drive->name);
 406                         data_loss = 1;
 407                         if (retry++) {
 408                                 struct request *rq = HWGROUP(drive)->rq;
 409                                 int unit;
 410                                 /* ERROR_RESET and drive->crc_count are needed
 411                                  * to reduce DMA transfer mode in retry process.
 412                                  */
 413                                 if (rq)
 414                                         rq->errors |= ERROR_RESET;
 415                                 for (unit = 0; unit < MAX_DRIVES; unit++) {
 416                                         ide_drive_t *drive = &hwif->drives[unit];
 417                                         drive->crc_count++;
 418                                 }
 419                         }
 420                 }
 421         }
 422
 423         while (1) {
 424                 reg = in_be32((void __iomem *)intsts_port);
 425
 426                 if (reg & INTSTS_SERROR) {
 427                         printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
 428                         out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
 429
 430                         out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
 431                         continue;
 432                 }
 433
 434                 if (reg & INTSTS_PRERR) {
 435                         u32 maea0, maec0;
 436                         unsigned long ctl_base = hwif->config_data;
 437
 438                         maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
 439                         maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
 440
 441                         printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
 442
 443                         out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
 444
 445                         out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
 446                         continue;
 447                 }
 448
 449                 if (reg & INTSTS_RERR) {
 450                         printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
 451                         out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
 452
 453                         out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
 454                         continue;
 455                 }
 456
 457                 if (reg & INTSTS_ICERR) {
 458                         out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
 459
 460                         printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
 461                         out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
 462                         continue;
 463                 }
 464
 465                 if (reg & INTSTS_BMSINT) {
 466                         printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
 467                         out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
 468
 469                         ide_do_reset(drive);
 470                         continue;
 471                 }
 472
 473                 if (reg & INTSTS_BMHE) {
 474                         out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
 475                         continue;
 476                 }
 477
 478                 if (reg & INTSTS_ACTEINT) {
 479                         out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
 480                         continue;
 481                 }
 482
 483                 if (reg & INTSTS_IOIRQS) {
 484                         out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
 485                         continue;
 486                 }
 487                 break;
 488         }
 489
 490         dma_stat = __scc_dma_end(drive);
 491         if (data_loss)
 492                 dma_stat |= 2; /* emulate DMA error (to retry command) */
 493         return dma_stat;
 494 }
 495
 496 /* returns 1 if dma irq issued, 0 otherwise */
 497 static int scc_dma_test_irq(ide_drive_t *drive)
 498 {
 499         ide_hwif_t *hwif = HWIF(drive);
 500         u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
 501
 502         /* SCC errata A252,A308 workaround: Step4 */
 503         if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)
 504              & ATA_ERR) &&
 505             (int_stat & INTSTS_INTRQ))
 506                 return 1;
 507
 508         /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
 509         if (int_stat & INTSTS_IOIRQS)
 510                 return 1;
 511
 512         return 0;
 513 }
 514
 515 static u8 scc_udma_filter(ide_drive_t *drive)
 516 {
 517         ide_hwif_t *hwif = drive->hwif;
 518         u8 mask = hwif->ultra_mask;
 519
 520         /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
 521         if ((drive->media != ide_disk) && (mask & 0xE0)) {
 522                 printk(KERN_INFO "%s: limit %s to UDMA4\n",
 523                        SCC_PATA_NAME, drive->name);
 524                 mask = ATA_UDMA4;
 525         }
 526
 527         return mask;
 528 }
 529
 530 /**
 531  *      setup_mmio_scc  -       map CTRL/BMID region
 532  *      @dev: PCI device we are configuring
 533  *      @name: device name
 534  *
 535  */
 536
 537 static int setup_mmio_scc (struct pci_dev *dev, const char *name)
 538 {
 539         void __iomem *ctl_addr;
 540         void __iomem *dma_addr;
 541         int i, ret;
 542
 543         for (i = 0; i < MAX_HWIFS; i++) {
 544                 if (scc_ports[i].ctl == 0)
 545                         break;
 546         }
 547         if (i >= MAX_HWIFS)
 548                 return -ENOMEM;
 549
 550         ret = pci_request_selected_regions(dev, (1 << 2) - 1, name);
 551         if (ret < 0) {
 552                 printk(KERN_ERR "%s: can't reserve resources\n", name);
 553                 return ret;
 554         }
 555
 556         ctl_addr = pci_ioremap_bar(dev, 0);
 557         if (!ctl_addr)
 558                 goto fail_0;
 559
 560         dma_addr = pci_ioremap_bar(dev, 1);
 561         if (!dma_addr)
 562                 goto fail_1;
 563
 564         pci_set_master(dev);
 565         scc_ports[i].ctl = (unsigned long)ctl_addr;
 566         scc_ports[i].dma = (unsigned long)dma_addr;
 567         pci_set_drvdata(dev, (void *) &scc_ports[i]);
 568
 569         return 1;
 570
 571  fail_1:
 572         iounmap(ctl_addr);
 573  fail_0:
 574         return -ENOMEM;
 575 }
 576
 577 static int scc_ide_setup_pci_device(struct pci_dev *dev,
 578                                     const struct ide_port_info *d)
 579 {
 580         struct scc_ports *ports = pci_get_drvdata(dev);
 581         struct ide_host *host;
 582         hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
 583         int i, rc;
 584
 585         memset(&hw, 0, sizeof(hw));
 586         for (i = 0; i <= 8; i++)
 587                 hw.io_ports_array[i] = ports->dma + 0x20 + i * 4;
 588         hw.irq = dev->irq;
 589         hw.dev = &dev->dev;
 590         hw.chipset = ide_pci;
 591
 592         rc = ide_host_add(d, hws, &host);
 593         if (rc)
 594                 return rc;
 595
 596         ports->host = host;
 597
 598         return 0;
 599 }
 600
 601 /**
 602  *      init_setup_scc  -       set up an SCC PATA Controller
 603  *      @dev: PCI device
 604  *      @d: IDE port info
 605  *
 606  *      Perform the initial set up for this device.
 607  */
 608
 609 static int __devinit init_setup_scc(struct pci_dev *dev,
 610                                     const struct ide_port_info *d)
 611 {
 612         unsigned long ctl_base;
 613         unsigned long dma_base;
 614         unsigned long cckctrl_port;
 615         unsigned long intmask_port;
 616         unsigned long mode_port;
 617         unsigned long ecmode_port;
 618         u32 reg = 0;
 619         struct scc_ports *ports;
 620         int rc;
 621
 622         rc = pci_enable_device(dev);
 623         if (rc)
 624                 goto end;
 625
 626         rc = setup_mmio_scc(dev, d->name);
 627         if (rc < 0)
 628                 goto end;
 629
 630         ports = pci_get_drvdata(dev);
 631         ctl_base = ports->ctl;
 632         dma_base = ports->dma;
 633         cckctrl_port = ctl_base + 0xff0;
 634         intmask_port = dma_base + 0x010;
 635         mode_port = ctl_base + 0x024;
 636         ecmode_port = ctl_base + 0xf00;
 637
 638         /* controller initialization */
 639         reg = 0;
 640         out_be32((void*)cckctrl_port, reg);
 641         reg |= CCKCTRL_ATACLKOEN;
 642         out_be32((void*)cckctrl_port, reg);
 643         reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
 644         out_be32((void*)cckctrl_port, reg);
 645         reg |= CCKCTRL_CRST;
 646         out_be32((void*)cckctrl_port, reg);
 647
 648         for (;;) {
 649                 reg = in_be32((void*)cckctrl_port);
 650                 if (reg & CCKCTRL_CRST)
 651                         break;
 652                 udelay(5000);
 653         }
 654
 655         reg |= CCKCTRL_ATARESET;
 656         out_be32((void*)cckctrl_port, reg);
 657
 658         out_be32((void*)ecmode_port, ECMODE_VALUE);
 659         out_be32((void*)mode_port, MODE_JCUSFEN);
 660         out_be32((void*)intmask_port, INTMASK_MSK);
 661
 662         rc = scc_ide_setup_pci_device(dev, d);
 663
 664  end:
 665         return rc;
 666 }
 667
 668 static void scc_tf_load(ide_drive_t *drive, ide_task_t *task)
 669 {
 670         struct ide_io_ports *io_ports = &drive->hwif->io_ports;
 671         struct ide_taskfile *tf = &task->tf;
 672         u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
 673
 674         if (task->tf_flags & IDE_TFLAG_FLAGGED)
 675                 HIHI = 0xFF;
 676
 677         if (task->tf_flags & IDE_TFLAG_OUT_DATA)
 678                 out_be32((void *)io_ports->data_addr,
 679                          (tf->hob_data << 8) | tf->data);
 680
 681         if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
 682                 scc_ide_outb(tf->hob_feature, io_ports->feature_addr);
 683         if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
 684                 scc_ide_outb(tf->hob_nsect, io_ports->nsect_addr);
 685         if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
 686                 scc_ide_outb(tf->hob_lbal, io_ports->lbal_addr);
 687         if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
 688                 scc_ide_outb(tf->hob_lbam, io_ports->lbam_addr);
 689         if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
 690                 scc_ide_outb(tf->hob_lbah, io_ports->lbah_addr);
 691
 692         if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
 693                 scc_ide_outb(tf->feature, io_ports->feature_addr);
 694         if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
 695                 scc_ide_outb(tf->nsect, io_ports->nsect_addr);
 696         if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
 697                 scc_ide_outb(tf->lbal, io_ports->lbal_addr);
 698         if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
 699                 scc_ide_outb(tf->lbam, io_ports->lbam_addr);
 700         if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
 701                 scc_ide_outb(tf->lbah, io_ports->lbah_addr);
 702
 703         if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
 704                 scc_ide_outb((tf->device & HIHI) | drive->select,
 705                              io_ports->device_addr);
 706 }
 707
 708 static void scc_tf_read(ide_drive_t *drive, ide_task_t *task)
 709 {
 710         struct ide_io_ports *io_ports = &drive->hwif->io_ports;
 711         struct ide_taskfile *tf = &task->tf;
 712
 713         if (task->tf_flags & IDE_TFLAG_IN_DATA) {
 714                 u16 data = (u16)in_be32((void *)io_ports->data_addr);
 715
 716                 tf->data = data & 0xff;
 717                 tf->hob_data = (data >> 8) & 0xff;
 718         }
 719
 720         /* be sure we're looking at the low order bits */
 721         scc_ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
 722
 723         if (task->tf_flags & IDE_TFLAG_IN_FEATURE)
 724                 tf->feature = scc_ide_inb(io_ports->feature_addr);
 725         if (task->tf_flags & IDE_TFLAG_IN_NSECT)
 726                 tf->nsect  = scc_ide_inb(io_ports->nsect_addr);
 727         if (task->tf_flags & IDE_TFLAG_IN_LBAL)
 728                 tf->lbal   = scc_ide_inb(io_ports->lbal_addr);
 729         if (task->tf_flags & IDE_TFLAG_IN_LBAM)
 730                 tf->lbam   = scc_ide_inb(io_ports->lbam_addr);
 731         if (task->tf_flags & IDE_TFLAG_IN_LBAH)
 732                 tf->lbah   = scc_ide_inb(io_ports->lbah_addr);
 733         if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
 734                 tf->device = scc_ide_inb(io_ports->device_addr);
 735
 736         if (task->tf_flags & IDE_TFLAG_LBA48) {
 737                 scc_ide_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
 738
 739                 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
 740                         tf->hob_feature = scc_ide_inb(io_ports->feature_addr);
 741                 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
 742                         tf->hob_nsect   = scc_ide_inb(io_ports->nsect_addr);
 743                 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
 744                         tf->hob_lbal    = scc_ide_inb(io_ports->lbal_addr);
 745                 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
 746                         tf->hob_lbam    = scc_ide_inb(io_ports->lbam_addr);
 747                 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
 748                         tf->hob_lbah    = scc_ide_inb(io_ports->lbah_addr);
 749         }
 750 }
 751
 752 static void scc_input_data(ide_drive_t *drive, struct request *rq,
 753                            void *buf, unsigned int len)
 754 {
 755         unsigned long data_addr = drive->hwif->io_ports.data_addr;
 756
 757         len++;
 758
 759         if (drive->io_32bit) {
 760                 scc_ide_insl(data_addr, buf, len / 4);
 761
 762                 if ((len & 3) >= 2)
 763                         scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1);
 764         } else
 765                 scc_ide_insw(data_addr, buf, len / 2);
 766 }
 767
 768 static void scc_output_data(ide_drive_t *drive,  struct request *rq,
 769                             void *buf, unsigned int len)
 770 {
 771         unsigned long data_addr = drive->hwif->io_ports.data_addr;
 772
 773         len++;
 774
 775         if (drive->io_32bit) {
 776                 scc_ide_outsl(data_addr, buf, len / 4);
 777
 778                 if ((len & 3) >= 2)
 779                         scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1);
 780         } else
 781                 scc_ide_outsw(data_addr, buf, len / 2);
 782 }
 783
 784 /**
 785  *      init_mmio_iops_scc      -       set up the iops for MMIO
 786  *      @hwif: interface to set up
 787  *
 788  */
 789
 790 static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
 791 {
 792         struct pci_dev *dev = to_pci_dev(hwif->dev);
 793         struct scc_ports *ports = pci_get_drvdata(dev);
 794         unsigned long dma_base = ports->dma;
 795
 796         ide_set_hwifdata(hwif, ports);
 797
 798         hwif->dma_base = dma_base;
 799         hwif->config_data = ports->ctl;
 800 }
 801
 802 /**
 803  *      init_iops_scc   -       set up iops
 804  *      @hwif: interface to set up
 805  *
 806  *      Do the basic setup for the SCC hardware interface
 807  *      and then do the MMIO setup.
 808  */
 809
 810 static void __devinit init_iops_scc(ide_hwif_t *hwif)
 811 {
 812         struct pci_dev *dev = to_pci_dev(hwif->dev);
 813
 814         hwif->hwif_data = NULL;
 815         if (pci_get_drvdata(dev) == NULL)
 816                 return;
 817         init_mmio_iops_scc(hwif);
 818 }
 819
 820 static int __devinit scc_init_dma(ide_hwif_t *hwif,
 821                                   const struct ide_port_info *d)
 822 {
 823         return ide_allocate_dma_engine(hwif);
 824 }
 825
 826 static u8 scc_cable_detect(ide_hwif_t *hwif)
 827 {
 828         return ATA_CBL_PATA80;
 829 }
 830
 831 /**
 832  *      init_hwif_scc   -       set up hwif
 833  *      @hwif: interface to set up
 834  *
 835  *      We do the basic set up of the interface structure. The SCC
 836  *      requires several custom handlers so we override the default
 837  *      ide DMA handlers appropriately.
 838  */
 839
 840 static void __devinit init_hwif_scc(ide_hwif_t *hwif)
 841 {
 842         /* PTERADD */
 843         out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
 844
 845         if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
 846                 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
 847         else
 848                 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
 849 }
 850
 851 static const struct ide_tp_ops scc_tp_ops = {
 852         .exec_command           = scc_exec_command,
 853         .read_status            = scc_read_status,
 854         .read_altstatus         = scc_read_altstatus,
 855         .read_sff_dma_status    = scc_read_sff_dma_status,
 856
 857         .set_irq                = scc_set_irq,
 858
 859         .tf_load                = scc_tf_load,
 860         .tf_read                = scc_tf_read,
 861
 862         .input_data             = scc_input_data,
 863         .output_data            = scc_output_data,
 864 };
 865
 866 static const struct ide_port_ops scc_port_ops = {
 867         .set_pio_mode           = scc_set_pio_mode,
 868         .set_dma_mode           = scc_set_dma_mode,
 869         .udma_filter            = scc_udma_filter,
 870         .cable_detect           = scc_cable_detect,
 871 };
 872
 873 static const struct ide_dma_ops scc_dma_ops = {
 874         .dma_host_set           = scc_dma_host_set,
 875         .dma_setup              = scc_dma_setup,
 876         .dma_exec_cmd           = ide_dma_exec_cmd,
 877         .dma_start              = scc_dma_start,
 878         .dma_end                = scc_dma_end,
 879         .dma_test_irq           = scc_dma_test_irq,
 880         .dma_lost_irq           = ide_dma_lost_irq,
 881         .dma_timeout            = ide_dma_timeout,
 882 };
 883
 884 #define DECLARE_SCC_DEV(name_str)                       \
 885   {                                                     \
 886       .name             = name_str,                     \
 887       .init_iops        = init_iops_scc,                \
 888       .init_dma         = scc_init_dma,                 \
 889       .init_hwif        = init_hwif_scc,                \
 890       .tp_ops           = &scc_tp_ops,          \
 891       .port_ops         = &scc_port_ops,                \
 892       .dma_ops          = &scc_dma_ops,                 \
 893       .host_flags       = IDE_HFLAG_SINGLE,             \
 894       .pio_mask         = ATA_PIO4,                     \
 895   }
 896
 897 static const struct ide_port_info scc_chipsets[] __devinitdata = {
 898         /* 0 */ DECLARE_SCC_DEV("sccIDE"),
 899 };
 900
 901 /**
 902  *      scc_init_one    -       pci layer discovery entry
 903  *      @dev: PCI device
 904  *      @id: ident table entry
 905  *
 906  *      Called by the PCI code when it finds an SCC PATA controller.
 907  *      We then use the IDE PCI generic helper to do most of the work.
 908  */
 909
 910 static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 911 {
 912         return init_setup_scc(dev, &scc_chipsets[id->driver_data]);
 913 }
 914
 915 /**
 916  *      scc_remove      -       pci layer remove entry
 917  *      @dev: PCI device
 918  *
 919  *      Called by the PCI code when it removes an SCC PATA controller.
 920  */
 921
 922 static void __devexit scc_remove(struct pci_dev *dev)
 923 {
 924         struct scc_ports *ports = pci_get_drvdata(dev);
 925         struct ide_host *host = ports->host;
 926
 927         ide_host_remove(host);
 928
 929         iounmap((void*)ports->dma);
 930         iounmap((void*)ports->ctl);
 931         pci_release_selected_regions(dev, (1 << 2) - 1);
 932         memset(ports, 0, sizeof(*ports));
 933 }
 934
 935 static const struct pci_device_id scc_pci_tbl[] = {
 936         { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
 937         { 0, },
 938 };
 939 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
 940
 941 static struct pci_driver scc_pci_driver = {
 942         .name = "SCC IDE",
 943         .id_table = scc_pci_tbl,
 944         .probe = scc_init_one,
 945         .remove = __devexit_p(scc_remove),
 946 };
 947
 948 static int scc_ide_init(void)
 949 {
 950         return ide_pci_register_driver(&scc_pci_driver);
 951 }
 952
 953 module_init(scc_ide_init);
 954 /* -- No exit code?
 955 static void scc_ide_exit(void)
 956 {
 957         ide_pci_unregister_driver(&scc_pci_driver);
 958 }
 959 module_exit(scc_ide_exit);
 960  */
 961
 962
 963 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
 964 MODULE_LICENSE("GPL");