drivers/ide/scc_pata.c

   1 /*
   2  * Support for IDE interfaces on Celleb platform
   3  *
   4  * (C) Copyright 2006 TOSHIBA CORPORATION
   5  *
   6  * This code is based on drivers/ide/pci/siimage.c:
   7  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   8  * Copyright (C) 2003           Red Hat
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along
  21  * with this program; if not, write to the Free Software Foundation, Inc.,
  22  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  23  */
  24
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/delay.h>
  29 #include <linux/ide.h>
  30 #include <linux/init.h>
  31
  32 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA            0x01b4
  33
  34 #define SCC_PATA_NAME           "scc IDE"
  35
  36 #define TDVHSEL_MASTER          0x00000001
  37 #define TDVHSEL_SLAVE           0x00000004
  38
  39 #define MODE_JCUSFEN            0x00000080
  40
  41 #define CCKCTRL_ATARESET        0x00040000
  42 #define CCKCTRL_BUFCNT          0x00020000
  43 #define CCKCTRL_CRST            0x00010000
  44 #define CCKCTRL_OCLKEN          0x00000100
  45 #define CCKCTRL_ATACLKOEN       0x00000002
  46 #define CCKCTRL_LCLKEN          0x00000001
  47
  48 #define QCHCD_IOS_SS            0x00000001
  49
  50 #define QCHSD_STPDIAG           0x00020000
  51
  52 #define INTMASK_MSK             0xD1000012
  53 #define INTSTS_SERROR           0x80000000
  54 #define INTSTS_PRERR            0x40000000
  55 #define INTSTS_RERR             0x10000000
  56 #define INTSTS_ICERR            0x01000000
  57 #define INTSTS_BMSINT           0x00000010
  58 #define INTSTS_BMHE             0x00000008
  59 #define INTSTS_IOIRQS           0x00000004
  60 #define INTSTS_INTRQ            0x00000002
  61 #define INTSTS_ACTEINT          0x00000001
  62
  63 #define ECMODE_VALUE 0x01
  64
  65 static struct scc_ports {
  66         unsigned long ctl, dma;
  67         struct ide_host *host;  /* for removing port from system */
  68 } scc_ports[MAX_HWIFS];
  69
  70 /* PIO transfer mode  table */
  71 /* JCHST */
  72 static unsigned long JCHSTtbl[2][7] = {
  73         {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00},   /* 100MHz */
  74         {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00}    /* 133MHz */
  75 };
  76
  77 /* JCHHT */
  78 static unsigned long JCHHTtbl[2][7] = {
  79         {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00},   /* 100MHz */
  80         {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}    /* 133MHz */
  81 };
  82
  83 /* JCHCT */
  84 static unsigned long JCHCTtbl[2][7] = {
  85         {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00},   /* 100MHz */
  86         {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00}    /* 133MHz */
  87 };
  88
  89
  90 /* DMA transfer mode  table */
  91 /* JCHDCTM/JCHDCTS */
  92 static unsigned long JCHDCTxtbl[2][7] = {
  93         {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00},   /* 100MHz */
  94         {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00}    /* 133MHz */
  95 };
  96
  97 /* JCSTWTM/JCSTWTS  */
  98 static unsigned long JCSTWTxtbl[2][7] = {
  99         {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00},   /* 100MHz */
 100         {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 101 };
 102
 103 /* JCTSS */
 104 static unsigned long JCTSStbl[2][7] = {
 105         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00},   /* 100MHz */
 106         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05}    /* 133MHz */
 107 };
 108
 109 /* JCENVT */
 110 static unsigned long JCENVTtbl[2][7] = {
 111         {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},   /* 100MHz */
 112         {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}    /* 133MHz */
 113 };
 114
 115 /* JCACTSELS/JCACTSELM */
 116 static unsigned long JCACTSELtbl[2][7] = {
 117         {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00},   /* 100MHz */
 118         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}    /* 133MHz */
 119 };
 120
 121
 122 static u8 scc_ide_inb(unsigned long port)
 123 {
 124         u32 data = in_be32((void*)port);
 125         return (u8)data;
 126 }
 127
 128 static void scc_exec_command(ide_hwif_t *hwif, u8 cmd)
 129 {
 130         out_be32((void *)hwif->io_ports.command_addr, cmd);
 131         eieio();
 132         in_be32((void *)(hwif->dma_base + 0x01c));
 133         eieio();
 134 }
 135
 136 static u8 scc_read_status(ide_hwif_t *hwif)
 137 {
 138         return (u8)in_be32((void *)hwif->io_ports.status_addr);
 139 }
 140
 141 static u8 scc_read_altstatus(ide_hwif_t *hwif)
 142 {
 143         return (u8)in_be32((void *)hwif->io_ports.ctl_addr);
 144 }
 145
 146 static u8 scc_dma_sff_read_status(ide_hwif_t *hwif)
 147 {
 148         return (u8)in_be32((void *)(hwif->dma_base + 4));
 149 }
 150
 151 static void scc_write_devctl(ide_hwif_t *hwif, u8 ctl)
 152 {
 153         out_be32((void *)hwif->io_ports.ctl_addr, ctl);
 154         eieio();
 155         in_be32((void *)(hwif->dma_base + 0x01c));
 156         eieio();
 157 }
 158
 159 static void scc_ide_insw(unsigned long port, void *addr, u32 count)
 160 {
 161         u16 *ptr = (u16 *)addr;
 162         while (count--) {
 163                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 164         }
 165 }
 166
 167 static void scc_ide_insl(unsigned long port, void *addr, u32 count)
 168 {
 169         u16 *ptr = (u16 *)addr;
 170         while (count--) {
 171                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 172                 *ptr++ = le16_to_cpu(in_be32((void*)port));
 173         }
 174 }
 175
 176 static void scc_ide_outb(u8 addr, unsigned long port)
 177 {
 178         out_be32((void*)port, addr);
 179 }
 180
 181 static void
 182 scc_ide_outsw(unsigned long port, void *addr, u32 count)
 183 {
 184         u16 *ptr = (u16 *)addr;
 185         while (count--) {
 186                 out_be32((void*)port, cpu_to_le16(*ptr++));
 187         }
 188 }
 189
 190 static void
 191 scc_ide_outsl(unsigned long port, void *addr, u32 count)
 192 {
 193         u16 *ptr = (u16 *)addr;
 194         while (count--) {
 195                 out_be32((void*)port, cpu_to_le16(*ptr++));
 196                 out_be32((void*)port, cpu_to_le16(*ptr++));
 197         }
 198 }
 199
 200 /**
 201  *      scc_set_pio_mode        -       set host controller for PIO mode
 202  *      @drive: drive
 203  *      @pio: PIO mode number
 204  *
 205  *      Load the timing settings for this device mode into the
 206  *      controller.
 207  */
 208
 209 static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
 210 {
 211         ide_hwif_t *hwif = drive->hwif;
 212         struct scc_ports *ports = ide_get_hwifdata(hwif);
 213         unsigned long ctl_base = ports->ctl;
 214         unsigned long cckctrl_port = ctl_base + 0xff0;
 215         unsigned long piosht_port = ctl_base + 0x000;
 216         unsigned long pioct_port = ctl_base + 0x004;
 217         unsigned long reg;
 218         int offset;
 219
 220         reg = in_be32((void __iomem *)cckctrl_port);
 221         if (reg & CCKCTRL_ATACLKOEN) {
 222                 offset = 1; /* 133MHz */
 223         } else {
 224                 offset = 0; /* 100MHz */
 225         }
 226         reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
 227         out_be32((void __iomem *)piosht_port, reg);
 228         reg = JCHCTtbl[offset][pio];
 229         out_be32((void __iomem *)pioct_port, reg);
 230 }
 231
 232 /**
 233  *      scc_set_dma_mode        -       set host controller for DMA mode
 234  *      @drive: drive
 235  *      @speed: DMA mode
 236  *
 237  *      Load the timing settings for this device mode into the
 238  *      controller.
 239  */
 240
 241 static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
 242 {
 243         ide_hwif_t *hwif = drive->hwif;
 244         struct scc_ports *ports = ide_get_hwifdata(hwif);
 245         unsigned long ctl_base = ports->ctl;
 246         unsigned long cckctrl_port = ctl_base + 0xff0;
 247         unsigned long mdmact_port = ctl_base + 0x008;
 248         unsigned long mcrcst_port = ctl_base + 0x00c;
 249         unsigned long sdmact_port = ctl_base + 0x010;
 250         unsigned long scrcst_port = ctl_base + 0x014;
 251         unsigned long udenvt_port = ctl_base + 0x018;
 252         unsigned long tdvhsel_port   = ctl_base + 0x020;
 253         int is_slave = drive->dn & 1;
 254         int offset, idx;
 255         unsigned long reg;
 256         unsigned long jcactsel;
 257
 258         reg = in_be32((void __iomem *)cckctrl_port);
 259         if (reg & CCKCTRL_ATACLKOEN) {
 260                 offset = 1; /* 133MHz */
 261         } else {
 262                 offset = 0; /* 100MHz */
 263         }
 264
 265         idx = speed - XFER_UDMA_0;
 266
 267         jcactsel = JCACTSELtbl[offset][idx];
 268         if (is_slave) {
 269                 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
 270                 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
 271                 jcactsel = jcactsel << 2;
 272                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
 273         } else {
 274                 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
 275                 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
 276                 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
 277         }
 278         reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
 279         out_be32((void __iomem *)udenvt_port, reg);
 280 }
 281
 282 static void scc_dma_host_set(ide_drive_t *drive, int on)
 283 {
 284         ide_hwif_t *hwif = drive->hwif;
 285         u8 unit = drive->dn & 1;
 286         u8 dma_stat = scc_dma_sff_read_status(hwif);
 287
 288         if (on)
 289                 dma_stat |= (1 << (5 + unit));
 290         else
 291                 dma_stat &= ~(1 << (5 + unit));
 292
 293         scc_ide_outb(dma_stat, hwif->dma_base + 4);
 294 }
 295
 296 /**
 297  *      scc_dma_setup   -       begin a DMA phase
 298  *      @drive: target device
 299  *      @cmd: command
 300  *
 301  *      Build an IDE DMA PRD (IDE speak for scatter gather table)
 302  *      and then set up the DMA transfer registers.
 303  *
 304  *      Returns 0 on success. If a PIO fallback is required then 1
 305  *      is returned.
 306  */
 307
 308 static int scc_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
 309 {
 310         ide_hwif_t *hwif = drive->hwif;
 311         u32 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
 312         u8 dma_stat;
 313
 314         /* fall back to pio! */
 315         if (ide_build_dmatable(drive, cmd) == 0)
 316                 return 1;
 317
 318         /* PRD table */
 319         out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);
 320
 321         /* specify r/w */
 322         out_be32((void __iomem *)hwif->dma_base, rw);
 323
 324         /* read DMA status for INTR & ERROR flags */
 325         dma_stat = scc_dma_sff_read_status(hwif);
 326
 327         /* clear INTR & ERROR flags */
 328         out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6);
 329
 330         return 0;
 331 }
 332
 333 static void scc_dma_start(ide_drive_t *drive)
 334 {
 335         ide_hwif_t *hwif = drive->hwif;
 336         u8 dma_cmd = scc_ide_inb(hwif->dma_base);
 337
 338         /* start DMA */
 339         scc_ide_outb(dma_cmd | 1, hwif->dma_base);
 340         wmb();
 341 }
 342
 343 static int __scc_dma_end(ide_drive_t *drive)
 344 {
 345         ide_hwif_t *hwif = drive->hwif;
 346         u8 dma_stat, dma_cmd;
 347
 348         /* get DMA command mode */
 349         dma_cmd = scc_ide_inb(hwif->dma_base);
 350         /* stop DMA */
 351         scc_ide_outb(dma_cmd & ~1, hwif->dma_base);
 352         /* get DMA status */
 353         dma_stat = scc_dma_sff_read_status(hwif);
 354         /* clear the INTR & ERROR bits */
 355         scc_ide_outb(dma_stat | 6, hwif->dma_base + 4);
 356         /* verify good DMA status */
 357         wmb();
 358         return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
 359 }
 360
 361 /**
 362  *      scc_dma_end     -       Stop DMA
 363  *      @drive: IDE drive
 364  *
 365  *      Check and clear INT Status register.
 366  *      Then call __scc_dma_end().
 367  */
 368
 369 static int scc_dma_end(ide_drive_t *drive)
 370 {
 371         ide_hwif_t *hwif = drive->hwif;
 372         void __iomem *dma_base = (void __iomem *)hwif->dma_base;
 373         unsigned long intsts_port = hwif->dma_base + 0x014;
 374         u32 reg;
 375         int dma_stat, data_loss = 0;
 376         static int retry = 0;
 377
 378         /* errata A308 workaround: Step5 (check data loss) */
 379         /* We don't check non ide_disk because it is limited to UDMA4 */
 380         if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)
 381               & ATA_ERR) &&
 382             drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
 383                 reg = in_be32((void __iomem *)intsts_port);
 384                 if (!(reg & INTSTS_ACTEINT)) {
 385                         printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
 386                                drive->name);
 387                         data_loss = 1;
 388                         if (retry++) {
 389                                 struct request *rq = hwif->rq;
 390                                 ide_drive_t *drive;
 391                                 int i;
 392
 393                                 /* ERROR_RESET and drive->crc_count are needed
 394                                  * to reduce DMA transfer mode in retry process.
 395                                  */
 396                                 if (rq)
 397                                         rq->errors |= ERROR_RESET;
 398
 399                                 ide_port_for_each_dev(i, drive, hwif)
 400                                         drive->crc_count++;
 401                         }
 402                 }
 403         }
 404
 405         while (1) {
 406                 reg = in_be32((void __iomem *)intsts_port);
 407
 408                 if (reg & INTSTS_SERROR) {
 409                         printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
 410                         out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
 411
 412                         out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
 413                         continue;
 414                 }
 415
 416                 if (reg & INTSTS_PRERR) {
 417                         u32 maea0, maec0;
 418                         unsigned long ctl_base = hwif->config_data;
 419
 420                         maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
 421                         maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
 422
 423                         printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
 424
 425                         out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
 426
 427                         out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
 428                         continue;
 429                 }
 430
 431                 if (reg & INTSTS_RERR) {
 432                         printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
 433                         out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
 434
 435                         out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
 436                         continue;
 437                 }
 438
 439                 if (reg & INTSTS_ICERR) {
 440                         out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
 441
 442                         printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
 443                         out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
 444                         continue;
 445                 }
 446
 447                 if (reg & INTSTS_BMSINT) {
 448                         printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
 449                         out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
 450
 451                         ide_do_reset(drive);
 452                         continue;
 453                 }
 454
 455                 if (reg & INTSTS_BMHE) {
 456                         out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
 457                         continue;
 458                 }
 459
 460                 if (reg & INTSTS_ACTEINT) {
 461                         out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
 462                         continue;
 463                 }
 464
 465                 if (reg & INTSTS_IOIRQS) {
 466                         out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
 467                         continue;
 468                 }
 469                 break;
 470         }
 471
 472         dma_stat = __scc_dma_end(drive);
 473         if (data_loss)
 474                 dma_stat |= 2; /* emulate DMA error (to retry command) */
 475         return dma_stat;
 476 }
 477
 478 /* returns 1 if dma irq issued, 0 otherwise */
 479 static int scc_dma_test_irq(ide_drive_t *drive)
 480 {
 481         ide_hwif_t *hwif = drive->hwif;
 482         u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
 483
 484         /* SCC errata A252,A308 workaround: Step4 */
 485         if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)
 486              & ATA_ERR) &&
 487             (int_stat & INTSTS_INTRQ))
 488                 return 1;
 489
 490         /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
 491         if (int_stat & INTSTS_IOIRQS)
 492                 return 1;
 493
 494         return 0;
 495 }
 496
 497 static u8 scc_udma_filter(ide_drive_t *drive)
 498 {
 499         ide_hwif_t *hwif = drive->hwif;
 500         u8 mask = hwif->ultra_mask;
 501
 502         /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
 503         if ((drive->media != ide_disk) && (mask & 0xE0)) {
 504                 printk(KERN_INFO "%s: limit %s to UDMA4\n",
 505                        SCC_PATA_NAME, drive->name);
 506                 mask = ATA_UDMA4;
 507         }
 508
 509         return mask;
 510 }
 511
 512 /**
 513  *      setup_mmio_scc  -       map CTRL/BMID region
 514  *      @dev: PCI device we are configuring
 515  *      @name: device name
 516  *
 517  */
 518
 519 static int setup_mmio_scc (struct pci_dev *dev, const char *name)
 520 {
 521         void __iomem *ctl_addr;
 522         void __iomem *dma_addr;
 523         int i, ret;
 524
 525         for (i = 0; i < MAX_HWIFS; i++) {
 526                 if (scc_ports[i].ctl == 0)
 527                         break;
 528         }
 529         if (i >= MAX_HWIFS)
 530                 return -ENOMEM;
 531
 532         ret = pci_request_selected_regions(dev, (1 << 2) - 1, name);
 533         if (ret < 0) {
 534                 printk(KERN_ERR "%s: can't reserve resources\n", name);
 535                 return ret;
 536         }
 537
 538         ctl_addr = pci_ioremap_bar(dev, 0);
 539         if (!ctl_addr)
 540                 goto fail_0;
 541
 542         dma_addr = pci_ioremap_bar(dev, 1);
 543         if (!dma_addr)
 544                 goto fail_1;
 545
 546         pci_set_master(dev);
 547         scc_ports[i].ctl = (unsigned long)ctl_addr;
 548         scc_ports[i].dma = (unsigned long)dma_addr;
 549         pci_set_drvdata(dev, (void *) &scc_ports[i]);
 550
 551         return 1;
 552
 553  fail_1:
 554         iounmap(ctl_addr);
 555  fail_0:
 556         return -ENOMEM;
 557 }
 558
 559 static int scc_ide_setup_pci_device(struct pci_dev *dev,
 560                                     const struct ide_port_info *d)
 561 {
 562         struct scc_ports *ports = pci_get_drvdata(dev);
 563         struct ide_host *host;
 564         hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
 565         int i, rc;
 566
 567         memset(&hw, 0, sizeof(hw));
 568         for (i = 0; i <= 8; i++)
 569                 hw.io_ports_array[i] = ports->dma + 0x20 + i * 4;
 570         hw.irq = dev->irq;
 571         hw.dev = &dev->dev;
 572         hw.chipset = ide_pci;
 573
 574         rc = ide_host_add(d, hws, &host);
 575         if (rc)
 576                 return rc;
 577
 578         ports->host = host;
 579
 580         return 0;
 581 }
 582
 583 /**
 584  *      init_setup_scc  -       set up an SCC PATA Controller
 585  *      @dev: PCI device
 586  *      @d: IDE port info
 587  *
 588  *      Perform the initial set up for this device.
 589  */
 590
 591 static int __devinit init_setup_scc(struct pci_dev *dev,
 592                                     const struct ide_port_info *d)
 593 {
 594         unsigned long ctl_base;
 595         unsigned long dma_base;
 596         unsigned long cckctrl_port;
 597         unsigned long intmask_port;
 598         unsigned long mode_port;
 599         unsigned long ecmode_port;
 600         u32 reg = 0;
 601         struct scc_ports *ports;
 602         int rc;
 603
 604         rc = pci_enable_device(dev);
 605         if (rc)
 606                 goto end;
 607
 608         rc = setup_mmio_scc(dev, d->name);
 609         if (rc < 0)
 610                 goto end;
 611
 612         ports = pci_get_drvdata(dev);
 613         ctl_base = ports->ctl;
 614         dma_base = ports->dma;
 615         cckctrl_port = ctl_base + 0xff0;
 616         intmask_port = dma_base + 0x010;
 617         mode_port = ctl_base + 0x024;
 618         ecmode_port = ctl_base + 0xf00;
 619
 620         /* controller initialization */
 621         reg = 0;
 622         out_be32((void*)cckctrl_port, reg);
 623         reg |= CCKCTRL_ATACLKOEN;
 624         out_be32((void*)cckctrl_port, reg);
 625         reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
 626         out_be32((void*)cckctrl_port, reg);
 627         reg |= CCKCTRL_CRST;
 628         out_be32((void*)cckctrl_port, reg);
 629
 630         for (;;) {
 631                 reg = in_be32((void*)cckctrl_port);
 632                 if (reg & CCKCTRL_CRST)
 633                         break;
 634                 udelay(5000);
 635         }
 636
 637         reg |= CCKCTRL_ATARESET;
 638         out_be32((void*)cckctrl_port, reg);
 639
 640         out_be32((void*)ecmode_port, ECMODE_VALUE);
 641         out_be32((void*)mode_port, MODE_JCUSFEN);
 642         out_be32((void*)intmask_port, INTMASK_MSK);
 643
 644         rc = scc_ide_setup_pci_device(dev, d);
 645
 646  end:
 647         return rc;
 648 }
 649
 650 static void scc_tf_load(ide_drive_t *drive, struct ide_cmd *cmd)
 651 {
 652         struct ide_io_ports *io_ports = &drive->hwif->io_ports;
 653         struct ide_taskfile *tf = &cmd->tf;
 654         u8 HIHI = (cmd->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
 655
 656         if (cmd->ftf_flags & IDE_FTFLAG_FLAGGED)
 657                 HIHI = 0xFF;
 658
 659         if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
 660                 scc_ide_outb(tf->hob_feature, io_ports->feature_addr);
 661         if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
 662                 scc_ide_outb(tf->hob_nsect, io_ports->nsect_addr);
 663         if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
 664                 scc_ide_outb(tf->hob_lbal, io_ports->lbal_addr);
 665         if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
 666                 scc_ide_outb(tf->hob_lbam, io_ports->lbam_addr);
 667         if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
 668                 scc_ide_outb(tf->hob_lbah, io_ports->lbah_addr);
 669
 670         if (cmd->tf_flags & IDE_TFLAG_OUT_FEATURE)
 671                 scc_ide_outb(tf->feature, io_ports->feature_addr);
 672         if (cmd->tf_flags & IDE_TFLAG_OUT_NSECT)
 673                 scc_ide_outb(tf->nsect, io_ports->nsect_addr);
 674         if (cmd->tf_flags & IDE_TFLAG_OUT_LBAL)
 675                 scc_ide_outb(tf->lbal, io_ports->lbal_addr);
 676         if (cmd->tf_flags & IDE_TFLAG_OUT_LBAM)
 677                 scc_ide_outb(tf->lbam, io_ports->lbam_addr);
 678         if (cmd->tf_flags & IDE_TFLAG_OUT_LBAH)
 679                 scc_ide_outb(tf->lbah, io_ports->lbah_addr);
 680
 681         if (cmd->tf_flags & IDE_TFLAG_OUT_DEVICE)
 682                 scc_ide_outb((tf->device & HIHI) | drive->select,
 683                              io_ports->device_addr);
 684 }
 685
 686 static void scc_tf_read(ide_drive_t *drive, struct ide_cmd *cmd)
 687 {
 688         struct ide_io_ports *io_ports = &drive->hwif->io_ports;
 689         struct ide_taskfile *tf = &cmd->tf;
 690
 691         /* be sure we're looking at the low order bits */
 692         scc_ide_outb(ATA_DEVCTL_OBS, io_ports->ctl_addr);
 693
 694         if (cmd->tf_flags & IDE_TFLAG_IN_ERROR)
 695                 tf->error  = scc_ide_inb(io_ports->feature_addr);
 696         if (cmd->tf_flags & IDE_TFLAG_IN_NSECT)
 697                 tf->nsect  = scc_ide_inb(io_ports->nsect_addr);
 698         if (cmd->tf_flags & IDE_TFLAG_IN_LBAL)
 699                 tf->lbal   = scc_ide_inb(io_ports->lbal_addr);
 700         if (cmd->tf_flags & IDE_TFLAG_IN_LBAM)
 701                 tf->lbam   = scc_ide_inb(io_ports->lbam_addr);
 702         if (cmd->tf_flags & IDE_TFLAG_IN_LBAH)
 703                 tf->lbah   = scc_ide_inb(io_ports->lbah_addr);
 704         if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE)
 705                 tf->device = scc_ide_inb(io_ports->device_addr);
 706
 707         if (cmd->tf_flags & IDE_TFLAG_LBA48) {
 708                 scc_ide_outb(ATA_HOB | ATA_DEVCTL_OBS, io_ports->ctl_addr);
 709
 710                 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_ERROR)
 711                         tf->hob_error = scc_ide_inb(io_ports->feature_addr);
 712                 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
 713                         tf->hob_nsect = scc_ide_inb(io_ports->nsect_addr);
 714                 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
 715                         tf->hob_lbal  = scc_ide_inb(io_ports->lbal_addr);
 716                 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
 717                         tf->hob_lbam  = scc_ide_inb(io_ports->lbam_addr);
 718                 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
 719                         tf->hob_lbah  = scc_ide_inb(io_ports->lbah_addr);
 720         }
 721 }
 722
 723 static void scc_input_data(ide_drive_t *drive, struct ide_cmd *cmd,
 724                            void *buf, unsigned int len)
 725 {
 726         unsigned long data_addr = drive->hwif->io_ports.data_addr;
 727
 728         len++;
 729
 730         if (drive->io_32bit) {
 731                 scc_ide_insl(data_addr, buf, len / 4);
 732
 733                 if ((len & 3) >= 2)
 734                         scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1);
 735         } else
 736                 scc_ide_insw(data_addr, buf, len / 2);
 737 }
 738
 739 static void scc_output_data(ide_drive_t *drive,  struct ide_cmd *cmd,
 740                             void *buf, unsigned int len)
 741 {
 742         unsigned long data_addr = drive->hwif->io_ports.data_addr;
 743
 744         len++;
 745
 746         if (drive->io_32bit) {
 747                 scc_ide_outsl(data_addr, buf, len / 4);
 748
 749                 if ((len & 3) >= 2)
 750                         scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1);
 751         } else
 752                 scc_ide_outsw(data_addr, buf, len / 2);
 753 }
 754
 755 /**
 756  *      init_mmio_iops_scc      -       set up the iops for MMIO
 757  *      @hwif: interface to set up
 758  *
 759  */
 760
 761 static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
 762 {
 763         struct pci_dev *dev = to_pci_dev(hwif->dev);
 764         struct scc_ports *ports = pci_get_drvdata(dev);
 765         unsigned long dma_base = ports->dma;
 766
 767         ide_set_hwifdata(hwif, ports);
 768
 769         hwif->dma_base = dma_base;
 770         hwif->config_data = ports->ctl;
 771 }
 772
 773 /**
 774  *      init_iops_scc   -       set up iops
 775  *      @hwif: interface to set up
 776  *
 777  *      Do the basic setup for the SCC hardware interface
 778  *      and then do the MMIO setup.
 779  */
 780
 781 static void __devinit init_iops_scc(ide_hwif_t *hwif)
 782 {
 783         struct pci_dev *dev = to_pci_dev(hwif->dev);
 784
 785         hwif->hwif_data = NULL;
 786         if (pci_get_drvdata(dev) == NULL)
 787                 return;
 788         init_mmio_iops_scc(hwif);
 789 }
 790
 791 static int __devinit scc_init_dma(ide_hwif_t *hwif,
 792                                   const struct ide_port_info *d)
 793 {
 794         return ide_allocate_dma_engine(hwif);
 795 }
 796
 797 static u8 scc_cable_detect(ide_hwif_t *hwif)
 798 {
 799         return ATA_CBL_PATA80;
 800 }
 801
 802 /**
 803  *      init_hwif_scc   -       set up hwif
 804  *      @hwif: interface to set up
 805  *
 806  *      We do the basic set up of the interface structure. The SCC
 807  *      requires several custom handlers so we override the default
 808  *      ide DMA handlers appropriately.
 809  */
 810
 811 static void __devinit init_hwif_scc(ide_hwif_t *hwif)
 812 {
 813         /* PTERADD */
 814         out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
 815
 816         if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
 817                 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
 818         else
 819                 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
 820 }
 821
 822 static const struct ide_tp_ops scc_tp_ops = {
 823         .exec_command           = scc_exec_command,
 824         .read_status            = scc_read_status,
 825         .read_altstatus         = scc_read_altstatus,
 826         .write_devctl           = scc_write_devctl,
 827
 828         .dev_select             = ide_dev_select,
 829         .tf_load                = scc_tf_load,
 830         .tf_read                = scc_tf_read,
 831
 832         .input_data             = scc_input_data,
 833         .output_data            = scc_output_data,
 834 };
 835
 836 static const struct ide_port_ops scc_port_ops = {
 837         .set_pio_mode           = scc_set_pio_mode,
 838         .set_dma_mode           = scc_set_dma_mode,
 839         .udma_filter            = scc_udma_filter,
 840         .cable_detect           = scc_cable_detect,
 841 };
 842
 843 static const struct ide_dma_ops scc_dma_ops = {
 844         .dma_host_set           = scc_dma_host_set,
 845         .dma_setup              = scc_dma_setup,
 846         .dma_start              = scc_dma_start,
 847         .dma_end                = scc_dma_end,
 848         .dma_test_irq           = scc_dma_test_irq,
 849         .dma_lost_irq           = ide_dma_lost_irq,
 850         .dma_timer_expiry       = ide_dma_sff_timer_expiry,
 851         .dma_sff_read_status    = scc_dma_sff_read_status,
 852 };
 853
 854 static const struct ide_port_info scc_chipset __devinitdata = {
 855         .name           = "sccIDE",
 856         .init_iops      = init_iops_scc,
 857         .init_dma       = scc_init_dma,
 858         .init_hwif      = init_hwif_scc,
 859         .tp_ops         = &scc_tp_ops,
 860         .port_ops       = &scc_port_ops,
 861         .dma_ops        = &scc_dma_ops,
 862         .host_flags     = IDE_HFLAG_SINGLE,
 863         .irq_flags      = IRQF_SHARED,
 864         .pio_mask       = ATA_PIO4,
 865 };
 866
 867 /**
 868  *      scc_init_one    -       pci layer discovery entry
 869  *      @dev: PCI device
 870  *      @id: ident table entry
 871  *
 872  *      Called by the PCI code when it finds an SCC PATA controller.
 873  *      We then use the IDE PCI generic helper to do most of the work.
 874  */
 875
 876 static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 877 {
 878         return init_setup_scc(dev, &scc_chipset);
 879 }
 880
 881 /**
 882  *      scc_remove      -       pci layer remove entry
 883  *      @dev: PCI device
 884  *
 885  *      Called by the PCI code when it removes an SCC PATA controller.
 886  */
 887
 888 static void __devexit scc_remove(struct pci_dev *dev)
 889 {
 890         struct scc_ports *ports = pci_get_drvdata(dev);
 891         struct ide_host *host = ports->host;
 892
 893         ide_host_remove(host);
 894
 895         iounmap((void*)ports->dma);
 896         iounmap((void*)ports->ctl);
 897         pci_release_selected_regions(dev, (1 << 2) - 1);
 898         memset(ports, 0, sizeof(*ports));
 899 }
 900
 901 static const struct pci_device_id scc_pci_tbl[] = {
 902         { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
 903         { 0, },
 904 };
 905 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
 906
 907 static struct pci_driver scc_pci_driver = {
 908         .name = "SCC IDE",
 909         .id_table = scc_pci_tbl,
 910         .probe = scc_init_one,
 911         .remove = __devexit_p(scc_remove),
 912 };
 913
 914 static int scc_ide_init(void)
 915 {
 916         return ide_pci_register_driver(&scc_pci_driver);
 917 }
 918
 919 module_init(scc_ide_init);
 920 /* -- No exit code?
 921 static void scc_ide_exit(void)
 922 {
 923         ide_pci_unregister_driver(&scc_pci_driver);
 924 }
 925 module_exit(scc_ide_exit);
 926  */
 927
 928
 929 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
 930 MODULE_LICENSE("GPL");