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ide: remove ide_task_t typedef
[deliverable/linux.git] / drivers / ide / tx4939ide.c
1 /*
2 * TX4939 internal IDE driver
3 * Based on RBTX49xx patch from CELF patch archive.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * (C) Copyright TOSHIBA CORPORATION 2005-2007
10 */
11
12 #include <linux/module.h>
13 #include <linux/types.h>
14 #include <linux/ide.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/scatterlist.h>
20
21 #include <asm/ide.h>
22
23 #define MODNAME "tx4939ide"
24
25 /* ATA Shadow Registers (8-bit except for Data which is 16-bit) */
26 #define TX4939IDE_Data 0x000
27 #define TX4939IDE_Error_Feature 0x001
28 #define TX4939IDE_Sec 0x002
29 #define TX4939IDE_LBA0 0x003
30 #define TX4939IDE_LBA1 0x004
31 #define TX4939IDE_LBA2 0x005
32 #define TX4939IDE_DevHead 0x006
33 #define TX4939IDE_Stat_Cmd 0x007
34 #define TX4939IDE_AltStat_DevCtl 0x402
35 /* H/W DMA Registers */
36 #define TX4939IDE_DMA_Cmd 0x800 /* 8-bit */
37 #define TX4939IDE_DMA_Stat 0x802 /* 8-bit */
38 #define TX4939IDE_PRD_Ptr 0x804 /* 32-bit */
39 /* ATA100 CORE Registers (16-bit) */
40 #define TX4939IDE_Sys_Ctl 0xc00
41 #define TX4939IDE_Xfer_Cnt_1 0xc08
42 #define TX4939IDE_Xfer_Cnt_2 0xc0a
43 #define TX4939IDE_Sec_Cnt 0xc10
44 #define TX4939IDE_Start_Lo_Addr 0xc18
45 #define TX4939IDE_Start_Up_Addr 0xc20
46 #define TX4939IDE_Add_Ctl 0xc28
47 #define TX4939IDE_Lo_Burst_Cnt 0xc30
48 #define TX4939IDE_Up_Burst_Cnt 0xc38
49 #define TX4939IDE_PIO_Addr 0xc88
50 #define TX4939IDE_H_Rst_Tim 0xc90
51 #define TX4939IDE_Int_Ctl 0xc98
52 #define TX4939IDE_Pkt_Cmd 0xcb8
53 #define TX4939IDE_Bxfer_Cnt_Hi 0xcc0
54 #define TX4939IDE_Bxfer_Cnt_Lo 0xcc8
55 #define TX4939IDE_Dev_TErr 0xcd0
56 #define TX4939IDE_Pkt_Xfer_Ctl 0xcd8
57 #define TX4939IDE_Start_TAddr 0xce0
58
59 /* bits for Int_Ctl */
60 #define TX4939IDE_INT_ADDRERR 0x80
61 #define TX4939IDE_INT_REACHMUL 0x40
62 #define TX4939IDE_INT_DEVTIMING 0x20
63 #define TX4939IDE_INT_UDMATERM 0x10
64 #define TX4939IDE_INT_TIMER 0x08
65 #define TX4939IDE_INT_BUSERR 0x04
66 #define TX4939IDE_INT_XFEREND 0x02
67 #define TX4939IDE_INT_HOST 0x01
68
69 #define TX4939IDE_IGNORE_INTS \
70 (TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \
71 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \
72 TX4939IDE_INT_TIMER | TX4939IDE_INT_XFEREND)
73
74 #ifdef __BIG_ENDIAN
75 #define tx4939ide_swizzlel(a) ((a) ^ 4)
76 #define tx4939ide_swizzlew(a) ((a) ^ 6)
77 #define tx4939ide_swizzleb(a) ((a) ^ 7)
78 #else
79 #define tx4939ide_swizzlel(a) (a)
80 #define tx4939ide_swizzlew(a) (a)
81 #define tx4939ide_swizzleb(a) (a)
82 #endif
83
84 static u16 tx4939ide_readw(void __iomem *base, u32 reg)
85 {
86 return __raw_readw(base + tx4939ide_swizzlew(reg));
87 }
88 static u8 tx4939ide_readb(void __iomem *base, u32 reg)
89 {
90 return __raw_readb(base + tx4939ide_swizzleb(reg));
91 }
92 static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg)
93 {
94 __raw_writel(val, base + tx4939ide_swizzlel(reg));
95 }
96 static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg)
97 {
98 __raw_writew(val, base + tx4939ide_swizzlew(reg));
99 }
100 static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg)
101 {
102 __raw_writeb(val, base + tx4939ide_swizzleb(reg));
103 }
104
105 #define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base)
106
107 static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
108 {
109 ide_hwif_t *hwif = drive->hwif;
110 int is_slave = drive->dn;
111 u32 mask, val;
112 u8 safe = pio;
113 ide_drive_t *pair;
114
115 pair = ide_get_pair_dev(drive);
116 if (pair)
117 safe = min(safe, ide_get_best_pio_mode(pair, 255, 4));
118 /*
119 * Update Command Transfer Mode for master/slave and Data
120 * Transfer Mode for this drive.
121 */
122 mask = is_slave ? 0x07f00000 : 0x000007f0;
123 val = ((safe << 8) | (pio << 4)) << (is_slave ? 16 : 0);
124 hwif->select_data = (hwif->select_data & ~mask) | val;
125 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
126 }
127
128 static void tx4939ide_set_dma_mode(ide_drive_t *drive, const u8 mode)
129 {
130 ide_hwif_t *hwif = drive->hwif;
131 u32 mask, val;
132
133 /* Update Data Transfer Mode for this drive. */
134 if (mode >= XFER_UDMA_0)
135 val = mode - XFER_UDMA_0 + 8;
136 else
137 val = mode - XFER_MW_DMA_0 + 5;
138 if (drive->dn) {
139 mask = 0x00f00000;
140 val <<= 20;
141 } else {
142 mask = 0x000000f0;
143 val <<= 4;
144 }
145 hwif->select_data = (hwif->select_data & ~mask) | val;
146 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
147 }
148
149 static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif)
150 {
151 void __iomem *base = TX4939IDE_BASE(hwif);
152 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
153
154 if (ctl & TX4939IDE_INT_BUSERR) {
155 /* reset FIFO */
156 u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl);
157
158 tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl);
159 mmiowb();
160 /* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */
161 ndelay(270);
162 tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
163 }
164 if (ctl & (TX4939IDE_INT_ADDRERR |
165 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR))
166 pr_err("%s: Error interrupt %#x (%s%s%s )\n",
167 hwif->name, ctl,
168 ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "",
169 ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "",
170 ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : "");
171 return ctl;
172 }
173
174 static void tx4939ide_clear_irq(ide_drive_t *drive)
175 {
176 ide_hwif_t *hwif;
177 void __iomem *base;
178 u16 ctl;
179
180 /*
181 * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all job
182 * for DMA case.
183 */
184 if (drive->waiting_for_dma)
185 return;
186 hwif = drive->hwif;
187 base = TX4939IDE_BASE(hwif);
188 ctl = tx4939ide_check_error_ints(hwif);
189 tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
190 }
191
192 static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
193 {
194 void __iomem *base = TX4939IDE_BASE(hwif);
195
196 return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ?
197 ATA_CBL_PATA40 : ATA_CBL_PATA80;
198 }
199
200 #ifdef __BIG_ENDIAN
201 static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
202 {
203 ide_hwif_t *hwif = drive->hwif;
204 u8 unit = drive->dn;
205 void __iomem *base = TX4939IDE_BASE(hwif);
206 u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
207
208 if (on)
209 dma_stat |= (1 << (5 + unit));
210 else
211 dma_stat &= ~(1 << (5 + unit));
212
213 tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat);
214 }
215 #else
216 #define tx4939ide_dma_host_set ide_dma_host_set
217 #endif
218
219 static u8 tx4939ide_clear_dma_status(void __iomem *base)
220 {
221 u8 dma_stat;
222
223 /* read DMA status for INTR & ERROR flags */
224 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
225 /* clear INTR & ERROR flags */
226 tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base,
227 TX4939IDE_DMA_Stat);
228 /* recover intmask cleared by writing to bit2 of DMA_Stat */
229 tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl);
230 return dma_stat;
231 }
232
233 #ifdef __BIG_ENDIAN
234 /* custom ide_build_dmatable to handle swapped layout */
235 static int tx4939ide_build_dmatable(ide_drive_t *drive, struct request *rq)
236 {
237 ide_hwif_t *hwif = drive->hwif;
238 u32 *table = (u32 *)hwif->dmatable_cpu;
239 unsigned int count = 0;
240 int i;
241 struct scatterlist *sg;
242
243 for_each_sg(hwif->sg_table, sg, hwif->sg_nents, i) {
244 u32 cur_addr, cur_len, bcount;
245
246 cur_addr = sg_dma_address(sg);
247 cur_len = sg_dma_len(sg);
248
249 /*
250 * Fill in the DMA table, without crossing any 64kB boundaries.
251 */
252
253 while (cur_len) {
254 if (count++ >= PRD_ENTRIES)
255 goto use_pio_instead;
256
257 bcount = 0x10000 - (cur_addr & 0xffff);
258 if (bcount > cur_len)
259 bcount = cur_len;
260 /*
261 * This workaround for zero count seems required.
262 * (standard ide_build_dmatable does it too)
263 */
264 if (bcount == 0x10000)
265 bcount = 0x8000;
266 *table++ = bcount & 0xffff;
267 *table++ = cur_addr;
268 cur_addr += bcount;
269 cur_len -= bcount;
270 }
271 }
272
273 if (count) {
274 *(table - 2) |= 0x80000000;
275 return count;
276 }
277
278 use_pio_instead:
279 printk(KERN_ERR "%s: %s\n", drive->name,
280 count ? "DMA table too small" : "empty DMA table?");
281
282 ide_destroy_dmatable(drive);
283
284 return 0; /* revert to PIO for this request */
285 }
286 #else
287 #define tx4939ide_build_dmatable ide_build_dmatable
288 #endif
289
290 static int tx4939ide_dma_setup(ide_drive_t *drive)
291 {
292 ide_hwif_t *hwif = drive->hwif;
293 void __iomem *base = TX4939IDE_BASE(hwif);
294 struct request *rq = hwif->rq;
295 u8 reading;
296 int nent;
297
298 if (rq_data_dir(rq))
299 reading = 0;
300 else
301 reading = ATA_DMA_WR;
302
303 /* fall back to PIO! */
304 nent = tx4939ide_build_dmatable(drive, rq);
305 if (!nent) {
306 ide_map_sg(drive, rq);
307 return 1;
308 }
309
310 /* PRD table */
311 tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr);
312
313 /* specify r/w */
314 tx4939ide_writeb(reading, base, TX4939IDE_DMA_Cmd);
315
316 /* clear INTR & ERROR flags */
317 tx4939ide_clear_dma_status(base);
318
319 drive->waiting_for_dma = 1;
320
321 tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ?
322 TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1);
323 tx4939ide_writew(rq->nr_sectors, base, TX4939IDE_Sec_Cnt);
324 return 0;
325 }
326
327 static int tx4939ide_dma_end(ide_drive_t *drive)
328 {
329 ide_hwif_t *hwif = drive->hwif;
330 u8 dma_stat, dma_cmd;
331 void __iomem *base = TX4939IDE_BASE(hwif);
332 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
333
334 drive->waiting_for_dma = 0;
335
336 /* get DMA command mode */
337 dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd);
338 /* stop DMA */
339 tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd);
340
341 /* read and clear the INTR & ERROR bits */
342 dma_stat = tx4939ide_clear_dma_status(base);
343
344 /* purge DMA mappings */
345 ide_destroy_dmatable(drive);
346 /* verify good DMA status */
347 wmb();
348
349 if ((dma_stat & (ATA_DMA_INTR | ATA_DMA_ERR | ATA_DMA_ACTIVE)) == 0 &&
350 (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
351 (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST))
352 /* INT_IDE lost... bug? */
353 return 0;
354 return ((dma_stat & (ATA_DMA_INTR | ATA_DMA_ERR | ATA_DMA_ACTIVE)) !=
355 ATA_DMA_INTR) ? 0x10 | dma_stat : 0;
356 }
357
358 /* returns 1 if DMA IRQ issued, 0 otherwise */
359 static int tx4939ide_dma_test_irq(ide_drive_t *drive)
360 {
361 ide_hwif_t *hwif = drive->hwif;
362 void __iomem *base = TX4939IDE_BASE(hwif);
363 u16 ctl, ide_int;
364 u8 dma_stat, stat;
365 int found = 0;
366
367 ctl = tx4939ide_check_error_ints(hwif);
368 ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST);
369 switch (ide_int) {
370 case TX4939IDE_INT_HOST:
371 /* On error, XFEREND might not be asserted. */
372 stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl);
373 if ((stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) == ATA_ERR)
374 found = 1;
375 else
376 /* Wait for XFEREND (Mask HOST and unmask XFEREND) */
377 ctl &= ~TX4939IDE_INT_XFEREND << 8;
378 ctl |= ide_int << 8;
379 break;
380 case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
381 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
382 if (!(dma_stat & ATA_DMA_INTR))
383 pr_warning("%s: weird interrupt status. "
384 "DMA_Stat %#02x int_ctl %#04x\n",
385 hwif->name, dma_stat, ctl);
386 found = 1;
387 break;
388 }
389 /*
390 * Do not clear XFEREND, HOST now. They will be cleared by
391 * clearing bit2 of DMA_Stat.
392 */
393 ctl &= ~ide_int;
394 tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
395 return found;
396 }
397
398 #ifdef __BIG_ENDIAN
399 static u8 tx4939ide_dma_sff_read_status(ide_hwif_t *hwif)
400 {
401 void __iomem *base = TX4939IDE_BASE(hwif);
402
403 return tx4939ide_readb(base, TX4939IDE_DMA_Stat);
404 }
405 #else
406 #define tx4939ide_dma_sff_read_status ide_dma_sff_read_status
407 #endif
408
409 static void tx4939ide_init_hwif(ide_hwif_t *hwif)
410 {
411 void __iomem *base = TX4939IDE_BASE(hwif);
412
413 /* Soft Reset */
414 tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl);
415 mmiowb();
416 /* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */
417 ndelay(450);
418 tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl);
419 /* mask some interrupts and clear all interrupts */
420 tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base,
421 TX4939IDE_Int_Ctl);
422
423 tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt);
424 tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt);
425 }
426
427 static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
428 {
429 hwif->dma_base =
430 hwif->extra_base + tx4939ide_swizzleb(TX4939IDE_DMA_Cmd);
431 /*
432 * Note that we cannot use ATA_DMA_TABLE_OFS, ATA_DMA_STATUS
433 * for big endian.
434 */
435 return ide_allocate_dma_engine(hwif);
436 }
437
438 static void tx4939ide_tf_load_fixup(ide_drive_t *drive)
439 {
440 ide_hwif_t *hwif = drive->hwif;
441 void __iomem *base = TX4939IDE_BASE(hwif);
442 u16 sysctl = hwif->select_data >> (drive->dn ? 16 : 0);
443
444 /*
445 * Fix ATA100 CORE System Control Register. (The write to the
446 * Device/Head register may write wrong data to the System
447 * Control Register)
448 * While Sys_Ctl is written here, selectproc is not needed.
449 */
450 tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
451 }
452
453 #ifdef __BIG_ENDIAN
454
455 /* custom iops (independent from SWAP_IO_SPACE) */
456 static u8 tx4939ide_inb(unsigned long port)
457 {
458 return __raw_readb((void __iomem *)port);
459 }
460
461 static void tx4939ide_outb(u8 value, unsigned long port)
462 {
463 __raw_writeb(value, (void __iomem *)port);
464 }
465
466 static void tx4939ide_tf_load(ide_drive_t *drive, struct ide_cmd *cmd)
467 {
468 ide_hwif_t *hwif = drive->hwif;
469 struct ide_io_ports *io_ports = &hwif->io_ports;
470 struct ide_taskfile *tf = &cmd->tf;
471 u8 HIHI = cmd->tf_flags & IDE_TFLAG_LBA48 ? 0xE0 : 0xEF;
472
473 if (cmd->ftf_flags & IDE_FTFLAG_FLAGGED)
474 HIHI = 0xFF;
475
476 if (cmd->ftf_flags & IDE_FTFLAG_OUT_DATA) {
477 u16 data = (tf->hob_data << 8) | tf->data;
478
479 /* no endian swap */
480 __raw_writew(data, (void __iomem *)io_ports->data_addr);
481 }
482
483 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
484 tx4939ide_outb(tf->hob_feature, io_ports->feature_addr);
485 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
486 tx4939ide_outb(tf->hob_nsect, io_ports->nsect_addr);
487 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
488 tx4939ide_outb(tf->hob_lbal, io_ports->lbal_addr);
489 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
490 tx4939ide_outb(tf->hob_lbam, io_ports->lbam_addr);
491 if (cmd->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
492 tx4939ide_outb(tf->hob_lbah, io_ports->lbah_addr);
493
494 if (cmd->tf_flags & IDE_TFLAG_OUT_FEATURE)
495 tx4939ide_outb(tf->feature, io_ports->feature_addr);
496 if (cmd->tf_flags & IDE_TFLAG_OUT_NSECT)
497 tx4939ide_outb(tf->nsect, io_ports->nsect_addr);
498 if (cmd->tf_flags & IDE_TFLAG_OUT_LBAL)
499 tx4939ide_outb(tf->lbal, io_ports->lbal_addr);
500 if (cmd->tf_flags & IDE_TFLAG_OUT_LBAM)
501 tx4939ide_outb(tf->lbam, io_ports->lbam_addr);
502 if (cmd->tf_flags & IDE_TFLAG_OUT_LBAH)
503 tx4939ide_outb(tf->lbah, io_ports->lbah_addr);
504
505 if (cmd->tf_flags & IDE_TFLAG_OUT_DEVICE) {
506 tx4939ide_outb((tf->device & HIHI) | drive->select,
507 io_ports->device_addr);
508 tx4939ide_tf_load_fixup(drive);
509 }
510 }
511
512 static void tx4939ide_tf_read(ide_drive_t *drive, struct ide_cmd *cmd)
513 {
514 ide_hwif_t *hwif = drive->hwif;
515 struct ide_io_ports *io_ports = &hwif->io_ports;
516 struct ide_taskfile *tf = &cmd->tf;
517
518 if (cmd->ftf_flags & IDE_FTFLAG_IN_DATA) {
519 u16 data;
520
521 /* no endian swap */
522 data = __raw_readw((void __iomem *)io_ports->data_addr);
523 tf->data = data & 0xff;
524 tf->hob_data = (data >> 8) & 0xff;
525 }
526
527 /* be sure we're looking at the low order bits */
528 tx4939ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
529
530 if (cmd->tf_flags & IDE_TFLAG_IN_FEATURE)
531 tf->feature = tx4939ide_inb(io_ports->feature_addr);
532 if (cmd->tf_flags & IDE_TFLAG_IN_NSECT)
533 tf->nsect = tx4939ide_inb(io_ports->nsect_addr);
534 if (cmd->tf_flags & IDE_TFLAG_IN_LBAL)
535 tf->lbal = tx4939ide_inb(io_ports->lbal_addr);
536 if (cmd->tf_flags & IDE_TFLAG_IN_LBAM)
537 tf->lbam = tx4939ide_inb(io_ports->lbam_addr);
538 if (cmd->tf_flags & IDE_TFLAG_IN_LBAH)
539 tf->lbah = tx4939ide_inb(io_ports->lbah_addr);
540 if (cmd->tf_flags & IDE_TFLAG_IN_DEVICE)
541 tf->device = tx4939ide_inb(io_ports->device_addr);
542
543 if (cmd->tf_flags & IDE_TFLAG_LBA48) {
544 tx4939ide_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
545
546 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
547 tf->hob_feature =
548 tx4939ide_inb(io_ports->feature_addr);
549 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
550 tf->hob_nsect = tx4939ide_inb(io_ports->nsect_addr);
551 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
552 tf->hob_lbal = tx4939ide_inb(io_ports->lbal_addr);
553 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
554 tf->hob_lbam = tx4939ide_inb(io_ports->lbam_addr);
555 if (cmd->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
556 tf->hob_lbah = tx4939ide_inb(io_ports->lbah_addr);
557 }
558 }
559
560 static void tx4939ide_input_data_swap(ide_drive_t *drive, struct request *rq,
561 void *buf, unsigned int len)
562 {
563 unsigned long port = drive->hwif->io_ports.data_addr;
564 unsigned short *ptr = buf;
565 unsigned int count = (len + 1) / 2;
566
567 while (count--)
568 *ptr++ = cpu_to_le16(__raw_readw((void __iomem *)port));
569 __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
570 }
571
572 static void tx4939ide_output_data_swap(ide_drive_t *drive, struct request *rq,
573 void *buf, unsigned int len)
574 {
575 unsigned long port = drive->hwif->io_ports.data_addr;
576 unsigned short *ptr = buf;
577 unsigned int count = (len + 1) / 2;
578
579 while (count--) {
580 __raw_writew(le16_to_cpu(*ptr), (void __iomem *)port);
581 ptr++;
582 }
583 __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
584 }
585
586 static const struct ide_tp_ops tx4939ide_tp_ops = {
587 .exec_command = ide_exec_command,
588 .read_status = ide_read_status,
589 .read_altstatus = ide_read_altstatus,
590
591 .set_irq = ide_set_irq,
592
593 .tf_load = tx4939ide_tf_load,
594 .tf_read = tx4939ide_tf_read,
595
596 .input_data = tx4939ide_input_data_swap,
597 .output_data = tx4939ide_output_data_swap,
598 };
599
600 #else /* __LITTLE_ENDIAN */
601
602 static void tx4939ide_tf_load(ide_drive_t *drive, struct ide_cmd *cmd)
603 {
604 ide_tf_load(drive, cmd);
605
606 if (cmd->tf_flags & IDE_TFLAG_OUT_DEVICE)
607 tx4939ide_tf_load_fixup(drive);
608 }
609
610 static const struct ide_tp_ops tx4939ide_tp_ops = {
611 .exec_command = ide_exec_command,
612 .read_status = ide_read_status,
613 .read_altstatus = ide_read_altstatus,
614
615 .set_irq = ide_set_irq,
616
617 .tf_load = tx4939ide_tf_load,
618 .tf_read = ide_tf_read,
619
620 .input_data = ide_input_data,
621 .output_data = ide_output_data,
622 };
623
624 #endif /* __LITTLE_ENDIAN */
625
626 static const struct ide_port_ops tx4939ide_port_ops = {
627 .set_pio_mode = tx4939ide_set_pio_mode,
628 .set_dma_mode = tx4939ide_set_dma_mode,
629 .clear_irq = tx4939ide_clear_irq,
630 .cable_detect = tx4939ide_cable_detect,
631 };
632
633 static const struct ide_dma_ops tx4939ide_dma_ops = {
634 .dma_host_set = tx4939ide_dma_host_set,
635 .dma_setup = tx4939ide_dma_setup,
636 .dma_exec_cmd = ide_dma_exec_cmd,
637 .dma_start = ide_dma_start,
638 .dma_end = tx4939ide_dma_end,
639 .dma_test_irq = tx4939ide_dma_test_irq,
640 .dma_lost_irq = ide_dma_lost_irq,
641 .dma_timeout = ide_dma_timeout,
642 .dma_sff_read_status = tx4939ide_dma_sff_read_status,
643 };
644
645 static const struct ide_port_info tx4939ide_port_info __initdata = {
646 .init_hwif = tx4939ide_init_hwif,
647 .init_dma = tx4939ide_init_dma,
648 .port_ops = &tx4939ide_port_ops,
649 .dma_ops = &tx4939ide_dma_ops,
650 .tp_ops = &tx4939ide_tp_ops,
651 .host_flags = IDE_HFLAG_MMIO,
652 .pio_mask = ATA_PIO4,
653 .mwdma_mask = ATA_MWDMA2,
654 .udma_mask = ATA_UDMA5,
655 .chipset = ide_generic,
656 };
657
658 static int __init tx4939ide_probe(struct platform_device *pdev)
659 {
660 hw_regs_t hw;
661 hw_regs_t *hws[] = { &hw, NULL, NULL, NULL };
662 struct ide_host *host;
663 struct resource *res;
664 int irq, ret;
665 unsigned long mapbase;
666
667 irq = platform_get_irq(pdev, 0);
668 if (irq < 0)
669 return -ENODEV;
670 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
671 if (!res)
672 return -ENODEV;
673
674 if (!devm_request_mem_region(&pdev->dev, res->start,
675 res->end - res->start + 1, "tx4938ide"))
676 return -EBUSY;
677 mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
678 res->end - res->start + 1);
679 if (!mapbase)
680 return -EBUSY;
681 memset(&hw, 0, sizeof(hw));
682 hw.io_ports.data_addr =
683 mapbase + tx4939ide_swizzlew(TX4939IDE_Data);
684 hw.io_ports.error_addr =
685 mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Feature);
686 hw.io_ports.nsect_addr =
687 mapbase + tx4939ide_swizzleb(TX4939IDE_Sec);
688 hw.io_ports.lbal_addr =
689 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0);
690 hw.io_ports.lbam_addr =
691 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1);
692 hw.io_ports.lbah_addr =
693 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2);
694 hw.io_ports.device_addr =
695 mapbase + tx4939ide_swizzleb(TX4939IDE_DevHead);
696 hw.io_ports.command_addr =
697 mapbase + tx4939ide_swizzleb(TX4939IDE_Stat_Cmd);
698 hw.io_ports.ctl_addr =
699 mapbase + tx4939ide_swizzleb(TX4939IDE_AltStat_DevCtl);
700 hw.irq = irq;
701 hw.dev = &pdev->dev;
702
703 pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq);
704 host = ide_host_alloc(&tx4939ide_port_info, hws);
705 if (!host)
706 return -ENOMEM;
707 /* use extra_base for base address of the all registers */
708 host->ports[0]->extra_base = mapbase;
709 ret = ide_host_register(host, &tx4939ide_port_info, hws);
710 if (ret) {
711 ide_host_free(host);
712 return ret;
713 }
714 platform_set_drvdata(pdev, host);
715 return 0;
716 }
717
718 static int __exit tx4939ide_remove(struct platform_device *pdev)
719 {
720 struct ide_host *host = platform_get_drvdata(pdev);
721
722 ide_host_remove(host);
723 return 0;
724 }
725
726 #ifdef CONFIG_PM
727 static int tx4939ide_resume(struct platform_device *dev)
728 {
729 struct ide_host *host = platform_get_drvdata(dev);
730 ide_hwif_t *hwif = host->ports[0];
731
732 tx4939ide_init_hwif(hwif);
733 return 0;
734 }
735 #else
736 #define tx4939ide_resume NULL
737 #endif
738
739 static struct platform_driver tx4939ide_driver = {
740 .driver = {
741 .name = MODNAME,
742 .owner = THIS_MODULE,
743 },
744 .remove = __exit_p(tx4939ide_remove),
745 .resume = tx4939ide_resume,
746 };
747
748 static int __init tx4939ide_init(void)
749 {
750 return platform_driver_probe(&tx4939ide_driver, tx4939ide_probe);
751 }
752
753 static void __exit tx4939ide_exit(void)
754 {
755 platform_driver_unregister(&tx4939ide_driver);
756 }
757
758 module_init(tx4939ide_init);
759 module_exit(tx4939ide_exit);
760
761 MODULE_DESCRIPTION("TX4939 internal IDE driver");
762 MODULE_LICENSE("GPL");
763 MODULE_ALIAS("platform:tx4939ide");
Linux kernel - Deliverables
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