2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
10 * Copyright (c) 2014, Intel Corporation.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
28 #include <linux/gpio/consumer.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/iio/iio.h>
32 #include <linux/iio/sysfs.h>
33 #include <linux/iio/buffer.h>
34 #include <linux/iio/events.h>
35 #include <linux/iio/trigger.h>
36 #include <linux/iio/trigger_consumer.h>
37 #include <linux/iio/triggered_buffer.h>
39 #define BMC150_ACCEL_DRV_NAME "bmc150_accel"
40 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
41 #define BMC150_ACCEL_GPIO_NAME "bmc150_accel_int"
43 #define BMC150_ACCEL_REG_CHIP_ID 0x00
45 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
46 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07
47 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
48 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
49 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
50 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
52 #define BMC150_ACCEL_REG_PMU_LPW 0x11
53 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0
54 #define BMC150_ACCEL_PMU_MODE_SHIFT 5
55 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
56 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
58 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F
60 #define BMC150_ACCEL_DEF_RANGE_2G 0x03
61 #define BMC150_ACCEL_DEF_RANGE_4G 0x05
62 #define BMC150_ACCEL_DEF_RANGE_8G 0x08
63 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C
65 /* Default BW: 125Hz */
66 #define BMC150_ACCEL_REG_PMU_BW 0x10
67 #define BMC150_ACCEL_DEF_BW 125
69 #define BMC150_ACCEL_REG_INT_MAP_0 0x19
70 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
72 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A
73 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
74 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1)
75 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2)
77 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
78 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
79 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
80 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
82 #define BMC150_ACCEL_REG_INT_EN_0 0x16
83 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
84 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
85 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
87 #define BMC150_ACCEL_REG_INT_EN_1 0x17
88 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
89 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
90 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
92 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
93 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
95 #define BMC150_ACCEL_REG_INT_5 0x27
96 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
98 #define BMC150_ACCEL_REG_INT_6 0x28
99 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
101 /* Slope duration in terms of number of samples */
102 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1
103 /* in terms of multiples of g's/LSB, based on range */
104 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
106 #define BMC150_ACCEL_REG_XOUT_L 0x02
108 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
110 /* Sleep Duration values */
111 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05
112 #define BMC150_ACCEL_SLEEP_1_MS 0x06
113 #define BMC150_ACCEL_SLEEP_2_MS 0x07
114 #define BMC150_ACCEL_SLEEP_4_MS 0x08
115 #define BMC150_ACCEL_SLEEP_6_MS 0x09
116 #define BMC150_ACCEL_SLEEP_10_MS 0x0A
117 #define BMC150_ACCEL_SLEEP_25_MS 0x0B
118 #define BMC150_ACCEL_SLEEP_50_MS 0x0C
119 #define BMC150_ACCEL_SLEEP_100_MS 0x0D
120 #define BMC150_ACCEL_SLEEP_500_MS 0x0E
121 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F
123 #define BMC150_ACCEL_REG_TEMP 0x08
124 #define BMC150_ACCEL_TEMP_CENTER_VAL 24
126 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
127 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000
129 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
130 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
131 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
132 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F
133 #define BMC150_ACCEL_FIFO_LENGTH 32
135 enum bmc150_accel_axis
{
141 enum bmc150_power_modes
{
142 BMC150_ACCEL_SLEEP_MODE_NORMAL
,
143 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND
,
144 BMC150_ACCEL_SLEEP_MODE_LPM
,
145 BMC150_ACCEL_SLEEP_MODE_SUSPEND
= 0x04,
148 struct bmc150_scale_info
{
153 struct bmc150_accel_chip_info
{
155 const struct iio_chan_spec
*channels
;
157 const struct bmc150_scale_info scale_table
[4];
160 struct bmc150_accel_interrupt
{
161 const struct bmc150_accel_interrupt_info
*info
;
165 struct bmc150_accel_trigger
{
166 struct bmc150_accel_data
*data
;
167 struct iio_trigger
*indio_trig
;
168 int (*setup
)(struct bmc150_accel_trigger
*t
, bool state
);
173 enum bmc150_accel_interrupt_id
{
174 BMC150_ACCEL_INT_DATA_READY
,
175 BMC150_ACCEL_INT_ANY_MOTION
,
176 BMC150_ACCEL_INT_WATERMARK
,
177 BMC150_ACCEL_INTERRUPTS
,
180 enum bmc150_accel_trigger_id
{
181 BMC150_ACCEL_TRIGGER_DATA_READY
,
182 BMC150_ACCEL_TRIGGER_ANY_MOTION
,
183 BMC150_ACCEL_TRIGGERS
,
186 struct bmc150_accel_data
{
187 struct i2c_client
*client
;
188 struct bmc150_accel_interrupt interrupts
[BMC150_ACCEL_INTERRUPTS
];
189 atomic_t active_intr
;
190 struct bmc150_accel_trigger triggers
[BMC150_ACCEL_TRIGGERS
];
192 u8 fifo_mode
, watermark
;
199 int64_t timestamp
, old_timestamp
; /* Only used in hw fifo mode. */
200 const struct bmc150_accel_chip_info
*chip_info
;
203 static const struct {
207 } bmc150_accel_samp_freq_table
[] = { {15, 620000, 0x08},
216 static const struct {
219 } bmc150_accel_sample_upd_time
[] = { {0x08, 64},
228 static const struct {
231 } bmc150_accel_sleep_value_table
[] = { {0, 0},
232 {500, BMC150_ACCEL_SLEEP_500_MICRO
},
233 {1000, BMC150_ACCEL_SLEEP_1_MS
},
234 {2000, BMC150_ACCEL_SLEEP_2_MS
},
235 {4000, BMC150_ACCEL_SLEEP_4_MS
},
236 {6000, BMC150_ACCEL_SLEEP_6_MS
},
237 {10000, BMC150_ACCEL_SLEEP_10_MS
},
238 {25000, BMC150_ACCEL_SLEEP_25_MS
},
239 {50000, BMC150_ACCEL_SLEEP_50_MS
},
240 {100000, BMC150_ACCEL_SLEEP_100_MS
},
241 {500000, BMC150_ACCEL_SLEEP_500_MS
},
242 {1000000, BMC150_ACCEL_SLEEP_1_SEC
} };
245 static int bmc150_accel_set_mode(struct bmc150_accel_data
*data
,
246 enum bmc150_power_modes mode
,
255 for (i
= 0; i
< ARRAY_SIZE(bmc150_accel_sleep_value_table
);
257 if (bmc150_accel_sleep_value_table
[i
].sleep_dur
==
260 bmc150_accel_sleep_value_table
[i
].reg_value
;
268 lpw_bits
= mode
<< BMC150_ACCEL_PMU_MODE_SHIFT
;
269 lpw_bits
|= (dur_val
<< BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT
);
271 dev_dbg(&data
->client
->dev
, "Set Mode bits %x\n", lpw_bits
);
273 ret
= i2c_smbus_write_byte_data(data
->client
,
274 BMC150_ACCEL_REG_PMU_LPW
, lpw_bits
);
276 dev_err(&data
->client
->dev
, "Error writing reg_pmu_lpw\n");
283 static int bmc150_accel_set_bw(struct bmc150_accel_data
*data
, int val
,
289 for (i
= 0; i
< ARRAY_SIZE(bmc150_accel_samp_freq_table
); ++i
) {
290 if (bmc150_accel_samp_freq_table
[i
].val
== val
&&
291 bmc150_accel_samp_freq_table
[i
].val2
== val2
) {
292 ret
= i2c_smbus_write_byte_data(
294 BMC150_ACCEL_REG_PMU_BW
,
295 bmc150_accel_samp_freq_table
[i
].bw_bits
);
300 bmc150_accel_samp_freq_table
[i
].bw_bits
;
308 static int bmc150_accel_update_slope(struct bmc150_accel_data
*data
)
312 ret
= i2c_smbus_write_byte_data(data
->client
, BMC150_ACCEL_REG_INT_6
,
315 dev_err(&data
->client
->dev
, "Error writing reg_int_6\n");
319 ret
= i2c_smbus_read_byte_data(data
->client
, BMC150_ACCEL_REG_INT_5
);
321 dev_err(&data
->client
->dev
, "Error reading reg_int_5\n");
325 val
= (ret
& ~BMC150_ACCEL_SLOPE_DUR_MASK
) | data
->slope_dur
;
326 ret
= i2c_smbus_write_byte_data(data
->client
, BMC150_ACCEL_REG_INT_5
,
329 dev_err(&data
->client
->dev
, "Error write reg_int_5\n");
333 dev_dbg(&data
->client
->dev
, "%s: %x %x\n", __func__
, data
->slope_thres
,
339 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger
*t
,
343 return bmc150_accel_update_slope(t
->data
);
348 static int bmc150_accel_chip_init(struct bmc150_accel_data
*data
)
352 ret
= i2c_smbus_read_byte_data(data
->client
, BMC150_ACCEL_REG_CHIP_ID
);
354 dev_err(&data
->client
->dev
,
355 "Error: Reading chip id\n");
359 dev_dbg(&data
->client
->dev
, "Chip Id %x\n", ret
);
360 if (ret
!= data
->chip_info
->chip_id
) {
361 dev_err(&data
->client
->dev
, "Invalid chip %x\n", ret
);
365 ret
= bmc150_accel_set_mode(data
, BMC150_ACCEL_SLEEP_MODE_NORMAL
, 0);
370 ret
= bmc150_accel_set_bw(data
, BMC150_ACCEL_DEF_BW
, 0);
374 /* Set Default Range */
375 ret
= i2c_smbus_write_byte_data(data
->client
,
376 BMC150_ACCEL_REG_PMU_RANGE
,
377 BMC150_ACCEL_DEF_RANGE_4G
);
379 dev_err(&data
->client
->dev
,
380 "Error writing reg_pmu_range\n");
384 data
->range
= BMC150_ACCEL_DEF_RANGE_4G
;
386 /* Set default slope duration and thresholds */
387 data
->slope_thres
= BMC150_ACCEL_DEF_SLOPE_THRESHOLD
;
388 data
->slope_dur
= BMC150_ACCEL_DEF_SLOPE_DURATION
;
389 ret
= bmc150_accel_update_slope(data
);
393 /* Set default as latched interrupts */
394 ret
= i2c_smbus_write_byte_data(data
->client
,
395 BMC150_ACCEL_REG_INT_RST_LATCH
,
396 BMC150_ACCEL_INT_MODE_LATCH_INT
|
397 BMC150_ACCEL_INT_MODE_LATCH_RESET
);
399 dev_err(&data
->client
->dev
,
400 "Error writing reg_int_rst_latch\n");
407 static int bmc150_accel_get_bw(struct bmc150_accel_data
*data
, int *val
,
412 for (i
= 0; i
< ARRAY_SIZE(bmc150_accel_samp_freq_table
); ++i
) {
413 if (bmc150_accel_samp_freq_table
[i
].bw_bits
== data
->bw_bits
) {
414 *val
= bmc150_accel_samp_freq_table
[i
].val
;
415 *val2
= bmc150_accel_samp_freq_table
[i
].val2
;
416 return IIO_VAL_INT_PLUS_MICRO
;
424 static int bmc150_accel_get_startup_times(struct bmc150_accel_data
*data
)
428 for (i
= 0; i
< ARRAY_SIZE(bmc150_accel_sample_upd_time
); ++i
) {
429 if (bmc150_accel_sample_upd_time
[i
].bw_bits
== data
->bw_bits
)
430 return bmc150_accel_sample_upd_time
[i
].msec
;
433 return BMC150_ACCEL_MAX_STARTUP_TIME_MS
;
436 static int bmc150_accel_set_power_state(struct bmc150_accel_data
*data
, bool on
)
441 ret
= pm_runtime_get_sync(&data
->client
->dev
);
443 pm_runtime_mark_last_busy(&data
->client
->dev
);
444 ret
= pm_runtime_put_autosuspend(&data
->client
->dev
);
447 dev_err(&data
->client
->dev
,
448 "Failed: bmc150_accel_set_power_state for %d\n", on
);
450 pm_runtime_put_noidle(&data
->client
->dev
);
458 static int bmc150_accel_set_power_state(struct bmc150_accel_data
*data
, bool on
)
464 static const struct bmc150_accel_interrupt_info
{
469 } bmc150_accel_interrupts
[BMC150_ACCEL_INTERRUPTS
] = {
470 { /* data ready interrupt */
471 .map_reg
= BMC150_ACCEL_REG_INT_MAP_1
,
472 .map_bitmask
= BMC150_ACCEL_INT_MAP_1_BIT_DATA
,
473 .en_reg
= BMC150_ACCEL_REG_INT_EN_1
,
474 .en_bitmask
= BMC150_ACCEL_INT_EN_BIT_DATA_EN
,
476 { /* motion interrupt */
477 .map_reg
= BMC150_ACCEL_REG_INT_MAP_0
,
478 .map_bitmask
= BMC150_ACCEL_INT_MAP_0_BIT_SLOPE
,
479 .en_reg
= BMC150_ACCEL_REG_INT_EN_0
,
480 .en_bitmask
= BMC150_ACCEL_INT_EN_BIT_SLP_X
|
481 BMC150_ACCEL_INT_EN_BIT_SLP_Y
|
482 BMC150_ACCEL_INT_EN_BIT_SLP_Z
484 { /* fifo watermark interrupt */
485 .map_reg
= BMC150_ACCEL_REG_INT_MAP_1
,
486 .map_bitmask
= BMC150_ACCEL_INT_MAP_1_BIT_FWM
,
487 .en_reg
= BMC150_ACCEL_REG_INT_EN_1
,
488 .en_bitmask
= BMC150_ACCEL_INT_EN_BIT_FWM_EN
,
492 static void bmc150_accel_interrupts_setup(struct iio_dev
*indio_dev
,
493 struct bmc150_accel_data
*data
)
497 for (i
= 0; i
< BMC150_ACCEL_INTERRUPTS
; i
++)
498 data
->interrupts
[i
].info
= &bmc150_accel_interrupts
[i
];
501 static int bmc150_accel_set_interrupt(struct bmc150_accel_data
*data
, int i
,
504 struct bmc150_accel_interrupt
*intr
= &data
->interrupts
[i
];
505 const struct bmc150_accel_interrupt_info
*info
= intr
->info
;
509 if (atomic_inc_return(&intr
->users
) > 1)
512 if (atomic_dec_return(&intr
->users
) > 0)
517 * We will expect the enable and disable to do operation in
518 * in reverse order. This will happen here anyway as our
519 * resume operation uses sync mode runtime pm calls, the
520 * suspend operation will be delayed by autosuspend delay
521 * So the disable operation will still happen in reverse of
522 * enable operation. When runtime pm is disabled the mode
523 * is always on so sequence doesn't matter
525 ret
= bmc150_accel_set_power_state(data
, state
);
529 /* map the interrupt to the appropriate pins */
530 ret
= i2c_smbus_read_byte_data(data
->client
, info
->map_reg
);
532 dev_err(&data
->client
->dev
, "Error reading reg_int_map\n");
533 goto out_fix_power_state
;
536 ret
|= info
->map_bitmask
;
538 ret
&= ~info
->map_bitmask
;
540 ret
= i2c_smbus_write_byte_data(data
->client
, info
->map_reg
,
543 dev_err(&data
->client
->dev
, "Error writing reg_int_map\n");
544 goto out_fix_power_state
;
547 /* enable/disable the interrupt */
548 ret
= i2c_smbus_read_byte_data(data
->client
, info
->en_reg
);
550 dev_err(&data
->client
->dev
, "Error reading reg_int_en\n");
551 goto out_fix_power_state
;
555 ret
|= info
->en_bitmask
;
557 ret
&= ~info
->en_bitmask
;
559 ret
= i2c_smbus_write_byte_data(data
->client
, info
->en_reg
, ret
);
561 dev_err(&data
->client
->dev
, "Error writing reg_int_en\n");
562 goto out_fix_power_state
;
566 atomic_inc(&data
->active_intr
);
568 atomic_dec(&data
->active_intr
);
573 bmc150_accel_set_power_state(data
, false);
578 static int bmc150_accel_set_scale(struct bmc150_accel_data
*data
, int val
)
582 for (i
= 0; i
< ARRAY_SIZE(data
->chip_info
->scale_table
); ++i
) {
583 if (data
->chip_info
->scale_table
[i
].scale
== val
) {
584 ret
= i2c_smbus_write_byte_data(
586 BMC150_ACCEL_REG_PMU_RANGE
,
587 data
->chip_info
->scale_table
[i
].reg_range
);
589 dev_err(&data
->client
->dev
,
590 "Error writing pmu_range\n");
594 data
->range
= data
->chip_info
->scale_table
[i
].reg_range
;
602 static int bmc150_accel_get_temp(struct bmc150_accel_data
*data
, int *val
)
606 mutex_lock(&data
->mutex
);
608 ret
= i2c_smbus_read_byte_data(data
->client
, BMC150_ACCEL_REG_TEMP
);
610 dev_err(&data
->client
->dev
, "Error reading reg_temp\n");
611 mutex_unlock(&data
->mutex
);
614 *val
= sign_extend32(ret
, 7);
616 mutex_unlock(&data
->mutex
);
621 static int bmc150_accel_get_axis(struct bmc150_accel_data
*data
,
622 struct iio_chan_spec
const *chan
,
626 int axis
= chan
->scan_index
;
628 mutex_lock(&data
->mutex
);
629 ret
= bmc150_accel_set_power_state(data
, true);
631 mutex_unlock(&data
->mutex
);
635 ret
= i2c_smbus_read_word_data(data
->client
,
636 BMC150_ACCEL_AXIS_TO_REG(axis
));
638 dev_err(&data
->client
->dev
, "Error reading axis %d\n", axis
);
639 bmc150_accel_set_power_state(data
, false);
640 mutex_unlock(&data
->mutex
);
643 *val
= sign_extend32(ret
>> chan
->scan_type
.shift
,
644 chan
->scan_type
.realbits
- 1);
645 ret
= bmc150_accel_set_power_state(data
, false);
646 mutex_unlock(&data
->mutex
);
653 static int bmc150_accel_read_raw(struct iio_dev
*indio_dev
,
654 struct iio_chan_spec
const *chan
,
655 int *val
, int *val2
, long mask
)
657 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
661 case IIO_CHAN_INFO_RAW
:
662 switch (chan
->type
) {
664 return bmc150_accel_get_temp(data
, val
);
666 if (iio_buffer_enabled(indio_dev
))
669 return bmc150_accel_get_axis(data
, chan
, val
);
673 case IIO_CHAN_INFO_OFFSET
:
674 if (chan
->type
== IIO_TEMP
) {
675 *val
= BMC150_ACCEL_TEMP_CENTER_VAL
;
679 case IIO_CHAN_INFO_SCALE
:
681 switch (chan
->type
) {
684 return IIO_VAL_INT_PLUS_MICRO
;
688 const struct bmc150_scale_info
*si
;
689 int st_size
= ARRAY_SIZE(data
->chip_info
->scale_table
);
691 for (i
= 0; i
< st_size
; ++i
) {
692 si
= &data
->chip_info
->scale_table
[i
];
693 if (si
->reg_range
== data
->range
) {
695 return IIO_VAL_INT_PLUS_MICRO
;
703 case IIO_CHAN_INFO_SAMP_FREQ
:
704 mutex_lock(&data
->mutex
);
705 ret
= bmc150_accel_get_bw(data
, val
, val2
);
706 mutex_unlock(&data
->mutex
);
713 static int bmc150_accel_write_raw(struct iio_dev
*indio_dev
,
714 struct iio_chan_spec
const *chan
,
715 int val
, int val2
, long mask
)
717 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
721 case IIO_CHAN_INFO_SAMP_FREQ
:
722 mutex_lock(&data
->mutex
);
723 ret
= bmc150_accel_set_bw(data
, val
, val2
);
724 mutex_unlock(&data
->mutex
);
726 case IIO_CHAN_INFO_SCALE
:
730 mutex_lock(&data
->mutex
);
731 ret
= bmc150_accel_set_scale(data
, val2
);
732 mutex_unlock(&data
->mutex
);
741 static int bmc150_accel_read_event(struct iio_dev
*indio_dev
,
742 const struct iio_chan_spec
*chan
,
743 enum iio_event_type type
,
744 enum iio_event_direction dir
,
745 enum iio_event_info info
,
748 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
752 case IIO_EV_INFO_VALUE
:
753 *val
= data
->slope_thres
;
755 case IIO_EV_INFO_PERIOD
:
756 *val
= data
->slope_dur
;
765 static int bmc150_accel_write_event(struct iio_dev
*indio_dev
,
766 const struct iio_chan_spec
*chan
,
767 enum iio_event_type type
,
768 enum iio_event_direction dir
,
769 enum iio_event_info info
,
772 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
774 if (data
->ev_enable_state
)
778 case IIO_EV_INFO_VALUE
:
779 data
->slope_thres
= val
& 0xFF;
781 case IIO_EV_INFO_PERIOD
:
782 data
->slope_dur
= val
& BMC150_ACCEL_SLOPE_DUR_MASK
;
791 static int bmc150_accel_read_event_config(struct iio_dev
*indio_dev
,
792 const struct iio_chan_spec
*chan
,
793 enum iio_event_type type
,
794 enum iio_event_direction dir
)
797 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
799 return data
->ev_enable_state
;
802 static int bmc150_accel_write_event_config(struct iio_dev
*indio_dev
,
803 const struct iio_chan_spec
*chan
,
804 enum iio_event_type type
,
805 enum iio_event_direction dir
,
808 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
811 if (state
== data
->ev_enable_state
)
814 mutex_lock(&data
->mutex
);
816 ret
= bmc150_accel_set_interrupt(data
, BMC150_ACCEL_INT_ANY_MOTION
,
819 mutex_unlock(&data
->mutex
);
823 data
->ev_enable_state
= state
;
824 mutex_unlock(&data
->mutex
);
829 static int bmc150_accel_validate_trigger(struct iio_dev
*indio_dev
,
830 struct iio_trigger
*trig
)
832 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
835 for (i
= 0; i
< BMC150_ACCEL_TRIGGERS
; i
++) {
836 if (data
->triggers
[i
].indio_trig
== trig
)
843 static ssize_t
bmc150_accel_get_fifo_watermark(struct device
*dev
,
844 struct device_attribute
*attr
,
847 struct iio_dev
*indio_dev
= dev_to_iio_dev(dev
);
848 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
851 mutex_lock(&data
->mutex
);
852 wm
= data
->watermark
;
853 mutex_unlock(&data
->mutex
);
855 return sprintf(buf
, "%d\n", wm
);
858 static ssize_t
bmc150_accel_get_fifo_state(struct device
*dev
,
859 struct device_attribute
*attr
,
862 struct iio_dev
*indio_dev
= dev_to_iio_dev(dev
);
863 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
866 mutex_lock(&data
->mutex
);
867 state
= data
->fifo_mode
;
868 mutex_unlock(&data
->mutex
);
870 return sprintf(buf
, "%d\n", state
);
873 static IIO_CONST_ATTR(hwfifo_watermark_min
, "1");
874 static IIO_CONST_ATTR(hwfifo_watermark_max
,
875 __stringify(BMC150_ACCEL_FIFO_LENGTH
));
876 static IIO_DEVICE_ATTR(hwfifo_enabled
, S_IRUGO
,
877 bmc150_accel_get_fifo_state
, NULL
, 0);
878 static IIO_DEVICE_ATTR(hwfifo_watermark
, S_IRUGO
,
879 bmc150_accel_get_fifo_watermark
, NULL
, 0);
881 static const struct attribute
*bmc150_accel_fifo_attributes
[] = {
882 &iio_const_attr_hwfifo_watermark_min
.dev_attr
.attr
,
883 &iio_const_attr_hwfifo_watermark_max
.dev_attr
.attr
,
884 &iio_dev_attr_hwfifo_watermark
.dev_attr
.attr
,
885 &iio_dev_attr_hwfifo_enabled
.dev_attr
.attr
,
889 static int bmc150_accel_set_watermark(struct iio_dev
*indio_dev
, unsigned val
)
891 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
893 if (val
> BMC150_ACCEL_FIFO_LENGTH
)
894 val
= BMC150_ACCEL_FIFO_LENGTH
;
896 mutex_lock(&data
->mutex
);
897 data
->watermark
= val
;
898 mutex_unlock(&data
->mutex
);
904 * We must read at least one full frame in one burst, otherwise the rest of the
905 * frame data is discarded.
907 static int bmc150_accel_fifo_transfer(const struct i2c_client
*client
,
908 char *buffer
, int samples
)
910 int sample_length
= 3 * 2;
911 u8 reg_fifo_data
= BMC150_ACCEL_REG_FIFO_DATA
;
914 if (i2c_check_functionality(client
->adapter
, I2C_FUNC_I2C
)) {
915 struct i2c_msg msg
[2] = {
917 .addr
= client
->addr
,
919 .buf
= ®_fifo_data
,
920 .len
= sizeof(reg_fifo_data
),
923 .addr
= client
->addr
,
926 .len
= samples
* sample_length
,
930 ret
= i2c_transfer(client
->adapter
, msg
, 2);
936 int i
, step
= I2C_SMBUS_BLOCK_MAX
/ sample_length
;
938 for (i
= 0; i
< samples
* sample_length
; i
+= step
) {
939 ret
= i2c_smbus_read_i2c_block_data(client
,
952 dev_err(&client
->dev
, "Error transferring data from fifo\n");
957 static int __bmc150_accel_fifo_flush(struct iio_dev
*indio_dev
,
958 unsigned samples
, bool irq
)
960 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
963 u16 buffer
[BMC150_ACCEL_FIFO_LENGTH
* 3];
965 uint64_t sample_period
;
966 ret
= i2c_smbus_read_byte_data(data
->client
,
967 BMC150_ACCEL_REG_FIFO_STATUS
);
969 dev_err(&data
->client
->dev
, "Error reading reg_fifo_status\n");
979 * If we getting called from IRQ handler we know the stored timestamp is
980 * fairly accurate for the last stored sample. Otherwise, if we are
981 * called as a result of a read operation from userspace and hence
982 * before the watermark interrupt was triggered, take a timestamp
983 * now. We can fall anywhere in between two samples so the error in this
984 * case is at most one sample period.
987 data
->old_timestamp
= data
->timestamp
;
988 data
->timestamp
= iio_get_time_ns();
992 * Approximate timestamps for each of the sample based on the sampling
993 * frequency, timestamp for last sample and number of samples.
995 * Note that we can't use the current bandwidth settings to compute the
996 * sample period because the sample rate varies with the device
997 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
998 * small variation adds when we store a large number of samples and
999 * creates significant jitter between the last and first samples in
1000 * different batches (e.g. 32ms vs 21ms).
1002 * To avoid this issue we compute the actual sample period ourselves
1003 * based on the timestamp delta between the last two flush operations.
1005 sample_period
= (data
->timestamp
- data
->old_timestamp
);
1006 do_div(sample_period
, count
);
1007 tstamp
= data
->timestamp
- (count
- 1) * sample_period
;
1009 if (samples
&& count
> samples
)
1012 ret
= bmc150_accel_fifo_transfer(data
->client
, (u8
*)buffer
, count
);
1017 * Ideally we want the IIO core to handle the demux when running in fifo
1018 * mode but not when running in triggered buffer mode. Unfortunately
1019 * this does not seem to be possible, so stick with driver demux for
1022 for (i
= 0; i
< count
; i
++) {
1027 for_each_set_bit(bit
, indio_dev
->active_scan_mask
,
1028 indio_dev
->masklength
)
1029 memcpy(&sample
[j
++], &buffer
[i
* 3 + bit
], 2);
1031 iio_push_to_buffers_with_timestamp(indio_dev
, sample
, tstamp
);
1033 tstamp
+= sample_period
;
1039 static int bmc150_accel_fifo_flush(struct iio_dev
*indio_dev
, unsigned samples
)
1041 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1044 mutex_lock(&data
->mutex
);
1045 ret
= __bmc150_accel_fifo_flush(indio_dev
, samples
, false);
1046 mutex_unlock(&data
->mutex
);
1051 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
1052 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
1054 static struct attribute
*bmc150_accel_attributes
[] = {
1055 &iio_const_attr_sampling_frequency_available
.dev_attr
.attr
,
1059 static const struct attribute_group bmc150_accel_attrs_group
= {
1060 .attrs
= bmc150_accel_attributes
,
1063 static const struct iio_event_spec bmc150_accel_event
= {
1064 .type
= IIO_EV_TYPE_ROC
,
1065 .dir
= IIO_EV_DIR_EITHER
,
1066 .mask_separate
= BIT(IIO_EV_INFO_VALUE
) |
1067 BIT(IIO_EV_INFO_ENABLE
) |
1068 BIT(IIO_EV_INFO_PERIOD
)
1071 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \
1072 .type = IIO_ACCEL, \
1074 .channel2 = IIO_MOD_##_axis, \
1075 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
1076 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
1077 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1078 .scan_index = AXIS_##_axis, \
1081 .realbits = (bits), \
1082 .storagebits = 16, \
1083 .shift = 16 - (bits), \
1085 .event_spec = &bmc150_accel_event, \
1086 .num_event_specs = 1 \
1089 #define BMC150_ACCEL_CHANNELS(bits) { \
1092 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1093 BIT(IIO_CHAN_INFO_SCALE) | \
1094 BIT(IIO_CHAN_INFO_OFFSET), \
1097 BMC150_ACCEL_CHANNEL(X, bits), \
1098 BMC150_ACCEL_CHANNEL(Y, bits), \
1099 BMC150_ACCEL_CHANNEL(Z, bits), \
1100 IIO_CHAN_SOFT_TIMESTAMP(3), \
1103 static const struct iio_chan_spec bma222e_accel_channels
[] =
1104 BMC150_ACCEL_CHANNELS(8);
1105 static const struct iio_chan_spec bma250e_accel_channels
[] =
1106 BMC150_ACCEL_CHANNELS(10);
1107 static const struct iio_chan_spec bmc150_accel_channels
[] =
1108 BMC150_ACCEL_CHANNELS(12);
1109 static const struct iio_chan_spec bma280_accel_channels
[] =
1110 BMC150_ACCEL_CHANNELS(14);
1121 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl
[] = {
1124 .channels
= bmc150_accel_channels
,
1125 .num_channels
= ARRAY_SIZE(bmc150_accel_channels
),
1126 .scale_table
= { {9610, BMC150_ACCEL_DEF_RANGE_2G
},
1127 {19122, BMC150_ACCEL_DEF_RANGE_4G
},
1128 {38344, BMC150_ACCEL_DEF_RANGE_8G
},
1129 {76590, BMC150_ACCEL_DEF_RANGE_16G
} },
1133 .channels
= bmc150_accel_channels
,
1134 .num_channels
= ARRAY_SIZE(bmc150_accel_channels
),
1135 .scale_table
= { {9610, BMC150_ACCEL_DEF_RANGE_2G
},
1136 {19122, BMC150_ACCEL_DEF_RANGE_4G
},
1137 {38344, BMC150_ACCEL_DEF_RANGE_8G
},
1138 {76590, BMC150_ACCEL_DEF_RANGE_16G
} },
1142 .channels
= bmc150_accel_channels
,
1143 .num_channels
= ARRAY_SIZE(bmc150_accel_channels
),
1144 .scale_table
= { {9610, BMC150_ACCEL_DEF_RANGE_2G
},
1145 {19122, BMC150_ACCEL_DEF_RANGE_4G
},
1146 {38344, BMC150_ACCEL_DEF_RANGE_8G
},
1147 {76590, BMC150_ACCEL_DEF_RANGE_16G
} },
1151 .channels
= bma250e_accel_channels
,
1152 .num_channels
= ARRAY_SIZE(bma250e_accel_channels
),
1153 .scale_table
= { {38344, BMC150_ACCEL_DEF_RANGE_2G
},
1154 {76590, BMC150_ACCEL_DEF_RANGE_4G
},
1155 {153277, BMC150_ACCEL_DEF_RANGE_8G
},
1156 {306457, BMC150_ACCEL_DEF_RANGE_16G
} },
1160 .channels
= bma222e_accel_channels
,
1161 .num_channels
= ARRAY_SIZE(bma222e_accel_channels
),
1162 .scale_table
= { {153277, BMC150_ACCEL_DEF_RANGE_2G
},
1163 {306457, BMC150_ACCEL_DEF_RANGE_4G
},
1164 {612915, BMC150_ACCEL_DEF_RANGE_8G
},
1165 {1225831, BMC150_ACCEL_DEF_RANGE_16G
} },
1169 .channels
= bma280_accel_channels
,
1170 .num_channels
= ARRAY_SIZE(bma280_accel_channels
),
1171 .scale_table
= { {2392, BMC150_ACCEL_DEF_RANGE_2G
},
1172 {4785, BMC150_ACCEL_DEF_RANGE_4G
},
1173 {9581, BMC150_ACCEL_DEF_RANGE_8G
},
1174 {19152, BMC150_ACCEL_DEF_RANGE_16G
} },
1178 static const struct iio_info bmc150_accel_info
= {
1179 .attrs
= &bmc150_accel_attrs_group
,
1180 .read_raw
= bmc150_accel_read_raw
,
1181 .write_raw
= bmc150_accel_write_raw
,
1182 .read_event_value
= bmc150_accel_read_event
,
1183 .write_event_value
= bmc150_accel_write_event
,
1184 .write_event_config
= bmc150_accel_write_event_config
,
1185 .read_event_config
= bmc150_accel_read_event_config
,
1186 .driver_module
= THIS_MODULE
,
1189 static const struct iio_info bmc150_accel_info_fifo
= {
1190 .attrs
= &bmc150_accel_attrs_group
,
1191 .read_raw
= bmc150_accel_read_raw
,
1192 .write_raw
= bmc150_accel_write_raw
,
1193 .read_event_value
= bmc150_accel_read_event
,
1194 .write_event_value
= bmc150_accel_write_event
,
1195 .write_event_config
= bmc150_accel_write_event_config
,
1196 .read_event_config
= bmc150_accel_read_event_config
,
1197 .validate_trigger
= bmc150_accel_validate_trigger
,
1198 .hwfifo_set_watermark
= bmc150_accel_set_watermark
,
1199 .hwfifo_flush_to_buffer
= bmc150_accel_fifo_flush
,
1200 .driver_module
= THIS_MODULE
,
1203 static irqreturn_t
bmc150_accel_trigger_handler(int irq
, void *p
)
1205 struct iio_poll_func
*pf
= p
;
1206 struct iio_dev
*indio_dev
= pf
->indio_dev
;
1207 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1208 int bit
, ret
, i
= 0;
1210 mutex_lock(&data
->mutex
);
1211 for_each_set_bit(bit
, indio_dev
->active_scan_mask
,
1212 indio_dev
->masklength
) {
1213 ret
= i2c_smbus_read_word_data(data
->client
,
1214 BMC150_ACCEL_AXIS_TO_REG(bit
));
1216 mutex_unlock(&data
->mutex
);
1219 data
->buffer
[i
++] = ret
;
1221 mutex_unlock(&data
->mutex
);
1223 iio_push_to_buffers_with_timestamp(indio_dev
, data
->buffer
,
1226 iio_trigger_notify_done(indio_dev
->trig
);
1231 static int bmc150_accel_trig_try_reen(struct iio_trigger
*trig
)
1233 struct bmc150_accel_trigger
*t
= iio_trigger_get_drvdata(trig
);
1234 struct bmc150_accel_data
*data
= t
->data
;
1237 /* new data interrupts don't need ack */
1238 if (t
== &t
->data
->triggers
[BMC150_ACCEL_TRIGGER_DATA_READY
])
1241 mutex_lock(&data
->mutex
);
1242 /* clear any latched interrupt */
1243 ret
= i2c_smbus_write_byte_data(data
->client
,
1244 BMC150_ACCEL_REG_INT_RST_LATCH
,
1245 BMC150_ACCEL_INT_MODE_LATCH_INT
|
1246 BMC150_ACCEL_INT_MODE_LATCH_RESET
);
1247 mutex_unlock(&data
->mutex
);
1249 dev_err(&data
->client
->dev
,
1250 "Error writing reg_int_rst_latch\n");
1257 static int bmc150_accel_trigger_set_state(struct iio_trigger
*trig
,
1260 struct bmc150_accel_trigger
*t
= iio_trigger_get_drvdata(trig
);
1261 struct bmc150_accel_data
*data
= t
->data
;
1264 mutex_lock(&data
->mutex
);
1266 if (t
->enabled
== state
) {
1267 mutex_unlock(&data
->mutex
);
1272 ret
= t
->setup(t
, state
);
1274 mutex_unlock(&data
->mutex
);
1279 ret
= bmc150_accel_set_interrupt(data
, t
->intr
, state
);
1281 mutex_unlock(&data
->mutex
);
1287 mutex_unlock(&data
->mutex
);
1292 static const struct iio_trigger_ops bmc150_accel_trigger_ops
= {
1293 .set_trigger_state
= bmc150_accel_trigger_set_state
,
1294 .try_reenable
= bmc150_accel_trig_try_reen
,
1295 .owner
= THIS_MODULE
,
1298 static int bmc150_accel_handle_roc_event(struct iio_dev
*indio_dev
)
1300 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1304 ret
= i2c_smbus_read_byte_data(data
->client
,
1305 BMC150_ACCEL_REG_INT_STATUS_2
);
1307 dev_err(&data
->client
->dev
, "Error reading reg_int_status_2\n");
1311 if (ret
& BMC150_ACCEL_ANY_MOTION_BIT_SIGN
)
1312 dir
= IIO_EV_DIR_FALLING
;
1314 dir
= IIO_EV_DIR_RISING
;
1316 if (ret
& BMC150_ACCEL_ANY_MOTION_BIT_X
)
1317 iio_push_event(indio_dev
, IIO_MOD_EVENT_CODE(IIO_ACCEL
,
1323 if (ret
& BMC150_ACCEL_ANY_MOTION_BIT_Y
)
1324 iio_push_event(indio_dev
, IIO_MOD_EVENT_CODE(IIO_ACCEL
,
1330 if (ret
& BMC150_ACCEL_ANY_MOTION_BIT_Z
)
1331 iio_push_event(indio_dev
, IIO_MOD_EVENT_CODE(IIO_ACCEL
,
1340 static irqreturn_t
bmc150_accel_irq_thread_handler(int irq
, void *private)
1342 struct iio_dev
*indio_dev
= private;
1343 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1347 mutex_lock(&data
->mutex
);
1349 if (data
->fifo_mode
) {
1350 ret
= __bmc150_accel_fifo_flush(indio_dev
,
1351 BMC150_ACCEL_FIFO_LENGTH
, true);
1356 if (data
->ev_enable_state
) {
1357 ret
= bmc150_accel_handle_roc_event(indio_dev
);
1363 ret
= i2c_smbus_write_byte_data(data
->client
,
1364 BMC150_ACCEL_REG_INT_RST_LATCH
,
1365 BMC150_ACCEL_INT_MODE_LATCH_INT
|
1366 BMC150_ACCEL_INT_MODE_LATCH_RESET
);
1368 dev_err(&data
->client
->dev
, "Error writing reg_int_rst_latch\n");
1374 mutex_unlock(&data
->mutex
);
1379 static irqreturn_t
bmc150_accel_irq_handler(int irq
, void *private)
1381 struct iio_dev
*indio_dev
= private;
1382 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1386 data
->old_timestamp
= data
->timestamp
;
1387 data
->timestamp
= iio_get_time_ns();
1389 for (i
= 0; i
< BMC150_ACCEL_TRIGGERS
; i
++) {
1390 if (data
->triggers
[i
].enabled
) {
1391 iio_trigger_poll(data
->triggers
[i
].indio_trig
);
1397 if (data
->ev_enable_state
|| data
->fifo_mode
)
1398 return IRQ_WAKE_THREAD
;
1406 static const char *bmc150_accel_match_acpi_device(struct device
*dev
, int *data
)
1408 const struct acpi_device_id
*id
;
1410 id
= acpi_match_device(dev
->driver
->acpi_match_table
, dev
);
1415 *data
= (int) id
->driver_data
;
1417 return dev_name(dev
);
1420 static int bmc150_accel_gpio_probe(struct i2c_client
*client
,
1421 struct bmc150_accel_data
*data
)
1424 struct gpio_desc
*gpio
;
1432 /* data ready gpio interrupt pin */
1433 gpio
= devm_gpiod_get_index(dev
, BMC150_ACCEL_GPIO_NAME
, 0, GPIOD_IN
);
1435 dev_err(dev
, "Failed: gpio get index\n");
1436 return PTR_ERR(gpio
);
1439 ret
= gpiod_to_irq(gpio
);
1441 dev_dbg(dev
, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio
), ret
);
1446 static const struct {
1449 int (*setup
)(struct bmc150_accel_trigger
*t
, bool state
);
1450 } bmc150_accel_triggers
[BMC150_ACCEL_TRIGGERS
] = {
1457 .name
= "%s-any-motion-dev%d",
1458 .setup
= bmc150_accel_any_motion_setup
,
1462 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data
*data
,
1467 for (i
= from
; i
>= 0; i
++) {
1468 if (data
->triggers
[i
].indio_trig
) {
1469 iio_trigger_unregister(data
->triggers
[i
].indio_trig
);
1470 data
->triggers
[i
].indio_trig
= NULL
;
1475 static int bmc150_accel_triggers_setup(struct iio_dev
*indio_dev
,
1476 struct bmc150_accel_data
*data
)
1480 for (i
= 0; i
< BMC150_ACCEL_TRIGGERS
; i
++) {
1481 struct bmc150_accel_trigger
*t
= &data
->triggers
[i
];
1483 t
->indio_trig
= devm_iio_trigger_alloc(&data
->client
->dev
,
1484 bmc150_accel_triggers
[i
].name
,
1487 if (!t
->indio_trig
) {
1492 t
->indio_trig
->dev
.parent
= &data
->client
->dev
;
1493 t
->indio_trig
->ops
= &bmc150_accel_trigger_ops
;
1494 t
->intr
= bmc150_accel_triggers
[i
].intr
;
1496 t
->setup
= bmc150_accel_triggers
[i
].setup
;
1497 iio_trigger_set_drvdata(t
->indio_trig
, t
);
1499 ret
= iio_trigger_register(t
->indio_trig
);
1505 bmc150_accel_unregister_triggers(data
, i
- 1);
1510 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1511 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1512 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1514 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data
*data
)
1516 u8 reg
= BMC150_ACCEL_REG_FIFO_CONFIG1
;
1519 ret
= i2c_smbus_write_byte_data(data
->client
, reg
, data
->fifo_mode
);
1521 dev_err(&data
->client
->dev
, "Error writing reg_fifo_config1\n");
1525 if (!data
->fifo_mode
)
1528 ret
= i2c_smbus_write_byte_data(data
->client
,
1529 BMC150_ACCEL_REG_FIFO_CONFIG0
,
1532 dev_err(&data
->client
->dev
, "Error writing reg_fifo_config0\n");
1537 static int bmc150_accel_buffer_preenable(struct iio_dev
*indio_dev
)
1539 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1541 return bmc150_accel_set_power_state(data
, true);
1544 static int bmc150_accel_buffer_postenable(struct iio_dev
*indio_dev
)
1546 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1549 if (indio_dev
->currentmode
== INDIO_BUFFER_TRIGGERED
)
1550 return iio_triggered_buffer_postenable(indio_dev
);
1552 mutex_lock(&data
->mutex
);
1554 if (!data
->watermark
)
1557 ret
= bmc150_accel_set_interrupt(data
, BMC150_ACCEL_INT_WATERMARK
,
1562 data
->fifo_mode
= BMC150_ACCEL_FIFO_MODE_FIFO
;
1564 ret
= bmc150_accel_fifo_set_mode(data
);
1566 data
->fifo_mode
= 0;
1567 bmc150_accel_set_interrupt(data
, BMC150_ACCEL_INT_WATERMARK
,
1572 mutex_unlock(&data
->mutex
);
1577 static int bmc150_accel_buffer_predisable(struct iio_dev
*indio_dev
)
1579 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1581 if (indio_dev
->currentmode
== INDIO_BUFFER_TRIGGERED
)
1582 return iio_triggered_buffer_predisable(indio_dev
);
1584 mutex_lock(&data
->mutex
);
1586 if (!data
->fifo_mode
)
1589 bmc150_accel_set_interrupt(data
, BMC150_ACCEL_INT_WATERMARK
, false);
1590 __bmc150_accel_fifo_flush(indio_dev
, BMC150_ACCEL_FIFO_LENGTH
, false);
1591 data
->fifo_mode
= 0;
1592 bmc150_accel_fifo_set_mode(data
);
1595 mutex_unlock(&data
->mutex
);
1600 static int bmc150_accel_buffer_postdisable(struct iio_dev
*indio_dev
)
1602 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1604 return bmc150_accel_set_power_state(data
, false);
1607 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops
= {
1608 .preenable
= bmc150_accel_buffer_preenable
,
1609 .postenable
= bmc150_accel_buffer_postenable
,
1610 .predisable
= bmc150_accel_buffer_predisable
,
1611 .postdisable
= bmc150_accel_buffer_postdisable
,
1614 static int bmc150_accel_probe(struct i2c_client
*client
,
1615 const struct i2c_device_id
*id
)
1617 struct bmc150_accel_data
*data
;
1618 struct iio_dev
*indio_dev
;
1620 const char *name
= NULL
;
1623 indio_dev
= devm_iio_device_alloc(&client
->dev
, sizeof(*data
));
1627 data
= iio_priv(indio_dev
);
1628 i2c_set_clientdata(client
, indio_dev
);
1629 data
->client
= client
;
1633 chip_id
= id
->driver_data
;
1636 if (ACPI_HANDLE(&client
->dev
))
1637 name
= bmc150_accel_match_acpi_device(&client
->dev
, &chip_id
);
1639 data
->chip_info
= &bmc150_accel_chip_info_tbl
[chip_id
];
1641 ret
= bmc150_accel_chip_init(data
);
1645 mutex_init(&data
->mutex
);
1647 indio_dev
->dev
.parent
= &client
->dev
;
1648 indio_dev
->channels
= data
->chip_info
->channels
;
1649 indio_dev
->num_channels
= data
->chip_info
->num_channels
;
1650 indio_dev
->name
= name
;
1651 indio_dev
->modes
= INDIO_DIRECT_MODE
;
1652 indio_dev
->info
= &bmc150_accel_info
;
1654 ret
= iio_triggered_buffer_setup(indio_dev
,
1655 &iio_pollfunc_store_time
,
1656 bmc150_accel_trigger_handler
,
1657 &bmc150_accel_buffer_ops
);
1659 dev_err(&client
->dev
, "Failed: iio triggered buffer setup\n");
1663 if (client
->irq
< 0)
1664 client
->irq
= bmc150_accel_gpio_probe(client
, data
);
1666 if (client
->irq
>= 0) {
1667 ret
= devm_request_threaded_irq(
1668 &client
->dev
, client
->irq
,
1669 bmc150_accel_irq_handler
,
1670 bmc150_accel_irq_thread_handler
,
1671 IRQF_TRIGGER_RISING
,
1672 BMC150_ACCEL_IRQ_NAME
,
1675 goto err_buffer_cleanup
;
1678 * Set latched mode interrupt. While certain interrupts are
1679 * non-latched regardless of this settings (e.g. new data) we
1680 * want to use latch mode when we can to prevent interrupt
1683 ret
= i2c_smbus_write_byte_data(data
->client
,
1684 BMC150_ACCEL_REG_INT_RST_LATCH
,
1685 BMC150_ACCEL_INT_MODE_LATCH_RESET
);
1687 dev_err(&data
->client
->dev
, "Error writing reg_int_rst_latch\n");
1688 goto err_buffer_cleanup
;
1691 bmc150_accel_interrupts_setup(indio_dev
, data
);
1693 ret
= bmc150_accel_triggers_setup(indio_dev
, data
);
1695 goto err_buffer_cleanup
;
1697 if (i2c_check_functionality(client
->adapter
, I2C_FUNC_I2C
) ||
1698 i2c_check_functionality(client
->adapter
,
1699 I2C_FUNC_SMBUS_READ_I2C_BLOCK
)) {
1700 indio_dev
->modes
|= INDIO_BUFFER_SOFTWARE
;
1701 indio_dev
->info
= &bmc150_accel_info_fifo
;
1702 indio_dev
->buffer
->attrs
= bmc150_accel_fifo_attributes
;
1706 ret
= iio_device_register(indio_dev
);
1708 dev_err(&client
->dev
, "Unable to register iio device\n");
1709 goto err_trigger_unregister
;
1712 ret
= pm_runtime_set_active(&client
->dev
);
1714 goto err_iio_unregister
;
1716 pm_runtime_enable(&client
->dev
);
1717 pm_runtime_set_autosuspend_delay(&client
->dev
,
1718 BMC150_AUTO_SUSPEND_DELAY_MS
);
1719 pm_runtime_use_autosuspend(&client
->dev
);
1724 iio_device_unregister(indio_dev
);
1725 err_trigger_unregister
:
1726 bmc150_accel_unregister_triggers(data
, BMC150_ACCEL_TRIGGERS
- 1);
1728 iio_triggered_buffer_cleanup(indio_dev
);
1733 static int bmc150_accel_remove(struct i2c_client
*client
)
1735 struct iio_dev
*indio_dev
= i2c_get_clientdata(client
);
1736 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1738 pm_runtime_disable(&client
->dev
);
1739 pm_runtime_set_suspended(&client
->dev
);
1740 pm_runtime_put_noidle(&client
->dev
);
1742 iio_device_unregister(indio_dev
);
1744 bmc150_accel_unregister_triggers(data
, BMC150_ACCEL_TRIGGERS
- 1);
1746 iio_triggered_buffer_cleanup(indio_dev
);
1748 mutex_lock(&data
->mutex
);
1749 bmc150_accel_set_mode(data
, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND
, 0);
1750 mutex_unlock(&data
->mutex
);
1755 #ifdef CONFIG_PM_SLEEP
1756 static int bmc150_accel_suspend(struct device
*dev
)
1758 struct iio_dev
*indio_dev
= i2c_get_clientdata(to_i2c_client(dev
));
1759 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1761 mutex_lock(&data
->mutex
);
1762 bmc150_accel_set_mode(data
, BMC150_ACCEL_SLEEP_MODE_SUSPEND
, 0);
1763 mutex_unlock(&data
->mutex
);
1768 static int bmc150_accel_resume(struct device
*dev
)
1770 struct iio_dev
*indio_dev
= i2c_get_clientdata(to_i2c_client(dev
));
1771 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1773 mutex_lock(&data
->mutex
);
1774 if (atomic_read(&data
->active_intr
))
1775 bmc150_accel_set_mode(data
, BMC150_ACCEL_SLEEP_MODE_NORMAL
, 0);
1776 bmc150_accel_fifo_set_mode(data
);
1777 mutex_unlock(&data
->mutex
);
1784 static int bmc150_accel_runtime_suspend(struct device
*dev
)
1786 struct iio_dev
*indio_dev
= i2c_get_clientdata(to_i2c_client(dev
));
1787 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1790 dev_dbg(&data
->client
->dev
, __func__
);
1791 ret
= bmc150_accel_set_mode(data
, BMC150_ACCEL_SLEEP_MODE_SUSPEND
, 0);
1798 static int bmc150_accel_runtime_resume(struct device
*dev
)
1800 struct iio_dev
*indio_dev
= i2c_get_clientdata(to_i2c_client(dev
));
1801 struct bmc150_accel_data
*data
= iio_priv(indio_dev
);
1805 dev_dbg(&data
->client
->dev
, __func__
);
1807 ret
= bmc150_accel_set_mode(data
, BMC150_ACCEL_SLEEP_MODE_NORMAL
, 0);
1810 ret
= bmc150_accel_fifo_set_mode(data
);
1814 sleep_val
= bmc150_accel_get_startup_times(data
);
1816 usleep_range(sleep_val
* 1000, 20000);
1818 msleep_interruptible(sleep_val
);
1824 static const struct dev_pm_ops bmc150_accel_pm_ops
= {
1825 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend
, bmc150_accel_resume
)
1826 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend
,
1827 bmc150_accel_runtime_resume
, NULL
)
1830 static const struct acpi_device_id bmc150_accel_acpi_match
[] = {
1831 {"BSBA0150", bmc150
},
1832 {"BMC150A", bmc150
},
1833 {"BMI055A", bmi055
},
1834 {"BMA0255", bma255
},
1835 {"BMA250E", bma250e
},
1836 {"BMA222E", bma222e
},
1837 {"BMA0280", bma280
},
1840 MODULE_DEVICE_TABLE(acpi
, bmc150_accel_acpi_match
);
1842 static const struct i2c_device_id bmc150_accel_id
[] = {
1843 {"bmc150_accel", bmc150
},
1844 {"bmi055_accel", bmi055
},
1846 {"bma250e", bma250e
},
1847 {"bma222e", bma222e
},
1852 MODULE_DEVICE_TABLE(i2c
, bmc150_accel_id
);
1854 static struct i2c_driver bmc150_accel_driver
= {
1856 .name
= BMC150_ACCEL_DRV_NAME
,
1857 .acpi_match_table
= ACPI_PTR(bmc150_accel_acpi_match
),
1858 .pm
= &bmc150_accel_pm_ops
,
1860 .probe
= bmc150_accel_probe
,
1861 .remove
= bmc150_accel_remove
,
1862 .id_table
= bmc150_accel_id
,
1864 module_i2c_driver(bmc150_accel_driver
);
1866 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1867 MODULE_LICENSE("GPL v2");
1868 MODULE_DESCRIPTION("BMC150 accelerometer driver");