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Merge tag 'samsung-fixes-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk...
[deliverable/linux.git] / drivers / iio / accel / mma8452.c
1 /*
2 * mma8452.c - Support for following Freescale 3-axis accelerometers:
3 *
4 * MMA8451Q (14 bit)
5 * MMA8452Q (12 bit)
6 * MMA8453Q (10 bit)
7 * MMA8652FC (12 bit)
8 * MMA8653FC (10 bit)
9 * FXLS8471Q (14 bit)
10 *
11 * Copyright 2015 Martin Kepplinger <martin.kepplinger@theobroma-systems.com>
12 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
13 *
14 * This file is subject to the terms and conditions of version 2 of
15 * the GNU General Public License. See the file COPYING in the main
16 * directory of this archive for more details.
17 *
18 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
19 *
20 * TODO: orientation events
21 */
22
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/iio/iio.h>
26 #include <linux/iio/sysfs.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/trigger.h>
29 #include <linux/iio/trigger_consumer.h>
30 #include <linux/iio/triggered_buffer.h>
31 #include <linux/iio/events.h>
32 #include <linux/delay.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/pm_runtime.h>
36
37 #define MMA8452_STATUS 0x00
38 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
39 #define MMA8452_OUT_X 0x01 /* MSB first */
40 #define MMA8452_OUT_Y 0x03
41 #define MMA8452_OUT_Z 0x05
42 #define MMA8452_INT_SRC 0x0c
43 #define MMA8452_WHO_AM_I 0x0d
44 #define MMA8452_DATA_CFG 0x0e
45 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
46 #define MMA8452_DATA_CFG_FS_2G 0
47 #define MMA8452_DATA_CFG_FS_4G 1
48 #define MMA8452_DATA_CFG_FS_8G 2
49 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
50 #define MMA8452_HP_FILTER_CUTOFF 0x0f
51 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
52 #define MMA8452_FF_MT_CFG 0x15
53 #define MMA8452_FF_MT_CFG_OAE BIT(6)
54 #define MMA8452_FF_MT_CFG_ELE BIT(7)
55 #define MMA8452_FF_MT_SRC 0x16
56 #define MMA8452_FF_MT_SRC_XHE BIT(1)
57 #define MMA8452_FF_MT_SRC_YHE BIT(3)
58 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
59 #define MMA8452_FF_MT_THS 0x17
60 #define MMA8452_FF_MT_THS_MASK 0x7f
61 #define MMA8452_FF_MT_COUNT 0x18
62 #define MMA8452_TRANSIENT_CFG 0x1d
63 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
64 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
65 #define MMA8452_TRANSIENT_SRC 0x1e
66 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
67 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
68 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
69 #define MMA8452_TRANSIENT_THS 0x1f
70 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
71 #define MMA8452_TRANSIENT_COUNT 0x20
72 #define MMA8452_CTRL_REG1 0x2a
73 #define MMA8452_CTRL_ACTIVE BIT(0)
74 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
75 #define MMA8452_CTRL_DR_SHIFT 3
76 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
77 #define MMA8452_CTRL_REG2 0x2b
78 #define MMA8452_CTRL_REG2_RST BIT(6)
79 #define MMA8452_CTRL_REG4 0x2d
80 #define MMA8452_CTRL_REG5 0x2e
81 #define MMA8452_OFF_X 0x2f
82 #define MMA8452_OFF_Y 0x30
83 #define MMA8452_OFF_Z 0x31
84
85 #define MMA8452_MAX_REG 0x31
86
87 #define MMA8452_INT_DRDY BIT(0)
88 #define MMA8452_INT_FF_MT BIT(2)
89 #define MMA8452_INT_TRANS BIT(5)
90
91 #define MMA8451_DEVICE_ID 0x1a
92 #define MMA8452_DEVICE_ID 0x2a
93 #define MMA8453_DEVICE_ID 0x3a
94 #define MMA8652_DEVICE_ID 0x4a
95 #define MMA8653_DEVICE_ID 0x5a
96 #define FXLS8471_DEVICE_ID 0x6a
97
98 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
99
100 struct mma8452_data {
101 struct i2c_client *client;
102 struct mutex lock;
103 u8 ctrl_reg1;
104 u8 data_cfg;
105 const struct mma_chip_info *chip_info;
106 };
107
108 /**
109 * struct mma_chip_info - chip specific data for Freescale's accelerometers
110 * @chip_id: WHO_AM_I register's value
111 * @channels: struct iio_chan_spec matching the device's
112 * capabilities
113 * @num_channels: number of channels
114 * @mma_scales: scale factors for converting register values
115 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
116 * per mode: m/s^2 and micro m/s^2
117 * @ev_cfg: event config register address
118 * @ev_cfg_ele: latch bit in event config register
119 * @ev_cfg_chan_shift: number of the bit to enable events in X
120 * direction; in event config register
121 * @ev_src: event source register address
122 * @ev_src_xe: bit in event source register that indicates
123 * an event in X direction
124 * @ev_src_ye: bit in event source register that indicates
125 * an event in Y direction
126 * @ev_src_ze: bit in event source register that indicates
127 * an event in Z direction
128 * @ev_ths: event threshold register address
129 * @ev_ths_mask: mask for the threshold value
130 * @ev_count: event count (period) register address
131 *
132 * Since not all chips supported by the driver support comparing high pass
133 * filtered data for events (interrupts), different interrupt sources are
134 * used for different chips and the relevant registers are included here.
135 */
136 struct mma_chip_info {
137 u8 chip_id;
138 const struct iio_chan_spec *channels;
139 int num_channels;
140 const int mma_scales[3][2];
141 u8 ev_cfg;
142 u8 ev_cfg_ele;
143 u8 ev_cfg_chan_shift;
144 u8 ev_src;
145 u8 ev_src_xe;
146 u8 ev_src_ye;
147 u8 ev_src_ze;
148 u8 ev_ths;
149 u8 ev_ths_mask;
150 u8 ev_count;
151 };
152
153 enum {
154 idx_x,
155 idx_y,
156 idx_z,
157 idx_ts,
158 };
159
160 static int mma8452_drdy(struct mma8452_data *data)
161 {
162 int tries = 150;
163
164 while (tries-- > 0) {
165 int ret = i2c_smbus_read_byte_data(data->client,
166 MMA8452_STATUS);
167 if (ret < 0)
168 return ret;
169 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
170 return 0;
171
172 msleep(20);
173 }
174
175 dev_err(&data->client->dev, "data not ready\n");
176
177 return -EIO;
178 }
179
180 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
181 {
182 #ifdef CONFIG_PM
183 int ret;
184
185 if (on) {
186 ret = pm_runtime_get_sync(&client->dev);
187 } else {
188 pm_runtime_mark_last_busy(&client->dev);
189 ret = pm_runtime_put_autosuspend(&client->dev);
190 }
191
192 if (ret < 0) {
193 dev_err(&client->dev,
194 "failed to change power state to %d\n", on);
195 if (on)
196 pm_runtime_put_noidle(&client->dev);
197
198 return ret;
199 }
200 #endif
201
202 return 0;
203 }
204
205 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
206 {
207 int ret = mma8452_drdy(data);
208
209 if (ret < 0)
210 return ret;
211
212 ret = mma8452_set_runtime_pm_state(data->client, true);
213 if (ret)
214 return ret;
215
216 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
217 3 * sizeof(__be16), (u8 *)buf);
218
219 ret = mma8452_set_runtime_pm_state(data->client, false);
220
221 return ret;
222 }
223
224 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
225 int n)
226 {
227 size_t len = 0;
228
229 while (n-- > 0)
230 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
231 vals[n][0], vals[n][1]);
232
233 /* replace trailing space by newline */
234 buf[len - 1] = '\n';
235
236 return len;
237 }
238
239 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
240 int val, int val2)
241 {
242 while (n-- > 0)
243 if (val == vals[n][0] && val2 == vals[n][1])
244 return n;
245
246 return -EINVAL;
247 }
248
249 static int mma8452_get_odr_index(struct mma8452_data *data)
250 {
251 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
252 MMA8452_CTRL_DR_SHIFT;
253 }
254
255 static const int mma8452_samp_freq[8][2] = {
256 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
257 {6, 250000}, {1, 560000}
258 };
259
260 /* Datasheet table 35 (step time vs sample frequency) */
261 static const int mma8452_transient_time_step_us[8] = {
262 1250,
263 2500,
264 5000,
265 10000,
266 20000,
267 20000,
268 20000,
269 20000
270 };
271
272 /* Datasheet table 18 (normal mode) */
273 static const int mma8452_hp_filter_cutoff[8][4][2] = {
274 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
275 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
276 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
277 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
278 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
279 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
280 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
281 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
282 };
283
284 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
285 struct device_attribute *attr,
286 char *buf)
287 {
288 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
289 ARRAY_SIZE(mma8452_samp_freq));
290 }
291
292 static ssize_t mma8452_show_scale_avail(struct device *dev,
293 struct device_attribute *attr,
294 char *buf)
295 {
296 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
297 to_i2c_client(dev)));
298
299 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
300 ARRAY_SIZE(data->chip_info->mma_scales));
301 }
302
303 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
304 struct device_attribute *attr,
305 char *buf)
306 {
307 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
308 struct mma8452_data *data = iio_priv(indio_dev);
309 int i = mma8452_get_odr_index(data);
310
311 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
312 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
313 }
314
315 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
316 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
317 mma8452_show_scale_avail, NULL, 0);
318 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
319 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
320
321 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
322 int val, int val2)
323 {
324 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
325 ARRAY_SIZE(mma8452_samp_freq),
326 val, val2);
327 }
328
329 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
330 {
331 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
332 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
333 }
334
335 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
336 int val, int val2)
337 {
338 int i = mma8452_get_odr_index(data);
339
340 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
341 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2);
342 }
343
344 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
345 {
346 int i, ret;
347
348 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
349 if (ret < 0)
350 return ret;
351
352 i = mma8452_get_odr_index(data);
353 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
354 *hz = mma8452_hp_filter_cutoff[i][ret][0];
355 *uHz = mma8452_hp_filter_cutoff[i][ret][1];
356
357 return 0;
358 }
359
360 static int mma8452_read_raw(struct iio_dev *indio_dev,
361 struct iio_chan_spec const *chan,
362 int *val, int *val2, long mask)
363 {
364 struct mma8452_data *data = iio_priv(indio_dev);
365 __be16 buffer[3];
366 int i, ret;
367
368 switch (mask) {
369 case IIO_CHAN_INFO_RAW:
370 if (iio_buffer_enabled(indio_dev))
371 return -EBUSY;
372
373 mutex_lock(&data->lock);
374 ret = mma8452_read(data, buffer);
375 mutex_unlock(&data->lock);
376 if (ret < 0)
377 return ret;
378
379 *val = sign_extend32(be16_to_cpu(
380 buffer[chan->scan_index]) >> chan->scan_type.shift,
381 chan->scan_type.realbits - 1);
382
383 return IIO_VAL_INT;
384 case IIO_CHAN_INFO_SCALE:
385 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
386 *val = data->chip_info->mma_scales[i][0];
387 *val2 = data->chip_info->mma_scales[i][1];
388
389 return IIO_VAL_INT_PLUS_MICRO;
390 case IIO_CHAN_INFO_SAMP_FREQ:
391 i = mma8452_get_odr_index(data);
392 *val = mma8452_samp_freq[i][0];
393 *val2 = mma8452_samp_freq[i][1];
394
395 return IIO_VAL_INT_PLUS_MICRO;
396 case IIO_CHAN_INFO_CALIBBIAS:
397 ret = i2c_smbus_read_byte_data(data->client,
398 MMA8452_OFF_X +
399 chan->scan_index);
400 if (ret < 0)
401 return ret;
402
403 *val = sign_extend32(ret, 7);
404
405 return IIO_VAL_INT;
406 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
407 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
408 ret = mma8452_read_hp_filter(data, val, val2);
409 if (ret < 0)
410 return ret;
411 } else {
412 *val = 0;
413 *val2 = 0;
414 }
415
416 return IIO_VAL_INT_PLUS_MICRO;
417 }
418
419 return -EINVAL;
420 }
421
422 static int mma8452_standby(struct mma8452_data *data)
423 {
424 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
425 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
426 }
427
428 static int mma8452_active(struct mma8452_data *data)
429 {
430 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
431 data->ctrl_reg1);
432 }
433
434 /* returns >0 if active, 0 if in standby and <0 on error */
435 static int mma8452_is_active(struct mma8452_data *data)
436 {
437 int reg;
438
439 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
440 if (reg < 0)
441 return reg;
442
443 return reg & MMA8452_CTRL_ACTIVE;
444 }
445
446 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
447 {
448 int ret;
449 int is_active;
450
451 mutex_lock(&data->lock);
452
453 is_active = mma8452_is_active(data);
454 if (is_active < 0) {
455 ret = is_active;
456 goto fail;
457 }
458
459 /* config can only be changed when in standby */
460 if (is_active > 0) {
461 ret = mma8452_standby(data);
462 if (ret < 0)
463 goto fail;
464 }
465
466 ret = i2c_smbus_write_byte_data(data->client, reg, val);
467 if (ret < 0)
468 goto fail;
469
470 if (is_active > 0) {
471 ret = mma8452_active(data);
472 if (ret < 0)
473 goto fail;
474 }
475
476 ret = 0;
477 fail:
478 mutex_unlock(&data->lock);
479
480 return ret;
481 }
482
483 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
484 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
485 {
486 int val;
487 const struct mma_chip_info *chip = data->chip_info;
488
489 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
490 if (val < 0)
491 return val;
492
493 return !(val & MMA8452_FF_MT_CFG_OAE);
494 }
495
496 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
497 {
498 int val;
499 const struct mma_chip_info *chip = data->chip_info;
500
501 if ((state && mma8452_freefall_mode_enabled(data)) ||
502 (!state && !(mma8452_freefall_mode_enabled(data))))
503 return 0;
504
505 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
506 if (val < 0)
507 return val;
508
509 if (state) {
510 val |= BIT(idx_x + chip->ev_cfg_chan_shift);
511 val |= BIT(idx_y + chip->ev_cfg_chan_shift);
512 val |= BIT(idx_z + chip->ev_cfg_chan_shift);
513 val &= ~MMA8452_FF_MT_CFG_OAE;
514 } else {
515 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
516 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
517 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
518 val |= MMA8452_FF_MT_CFG_OAE;
519 }
520
521 val = mma8452_change_config(data, chip->ev_cfg, val);
522 if (val)
523 return val;
524
525 return 0;
526 }
527
528 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
529 int val, int val2)
530 {
531 int i, reg;
532
533 i = mma8452_get_hp_filter_index(data, val, val2);
534 if (i < 0)
535 return i;
536
537 reg = i2c_smbus_read_byte_data(data->client,
538 MMA8452_HP_FILTER_CUTOFF);
539 if (reg < 0)
540 return reg;
541
542 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
543 reg |= i;
544
545 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
546 }
547
548 static int mma8452_write_raw(struct iio_dev *indio_dev,
549 struct iio_chan_spec const *chan,
550 int val, int val2, long mask)
551 {
552 struct mma8452_data *data = iio_priv(indio_dev);
553 int i, ret;
554
555 if (iio_buffer_enabled(indio_dev))
556 return -EBUSY;
557
558 switch (mask) {
559 case IIO_CHAN_INFO_SAMP_FREQ:
560 i = mma8452_get_samp_freq_index(data, val, val2);
561 if (i < 0)
562 return i;
563
564 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
565 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
566
567 return mma8452_change_config(data, MMA8452_CTRL_REG1,
568 data->ctrl_reg1);
569 case IIO_CHAN_INFO_SCALE:
570 i = mma8452_get_scale_index(data, val, val2);
571 if (i < 0)
572 return i;
573
574 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
575 data->data_cfg |= i;
576
577 return mma8452_change_config(data, MMA8452_DATA_CFG,
578 data->data_cfg);
579 case IIO_CHAN_INFO_CALIBBIAS:
580 if (val < -128 || val > 127)
581 return -EINVAL;
582
583 return mma8452_change_config(data,
584 MMA8452_OFF_X + chan->scan_index,
585 val);
586
587 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
588 if (val == 0 && val2 == 0) {
589 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
590 } else {
591 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
592 ret = mma8452_set_hp_filter_frequency(data, val, val2);
593 if (ret < 0)
594 return ret;
595 }
596
597 return mma8452_change_config(data, MMA8452_DATA_CFG,
598 data->data_cfg);
599
600 default:
601 return -EINVAL;
602 }
603 }
604
605 static int mma8452_read_thresh(struct iio_dev *indio_dev,
606 const struct iio_chan_spec *chan,
607 enum iio_event_type type,
608 enum iio_event_direction dir,
609 enum iio_event_info info,
610 int *val, int *val2)
611 {
612 struct mma8452_data *data = iio_priv(indio_dev);
613 int ret, us;
614
615 switch (info) {
616 case IIO_EV_INFO_VALUE:
617 ret = i2c_smbus_read_byte_data(data->client,
618 data->chip_info->ev_ths);
619 if (ret < 0)
620 return ret;
621
622 *val = ret & data->chip_info->ev_ths_mask;
623
624 return IIO_VAL_INT;
625
626 case IIO_EV_INFO_PERIOD:
627 ret = i2c_smbus_read_byte_data(data->client,
628 data->chip_info->ev_count);
629 if (ret < 0)
630 return ret;
631
632 us = ret * mma8452_transient_time_step_us[
633 mma8452_get_odr_index(data)];
634 *val = us / USEC_PER_SEC;
635 *val2 = us % USEC_PER_SEC;
636
637 return IIO_VAL_INT_PLUS_MICRO;
638
639 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
640 ret = i2c_smbus_read_byte_data(data->client,
641 MMA8452_TRANSIENT_CFG);
642 if (ret < 0)
643 return ret;
644
645 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
646 *val = 0;
647 *val2 = 0;
648 } else {
649 ret = mma8452_read_hp_filter(data, val, val2);
650 if (ret < 0)
651 return ret;
652 }
653
654 return IIO_VAL_INT_PLUS_MICRO;
655
656 default:
657 return -EINVAL;
658 }
659 }
660
661 static int mma8452_write_thresh(struct iio_dev *indio_dev,
662 const struct iio_chan_spec *chan,
663 enum iio_event_type type,
664 enum iio_event_direction dir,
665 enum iio_event_info info,
666 int val, int val2)
667 {
668 struct mma8452_data *data = iio_priv(indio_dev);
669 int ret, reg, steps;
670
671 switch (info) {
672 case IIO_EV_INFO_VALUE:
673 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
674 return -EINVAL;
675
676 return mma8452_change_config(data, data->chip_info->ev_ths,
677 val);
678
679 case IIO_EV_INFO_PERIOD:
680 steps = (val * USEC_PER_SEC + val2) /
681 mma8452_transient_time_step_us[
682 mma8452_get_odr_index(data)];
683
684 if (steps < 0 || steps > 0xff)
685 return -EINVAL;
686
687 return mma8452_change_config(data, data->chip_info->ev_count,
688 steps);
689
690 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
691 reg = i2c_smbus_read_byte_data(data->client,
692 MMA8452_TRANSIENT_CFG);
693 if (reg < 0)
694 return reg;
695
696 if (val == 0 && val2 == 0) {
697 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
698 } else {
699 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
700 ret = mma8452_set_hp_filter_frequency(data, val, val2);
701 if (ret < 0)
702 return ret;
703 }
704
705 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
706
707 default:
708 return -EINVAL;
709 }
710 }
711
712 static int mma8452_read_event_config(struct iio_dev *indio_dev,
713 const struct iio_chan_spec *chan,
714 enum iio_event_type type,
715 enum iio_event_direction dir)
716 {
717 struct mma8452_data *data = iio_priv(indio_dev);
718 const struct mma_chip_info *chip = data->chip_info;
719 int ret;
720
721 switch (dir) {
722 case IIO_EV_DIR_FALLING:
723 return mma8452_freefall_mode_enabled(data);
724 case IIO_EV_DIR_RISING:
725 if (mma8452_freefall_mode_enabled(data))
726 return 0;
727
728 ret = i2c_smbus_read_byte_data(data->client,
729 data->chip_info->ev_cfg);
730 if (ret < 0)
731 return ret;
732
733 return !!(ret & BIT(chan->scan_index +
734 chip->ev_cfg_chan_shift));
735 default:
736 return -EINVAL;
737 }
738 }
739
740 static int mma8452_write_event_config(struct iio_dev *indio_dev,
741 const struct iio_chan_spec *chan,
742 enum iio_event_type type,
743 enum iio_event_direction dir,
744 int state)
745 {
746 struct mma8452_data *data = iio_priv(indio_dev);
747 const struct mma_chip_info *chip = data->chip_info;
748 int val, ret;
749
750 ret = mma8452_set_runtime_pm_state(data->client, state);
751 if (ret)
752 return ret;
753
754 switch (dir) {
755 case IIO_EV_DIR_FALLING:
756 return mma8452_set_freefall_mode(data, state);
757 case IIO_EV_DIR_RISING:
758 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
759 if (val < 0)
760 return val;
761
762 if (state) {
763 if (mma8452_freefall_mode_enabled(data)) {
764 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
765 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
766 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
767 val |= MMA8452_FF_MT_CFG_OAE;
768 }
769 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
770 } else {
771 if (mma8452_freefall_mode_enabled(data))
772 return 0;
773
774 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
775 }
776
777 val |= chip->ev_cfg_ele;
778
779 return mma8452_change_config(data, chip->ev_cfg, val);
780 default:
781 return -EINVAL;
782 }
783 }
784
785 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
786 {
787 struct mma8452_data *data = iio_priv(indio_dev);
788 s64 ts = iio_get_time_ns();
789 int src;
790
791 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
792 if (src < 0)
793 return;
794
795 if (mma8452_freefall_mode_enabled(data)) {
796 iio_push_event(indio_dev,
797 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
798 IIO_MOD_X_AND_Y_AND_Z,
799 IIO_EV_TYPE_MAG,
800 IIO_EV_DIR_FALLING),
801 ts);
802 return;
803 }
804
805 if (src & data->chip_info->ev_src_xe)
806 iio_push_event(indio_dev,
807 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
808 IIO_EV_TYPE_MAG,
809 IIO_EV_DIR_RISING),
810 ts);
811
812 if (src & data->chip_info->ev_src_ye)
813 iio_push_event(indio_dev,
814 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
815 IIO_EV_TYPE_MAG,
816 IIO_EV_DIR_RISING),
817 ts);
818
819 if (src & data->chip_info->ev_src_ze)
820 iio_push_event(indio_dev,
821 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
822 IIO_EV_TYPE_MAG,
823 IIO_EV_DIR_RISING),
824 ts);
825 }
826
827 static irqreturn_t mma8452_interrupt(int irq, void *p)
828 {
829 struct iio_dev *indio_dev = p;
830 struct mma8452_data *data = iio_priv(indio_dev);
831 const struct mma_chip_info *chip = data->chip_info;
832 int ret = IRQ_NONE;
833 int src;
834
835 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
836 if (src < 0)
837 return IRQ_NONE;
838
839 if (src & MMA8452_INT_DRDY) {
840 iio_trigger_poll_chained(indio_dev->trig);
841 ret = IRQ_HANDLED;
842 }
843
844 if ((src & MMA8452_INT_TRANS &&
845 chip->ev_src == MMA8452_TRANSIENT_SRC) ||
846 (src & MMA8452_INT_FF_MT &&
847 chip->ev_src == MMA8452_FF_MT_SRC)) {
848 mma8452_transient_interrupt(indio_dev);
849 ret = IRQ_HANDLED;
850 }
851
852 return ret;
853 }
854
855 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
856 {
857 struct iio_poll_func *pf = p;
858 struct iio_dev *indio_dev = pf->indio_dev;
859 struct mma8452_data *data = iio_priv(indio_dev);
860 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
861 int ret;
862
863 ret = mma8452_read(data, (__be16 *)buffer);
864 if (ret < 0)
865 goto done;
866
867 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
868 iio_get_time_ns());
869
870 done:
871 iio_trigger_notify_done(indio_dev->trig);
872
873 return IRQ_HANDLED;
874 }
875
876 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
877 unsigned reg, unsigned writeval,
878 unsigned *readval)
879 {
880 int ret;
881 struct mma8452_data *data = iio_priv(indio_dev);
882
883 if (reg > MMA8452_MAX_REG)
884 return -EINVAL;
885
886 if (!readval)
887 return mma8452_change_config(data, reg, writeval);
888
889 ret = i2c_smbus_read_byte_data(data->client, reg);
890 if (ret < 0)
891 return ret;
892
893 *readval = ret;
894
895 return 0;
896 }
897
898 static const struct iio_event_spec mma8452_freefall_event[] = {
899 {
900 .type = IIO_EV_TYPE_MAG,
901 .dir = IIO_EV_DIR_FALLING,
902 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
903 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
904 BIT(IIO_EV_INFO_PERIOD) |
905 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
906 },
907 };
908
909 static const struct iio_event_spec mma8652_freefall_event[] = {
910 {
911 .type = IIO_EV_TYPE_MAG,
912 .dir = IIO_EV_DIR_FALLING,
913 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
914 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
915 BIT(IIO_EV_INFO_PERIOD)
916 },
917 };
918
919 static const struct iio_event_spec mma8452_transient_event[] = {
920 {
921 .type = IIO_EV_TYPE_MAG,
922 .dir = IIO_EV_DIR_RISING,
923 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
924 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
925 BIT(IIO_EV_INFO_PERIOD) |
926 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
927 },
928 };
929
930 static const struct iio_event_spec mma8452_motion_event[] = {
931 {
932 .type = IIO_EV_TYPE_MAG,
933 .dir = IIO_EV_DIR_RISING,
934 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
935 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
936 BIT(IIO_EV_INFO_PERIOD)
937 },
938 };
939
940 /*
941 * Threshold is configured in fixed 8G/127 steps regardless of
942 * currently selected scale for measurement.
943 */
944 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
945
946 static struct attribute *mma8452_event_attributes[] = {
947 &iio_const_attr_accel_transient_scale.dev_attr.attr,
948 NULL,
949 };
950
951 static struct attribute_group mma8452_event_attribute_group = {
952 .attrs = mma8452_event_attributes,
953 };
954
955 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
956 .type = IIO_ACCEL, \
957 .modified = 1, \
958 .channel2 = modifier, \
959 .scan_index = -1, \
960 .event_spec = mma8452_freefall_event, \
961 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
962 }
963
964 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
965 .type = IIO_ACCEL, \
966 .modified = 1, \
967 .channel2 = modifier, \
968 .scan_index = -1, \
969 .event_spec = mma8652_freefall_event, \
970 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
971 }
972
973 #define MMA8452_CHANNEL(axis, idx, bits) { \
974 .type = IIO_ACCEL, \
975 .modified = 1, \
976 .channel2 = IIO_MOD_##axis, \
977 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
978 BIT(IIO_CHAN_INFO_CALIBBIAS), \
979 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
980 BIT(IIO_CHAN_INFO_SCALE) | \
981 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
982 .scan_index = idx, \
983 .scan_type = { \
984 .sign = 's', \
985 .realbits = (bits), \
986 .storagebits = 16, \
987 .shift = 16 - (bits), \
988 .endianness = IIO_BE, \
989 }, \
990 .event_spec = mma8452_transient_event, \
991 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
992 }
993
994 #define MMA8652_CHANNEL(axis, idx, bits) { \
995 .type = IIO_ACCEL, \
996 .modified = 1, \
997 .channel2 = IIO_MOD_##axis, \
998 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
999 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1000 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1001 BIT(IIO_CHAN_INFO_SCALE), \
1002 .scan_index = idx, \
1003 .scan_type = { \
1004 .sign = 's', \
1005 .realbits = (bits), \
1006 .storagebits = 16, \
1007 .shift = 16 - (bits), \
1008 .endianness = IIO_BE, \
1009 }, \
1010 .event_spec = mma8452_motion_event, \
1011 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1012 }
1013
1014 static const struct iio_chan_spec mma8451_channels[] = {
1015 MMA8452_CHANNEL(X, idx_x, 14),
1016 MMA8452_CHANNEL(Y, idx_y, 14),
1017 MMA8452_CHANNEL(Z, idx_z, 14),
1018 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1019 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1020 };
1021
1022 static const struct iio_chan_spec mma8452_channels[] = {
1023 MMA8452_CHANNEL(X, idx_x, 12),
1024 MMA8452_CHANNEL(Y, idx_y, 12),
1025 MMA8452_CHANNEL(Z, idx_z, 12),
1026 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1027 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1028 };
1029
1030 static const struct iio_chan_spec mma8453_channels[] = {
1031 MMA8452_CHANNEL(X, idx_x, 10),
1032 MMA8452_CHANNEL(Y, idx_y, 10),
1033 MMA8452_CHANNEL(Z, idx_z, 10),
1034 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1035 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1036 };
1037
1038 static const struct iio_chan_spec mma8652_channels[] = {
1039 MMA8652_CHANNEL(X, idx_x, 12),
1040 MMA8652_CHANNEL(Y, idx_y, 12),
1041 MMA8652_CHANNEL(Z, idx_z, 12),
1042 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1043 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1044 };
1045
1046 static const struct iio_chan_spec mma8653_channels[] = {
1047 MMA8652_CHANNEL(X, idx_x, 10),
1048 MMA8652_CHANNEL(Y, idx_y, 10),
1049 MMA8652_CHANNEL(Z, idx_z, 10),
1050 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1051 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1052 };
1053
1054 enum {
1055 mma8451,
1056 mma8452,
1057 mma8453,
1058 mma8652,
1059 mma8653,
1060 fxls8471,
1061 };
1062
1063 static const struct mma_chip_info mma_chip_info_table[] = {
1064 [mma8451] = {
1065 .chip_id = MMA8451_DEVICE_ID,
1066 .channels = mma8451_channels,
1067 .num_channels = ARRAY_SIZE(mma8451_channels),
1068 /*
1069 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1070 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1071 * bit.
1072 * The userspace interface uses m/s^2 and we declare micro units
1073 * So scale factor for 12 bit here is given by:
1074 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1075 */
1076 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1077 .ev_cfg = MMA8452_TRANSIENT_CFG,
1078 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1079 .ev_cfg_chan_shift = 1,
1080 .ev_src = MMA8452_TRANSIENT_SRC,
1081 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1082 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1083 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1084 .ev_ths = MMA8452_TRANSIENT_THS,
1085 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1086 .ev_count = MMA8452_TRANSIENT_COUNT,
1087 },
1088 [mma8452] = {
1089 .chip_id = MMA8452_DEVICE_ID,
1090 .channels = mma8452_channels,
1091 .num_channels = ARRAY_SIZE(mma8452_channels),
1092 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1093 .ev_cfg = MMA8452_TRANSIENT_CFG,
1094 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1095 .ev_cfg_chan_shift = 1,
1096 .ev_src = MMA8452_TRANSIENT_SRC,
1097 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1098 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1099 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1100 .ev_ths = MMA8452_TRANSIENT_THS,
1101 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1102 .ev_count = MMA8452_TRANSIENT_COUNT,
1103 },
1104 [mma8453] = {
1105 .chip_id = MMA8453_DEVICE_ID,
1106 .channels = mma8453_channels,
1107 .num_channels = ARRAY_SIZE(mma8453_channels),
1108 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1109 .ev_cfg = MMA8452_TRANSIENT_CFG,
1110 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1111 .ev_cfg_chan_shift = 1,
1112 .ev_src = MMA8452_TRANSIENT_SRC,
1113 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1114 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1115 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1116 .ev_ths = MMA8452_TRANSIENT_THS,
1117 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1118 .ev_count = MMA8452_TRANSIENT_COUNT,
1119 },
1120 [mma8652] = {
1121 .chip_id = MMA8652_DEVICE_ID,
1122 .channels = mma8652_channels,
1123 .num_channels = ARRAY_SIZE(mma8652_channels),
1124 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1125 .ev_cfg = MMA8452_FF_MT_CFG,
1126 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1127 .ev_cfg_chan_shift = 3,
1128 .ev_src = MMA8452_FF_MT_SRC,
1129 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1130 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1131 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1132 .ev_ths = MMA8452_FF_MT_THS,
1133 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1134 .ev_count = MMA8452_FF_MT_COUNT,
1135 },
1136 [mma8653] = {
1137 .chip_id = MMA8653_DEVICE_ID,
1138 .channels = mma8653_channels,
1139 .num_channels = ARRAY_SIZE(mma8653_channels),
1140 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1141 .ev_cfg = MMA8452_FF_MT_CFG,
1142 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1143 .ev_cfg_chan_shift = 3,
1144 .ev_src = MMA8452_FF_MT_SRC,
1145 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1146 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1147 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1148 .ev_ths = MMA8452_FF_MT_THS,
1149 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1150 .ev_count = MMA8452_FF_MT_COUNT,
1151 },
1152 [fxls8471] = {
1153 .chip_id = FXLS8471_DEVICE_ID,
1154 .channels = mma8451_channels,
1155 .num_channels = ARRAY_SIZE(mma8451_channels),
1156 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1157 .ev_cfg = MMA8452_TRANSIENT_CFG,
1158 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1159 .ev_cfg_chan_shift = 1,
1160 .ev_src = MMA8452_TRANSIENT_SRC,
1161 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1162 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1163 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1164 .ev_ths = MMA8452_TRANSIENT_THS,
1165 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1166 .ev_count = MMA8452_TRANSIENT_COUNT,
1167 },
1168 };
1169
1170 static struct attribute *mma8452_attributes[] = {
1171 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1172 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1173 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1174 NULL
1175 };
1176
1177 static const struct attribute_group mma8452_group = {
1178 .attrs = mma8452_attributes,
1179 };
1180
1181 static const struct iio_info mma8452_info = {
1182 .attrs = &mma8452_group,
1183 .read_raw = &mma8452_read_raw,
1184 .write_raw = &mma8452_write_raw,
1185 .event_attrs = &mma8452_event_attribute_group,
1186 .read_event_value = &mma8452_read_thresh,
1187 .write_event_value = &mma8452_write_thresh,
1188 .read_event_config = &mma8452_read_event_config,
1189 .write_event_config = &mma8452_write_event_config,
1190 .debugfs_reg_access = &mma8452_reg_access_dbg,
1191 .driver_module = THIS_MODULE,
1192 };
1193
1194 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1195
1196 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1197 bool state)
1198 {
1199 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1200 struct mma8452_data *data = iio_priv(indio_dev);
1201 int reg, ret;
1202
1203 ret = mma8452_set_runtime_pm_state(data->client, state);
1204 if (ret)
1205 return ret;
1206
1207 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1208 if (reg < 0)
1209 return reg;
1210
1211 if (state)
1212 reg |= MMA8452_INT_DRDY;
1213 else
1214 reg &= ~MMA8452_INT_DRDY;
1215
1216 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1217 }
1218
1219 static int mma8452_validate_device(struct iio_trigger *trig,
1220 struct iio_dev *indio_dev)
1221 {
1222 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
1223
1224 if (indio != indio_dev)
1225 return -EINVAL;
1226
1227 return 0;
1228 }
1229
1230 static const struct iio_trigger_ops mma8452_trigger_ops = {
1231 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1232 .validate_device = mma8452_validate_device,
1233 .owner = THIS_MODULE,
1234 };
1235
1236 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1237 {
1238 struct mma8452_data *data = iio_priv(indio_dev);
1239 struct iio_trigger *trig;
1240 int ret;
1241
1242 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1243 indio_dev->name,
1244 indio_dev->id);
1245 if (!trig)
1246 return -ENOMEM;
1247
1248 trig->dev.parent = &data->client->dev;
1249 trig->ops = &mma8452_trigger_ops;
1250 iio_trigger_set_drvdata(trig, indio_dev);
1251
1252 ret = iio_trigger_register(trig);
1253 if (ret)
1254 return ret;
1255
1256 indio_dev->trig = trig;
1257
1258 return 0;
1259 }
1260
1261 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1262 {
1263 if (indio_dev->trig)
1264 iio_trigger_unregister(indio_dev->trig);
1265 }
1266
1267 static int mma8452_reset(struct i2c_client *client)
1268 {
1269 int i;
1270 int ret;
1271
1272 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1273 MMA8452_CTRL_REG2_RST);
1274 if (ret < 0)
1275 return ret;
1276
1277 for (i = 0; i < 10; i++) {
1278 usleep_range(100, 200);
1279 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1280 if (ret == -EIO)
1281 continue; /* I2C comm reset */
1282 if (ret < 0)
1283 return ret;
1284 if (!(ret & MMA8452_CTRL_REG2_RST))
1285 return 0;
1286 }
1287
1288 return -ETIMEDOUT;
1289 }
1290
1291 static const struct of_device_id mma8452_dt_ids[] = {
1292 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1293 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1294 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1295 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1296 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1297 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1298 { }
1299 };
1300 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1301
1302 static int mma8452_probe(struct i2c_client *client,
1303 const struct i2c_device_id *id)
1304 {
1305 struct mma8452_data *data;
1306 struct iio_dev *indio_dev;
1307 int ret;
1308 const struct of_device_id *match;
1309
1310 match = of_match_device(mma8452_dt_ids, &client->dev);
1311 if (!match) {
1312 dev_err(&client->dev, "unknown device model\n");
1313 return -ENODEV;
1314 }
1315
1316 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1317 if (!indio_dev)
1318 return -ENOMEM;
1319
1320 data = iio_priv(indio_dev);
1321 data->client = client;
1322 mutex_init(&data->lock);
1323 data->chip_info = match->data;
1324
1325 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1326 if (ret < 0)
1327 return ret;
1328
1329 switch (ret) {
1330 case MMA8451_DEVICE_ID:
1331 case MMA8452_DEVICE_ID:
1332 case MMA8453_DEVICE_ID:
1333 case MMA8652_DEVICE_ID:
1334 case MMA8653_DEVICE_ID:
1335 case FXLS8471_DEVICE_ID:
1336 if (ret == data->chip_info->chip_id)
1337 break;
1338 default:
1339 return -ENODEV;
1340 }
1341
1342 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1343 match->compatible, data->chip_info->chip_id);
1344
1345 i2c_set_clientdata(client, indio_dev);
1346 indio_dev->info = &mma8452_info;
1347 indio_dev->name = id->name;
1348 indio_dev->dev.parent = &client->dev;
1349 indio_dev->modes = INDIO_DIRECT_MODE;
1350 indio_dev->channels = data->chip_info->channels;
1351 indio_dev->num_channels = data->chip_info->num_channels;
1352 indio_dev->available_scan_masks = mma8452_scan_masks;
1353
1354 ret = mma8452_reset(client);
1355 if (ret < 0)
1356 return ret;
1357
1358 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1359 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1360 data->data_cfg);
1361 if (ret < 0)
1362 return ret;
1363
1364 /*
1365 * By default set transient threshold to max to avoid events if
1366 * enabling without configuring threshold.
1367 */
1368 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1369 MMA8452_TRANSIENT_THS_MASK);
1370 if (ret < 0)
1371 return ret;
1372
1373 if (client->irq) {
1374 /*
1375 * Although we enable the interrupt sources once and for
1376 * all here the event detection itself is not enabled until
1377 * userspace asks for it by mma8452_write_event_config()
1378 */
1379 int supported_interrupts = MMA8452_INT_DRDY |
1380 MMA8452_INT_TRANS |
1381 MMA8452_INT_FF_MT;
1382 int enabled_interrupts = MMA8452_INT_TRANS |
1383 MMA8452_INT_FF_MT;
1384 int irq2;
1385
1386 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1387
1388 if (irq2 == client->irq) {
1389 dev_dbg(&client->dev, "using interrupt line INT2\n");
1390 } else {
1391 ret = i2c_smbus_write_byte_data(client,
1392 MMA8452_CTRL_REG5,
1393 supported_interrupts);
1394 if (ret < 0)
1395 return ret;
1396
1397 dev_dbg(&client->dev, "using interrupt line INT1\n");
1398 }
1399
1400 ret = i2c_smbus_write_byte_data(client,
1401 MMA8452_CTRL_REG4,
1402 enabled_interrupts);
1403 if (ret < 0)
1404 return ret;
1405
1406 ret = mma8452_trigger_setup(indio_dev);
1407 if (ret < 0)
1408 return ret;
1409 }
1410
1411 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1412 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1413 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1414 data->ctrl_reg1);
1415 if (ret < 0)
1416 goto trigger_cleanup;
1417
1418 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1419 mma8452_trigger_handler, NULL);
1420 if (ret < 0)
1421 goto trigger_cleanup;
1422
1423 if (client->irq) {
1424 ret = devm_request_threaded_irq(&client->dev,
1425 client->irq,
1426 NULL, mma8452_interrupt,
1427 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1428 client->name, indio_dev);
1429 if (ret)
1430 goto buffer_cleanup;
1431 }
1432
1433 ret = pm_runtime_set_active(&client->dev);
1434 if (ret < 0)
1435 goto buffer_cleanup;
1436
1437 pm_runtime_enable(&client->dev);
1438 pm_runtime_set_autosuspend_delay(&client->dev,
1439 MMA8452_AUTO_SUSPEND_DELAY_MS);
1440 pm_runtime_use_autosuspend(&client->dev);
1441
1442 ret = iio_device_register(indio_dev);
1443 if (ret < 0)
1444 goto buffer_cleanup;
1445
1446 ret = mma8452_set_freefall_mode(data, false);
1447 if (ret)
1448 return ret;
1449
1450 return 0;
1451
1452 buffer_cleanup:
1453 iio_triggered_buffer_cleanup(indio_dev);
1454
1455 trigger_cleanup:
1456 mma8452_trigger_cleanup(indio_dev);
1457
1458 return ret;
1459 }
1460
1461 static int mma8452_remove(struct i2c_client *client)
1462 {
1463 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1464
1465 iio_device_unregister(indio_dev);
1466
1467 pm_runtime_disable(&client->dev);
1468 pm_runtime_set_suspended(&client->dev);
1469 pm_runtime_put_noidle(&client->dev);
1470
1471 iio_triggered_buffer_cleanup(indio_dev);
1472 mma8452_trigger_cleanup(indio_dev);
1473 mma8452_standby(iio_priv(indio_dev));
1474
1475 return 0;
1476 }
1477
1478 #ifdef CONFIG_PM
1479 static int mma8452_runtime_suspend(struct device *dev)
1480 {
1481 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1482 struct mma8452_data *data = iio_priv(indio_dev);
1483 int ret;
1484
1485 mutex_lock(&data->lock);
1486 ret = mma8452_standby(data);
1487 mutex_unlock(&data->lock);
1488 if (ret < 0) {
1489 dev_err(&data->client->dev, "powering off device failed\n");
1490 return -EAGAIN;
1491 }
1492
1493 return 0;
1494 }
1495
1496 static int mma8452_runtime_resume(struct device *dev)
1497 {
1498 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1499 struct mma8452_data *data = iio_priv(indio_dev);
1500 int ret, sleep_val;
1501
1502 ret = mma8452_active(data);
1503 if (ret < 0)
1504 return ret;
1505
1506 ret = mma8452_get_odr_index(data);
1507 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1508 if (sleep_val < 20)
1509 usleep_range(sleep_val * 1000, 20000);
1510 else
1511 msleep_interruptible(sleep_val);
1512
1513 return 0;
1514 }
1515 #endif
1516
1517 #ifdef CONFIG_PM_SLEEP
1518 static int mma8452_suspend(struct device *dev)
1519 {
1520 return mma8452_standby(iio_priv(i2c_get_clientdata(
1521 to_i2c_client(dev))));
1522 }
1523
1524 static int mma8452_resume(struct device *dev)
1525 {
1526 return mma8452_active(iio_priv(i2c_get_clientdata(
1527 to_i2c_client(dev))));
1528 }
1529 #endif
1530
1531 static const struct dev_pm_ops mma8452_pm_ops = {
1532 SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend, mma8452_resume)
1533 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1534 mma8452_runtime_resume, NULL)
1535 };
1536
1537 static const struct i2c_device_id mma8452_id[] = {
1538 { "mma8451", mma8451 },
1539 { "mma8452", mma8452 },
1540 { "mma8453", mma8453 },
1541 { "mma8652", mma8652 },
1542 { "mma8653", mma8653 },
1543 { "fxls8471", fxls8471 },
1544 { }
1545 };
1546 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1547
1548 static struct i2c_driver mma8452_driver = {
1549 .driver = {
1550 .name = "mma8452",
1551 .of_match_table = of_match_ptr(mma8452_dt_ids),
1552 .pm = &mma8452_pm_ops,
1553 },
1554 .probe = mma8452_probe,
1555 .remove = mma8452_remove,
1556 .id_table = mma8452_id,
1557 };
1558 module_i2c_driver(mma8452_driver);
1559
1560 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1561 MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
1562 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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