drivers/iio/adc/cc10001_adc.c

   1 /*
   2  * Copyright (c) 2014-2015 Imagination Technologies Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published by
   6  * the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/slab.h>
  20
  21 #include <linux/iio/buffer.h>
  22 #include <linux/iio/iio.h>
  23 #include <linux/iio/sysfs.h>
  24 #include <linux/iio/trigger.h>
  25 #include <linux/iio/trigger_consumer.h>
  26 #include <linux/iio/triggered_buffer.h>
  27
  28 /* Registers */
  29 #define CC10001_ADC_CONFIG              0x00
  30 #define CC10001_ADC_START_CONV          BIT(4)
  31 #define CC10001_ADC_MODE_SINGLE_CONV    BIT(5)
  32
  33 #define CC10001_ADC_DDATA_OUT           0x04
  34 #define CC10001_ADC_EOC                 0x08
  35 #define CC10001_ADC_EOC_SET             BIT(0)
  36
  37 #define CC10001_ADC_CHSEL_SAMPLED       0x0c
  38 #define CC10001_ADC_POWER_UP            0x10
  39 #define CC10001_ADC_POWER_UP_SET        BIT(0)
  40 #define CC10001_ADC_DEBUG               0x14
  41 #define CC10001_ADC_DATA_COUNT          0x20
  42
  43 #define CC10001_ADC_DATA_MASK           GENMASK(9, 0)
  44 #define CC10001_ADC_NUM_CHANNELS        8
  45 #define CC10001_ADC_CH_MASK             GENMASK(2, 0)
  46
  47 #define CC10001_INVALID_SAMPLED         0xffff
  48 #define CC10001_MAX_POLL_COUNT          20
  49
  50 /*
  51  * As per device specification, wait six clock cycles after power-up to
  52  * activate START. Since adding two more clock cycles delay does not
  53  * impact the performance too much, we are adding two additional cycles delay
  54  * intentionally here.
  55  */
  56 #define CC10001_WAIT_CYCLES             8
  57
  58 struct cc10001_adc_device {
  59         void __iomem *reg_base;
  60         struct clk *adc_clk;
  61         struct regulator *reg;
  62         u16 *buf;
  63
  64         struct mutex lock;
  65         unsigned long channel_map;
  66         unsigned int start_delay_ns;
  67         unsigned int eoc_delay_ns;
  68 };
  69
  70 static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev,
  71                                          u32 reg, u32 val)
  72 {
  73         writel(val, adc_dev->reg_base + reg);
  74 }
  75
  76 static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev,
  77                                        u32 reg)
  78 {
  79         return readl(adc_dev->reg_base + reg);
  80 }
  81
  82 static void cc10001_adc_start(struct cc10001_adc_device *adc_dev,
  83                               unsigned int channel)
  84 {
  85         u32 val;
  86
  87         /* Channel selection and mode of operation */
  88         val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV;
  89         cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
  90
  91         val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG);
  92         val = val | CC10001_ADC_START_CONV;
  93         cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
  94 }
  95
  96 static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev,
  97                                  unsigned int channel,
  98                                  unsigned int delay)
  99 {
 100         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 101         unsigned int poll_count = 0;
 102
 103         while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) &
 104                         CC10001_ADC_EOC_SET)) {
 105
 106                 ndelay(delay);
 107                 if (poll_count++ == CC10001_MAX_POLL_COUNT)
 108                         return CC10001_INVALID_SAMPLED;
 109         }
 110
 111         poll_count = 0;
 112         while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) &
 113                         CC10001_ADC_CH_MASK) != channel) {
 114
 115                 ndelay(delay);
 116                 if (poll_count++ == CC10001_MAX_POLL_COUNT)
 117                         return CC10001_INVALID_SAMPLED;
 118         }
 119
 120         /* Read the 10 bit output register */
 121         return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) &
 122                                CC10001_ADC_DATA_MASK;
 123 }
 124
 125 static irqreturn_t cc10001_adc_trigger_h(int irq, void *p)
 126 {
 127         struct cc10001_adc_device *adc_dev;
 128         struct iio_poll_func *pf = p;
 129         struct iio_dev *indio_dev;
 130         unsigned int delay_ns;
 131         unsigned int channel;
 132         bool sample_invalid;
 133         u16 *data;
 134         int i;
 135
 136         indio_dev = pf->indio_dev;
 137         adc_dev = iio_priv(indio_dev);
 138         data = adc_dev->buf;
 139
 140         mutex_lock(&adc_dev->lock);
 141
 142         cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_UP,
 143                               CC10001_ADC_POWER_UP_SET);
 144
 145         /* Wait for 8 (6+2) clock cycles before activating START */
 146         ndelay(adc_dev->start_delay_ns);
 147
 148         /* Calculate delay step for eoc and sampled data */
 149         delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
 150
 151         i = 0;
 152         sample_invalid = false;
 153         for_each_set_bit(channel, indio_dev->active_scan_mask,
 154                                   indio_dev->masklength) {
 155
 156                 cc10001_adc_start(adc_dev, channel);
 157
 158                 data[i] = cc10001_adc_poll_done(indio_dev, channel, delay_ns);
 159                 if (data[i] == CC10001_INVALID_SAMPLED) {
 160                         dev_warn(&indio_dev->dev,
 161                                  "invalid sample on channel %d\n", channel);
 162                         sample_invalid = true;
 163                         goto done;
 164                 }
 165                 i++;
 166         }
 167
 168 done:
 169         cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_UP, 0);
 170
 171         mutex_unlock(&adc_dev->lock);
 172
 173         if (!sample_invalid)
 174                 iio_push_to_buffers_with_timestamp(indio_dev, data,
 175                                                    iio_get_time_ns());
 176         iio_trigger_notify_done(indio_dev->trig);
 177
 178         return IRQ_HANDLED;
 179 }
 180
 181 static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev,
 182                                         struct iio_chan_spec const *chan)
 183 {
 184         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 185         unsigned int delay_ns;
 186         u16 val;
 187
 188         cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_UP,
 189                               CC10001_ADC_POWER_UP_SET);
 190
 191         /* Wait for 8 (6+2) clock cycles before activating START */
 192         ndelay(adc_dev->start_delay_ns);
 193
 194         /* Calculate delay step for eoc and sampled data */
 195         delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
 196
 197         cc10001_adc_start(adc_dev, chan->channel);
 198
 199         val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns);
 200
 201         cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_UP, 0);
 202
 203         return val;
 204 }
 205
 206 static int cc10001_adc_read_raw(struct iio_dev *indio_dev,
 207                                  struct iio_chan_spec const *chan,
 208                                  int *val, int *val2, long mask)
 209 {
 210         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 211         int ret;
 212
 213         switch (mask) {
 214         case IIO_CHAN_INFO_RAW:
 215                 if (iio_buffer_enabled(indio_dev))
 216                         return -EBUSY;
 217                 mutex_lock(&adc_dev->lock);
 218                 *val = cc10001_adc_read_raw_voltage(indio_dev, chan);
 219                 mutex_unlock(&adc_dev->lock);
 220
 221                 if (*val == CC10001_INVALID_SAMPLED)
 222                         return -EIO;
 223                 return IIO_VAL_INT;
 224
 225         case IIO_CHAN_INFO_SCALE:
 226                 ret = regulator_get_voltage(adc_dev->reg);
 227                 if (ret)
 228                         return ret;
 229
 230                 *val = ret / 1000;
 231                 *val2 = chan->scan_type.realbits;
 232                 return IIO_VAL_FRACTIONAL_LOG2;
 233
 234         default:
 235                 return -EINVAL;
 236         }
 237 }
 238
 239 static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
 240                                     const unsigned long *scan_mask)
 241 {
 242         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 243
 244         kfree(adc_dev->buf);
 245         adc_dev->buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
 246         if (!adc_dev->buf)
 247                 return -ENOMEM;
 248
 249         return 0;
 250 }
 251
 252 static const struct iio_info cc10001_adc_info = {
 253         .driver_module = THIS_MODULE,
 254         .read_raw = &cc10001_adc_read_raw,
 255         .update_scan_mode = &cc10001_update_scan_mode,
 256 };
 257
 258 static int cc10001_adc_channel_init(struct iio_dev *indio_dev)
 259 {
 260         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 261         struct iio_chan_spec *chan_array, *timestamp;
 262         unsigned int bit, idx = 0;
 263
 264         indio_dev->num_channels = bitmap_weight(&adc_dev->channel_map,
 265                                                 CC10001_ADC_NUM_CHANNELS);
 266
 267         chan_array = devm_kcalloc(&indio_dev->dev, indio_dev->num_channels + 1,
 268                                   sizeof(struct iio_chan_spec),
 269                                   GFP_KERNEL);
 270         if (!chan_array)
 271                 return -ENOMEM;
 272
 273         for_each_set_bit(bit, &adc_dev->channel_map, CC10001_ADC_NUM_CHANNELS) {
 274                 struct iio_chan_spec *chan = &chan_array[idx];
 275
 276                 chan->type = IIO_VOLTAGE;
 277                 chan->indexed = 1;
 278                 chan->channel = bit;
 279                 chan->scan_index = idx;
 280                 chan->scan_type.sign = 'u';
 281                 chan->scan_type.realbits = 10;
 282                 chan->scan_type.storagebits = 16;
 283                 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
 284                 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
 285                 idx++;
 286         }
 287
 288         timestamp = &chan_array[idx];
 289         timestamp->type = IIO_TIMESTAMP;
 290         timestamp->channel = -1;
 291         timestamp->scan_index = idx;
 292         timestamp->scan_type.sign = 's';
 293         timestamp->scan_type.realbits = 64;
 294         timestamp->scan_type.storagebits = 64;
 295
 296         indio_dev->channels = chan_array;
 297
 298         return 0;
 299 }
 300
 301 static int cc10001_adc_probe(struct platform_device *pdev)
 302 {
 303         struct device_node *node = pdev->dev.of_node;
 304         struct cc10001_adc_device *adc_dev;
 305         unsigned long adc_clk_rate;
 306         struct resource *res;
 307         struct iio_dev *indio_dev;
 308         int ret;
 309
 310         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
 311         if (indio_dev == NULL)
 312                 return -ENOMEM;
 313
 314         adc_dev = iio_priv(indio_dev);
 315
 316         adc_dev->channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);
 317         if (!of_property_read_u32(node, "adc-reserved-channels", &ret))
 318                 adc_dev->channel_map &= ~ret;
 319
 320         adc_dev->reg = devm_regulator_get(&pdev->dev, "vref");
 321         if (IS_ERR(adc_dev->reg))
 322                 return PTR_ERR(adc_dev->reg);
 323
 324         ret = regulator_enable(adc_dev->reg);
 325         if (ret)
 326                 return ret;
 327
 328         indio_dev->dev.parent = &pdev->dev;
 329         indio_dev->name = dev_name(&pdev->dev);
 330         indio_dev->info = &cc10001_adc_info;
 331         indio_dev->modes = INDIO_DIRECT_MODE;
 332
 333         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 334         adc_dev->reg_base = devm_ioremap_resource(&pdev->dev, res);
 335         if (IS_ERR(adc_dev->reg_base)) {
 336                 ret = PTR_ERR(adc_dev->reg_base);
 337                 goto err_disable_reg;
 338         }
 339
 340         adc_dev->adc_clk = devm_clk_get(&pdev->dev, "adc");
 341         if (IS_ERR(adc_dev->adc_clk)) {
 342                 dev_err(&pdev->dev, "failed to get the clock\n");
 343                 ret = PTR_ERR(adc_dev->adc_clk);
 344                 goto err_disable_reg;
 345         }
 346
 347         ret = clk_prepare_enable(adc_dev->adc_clk);
 348         if (ret) {
 349                 dev_err(&pdev->dev, "failed to enable the clock\n");
 350                 goto err_disable_reg;
 351         }
 352
 353         adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
 354         if (!adc_clk_rate) {
 355                 ret = -EINVAL;
 356                 dev_err(&pdev->dev, "null clock rate!\n");
 357                 goto err_disable_clk;
 358         }
 359
 360         adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate;
 361         adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES;
 362
 363         /* Setup the ADC channels available on the device */
 364         ret = cc10001_adc_channel_init(indio_dev);
 365         if (ret < 0)
 366                 goto err_disable_clk;
 367
 368         mutex_init(&adc_dev->lock);
 369
 370         ret = iio_triggered_buffer_setup(indio_dev, NULL,
 371                                          &cc10001_adc_trigger_h, NULL);
 372         if (ret < 0)
 373                 goto err_disable_clk;
 374
 375         ret = iio_device_register(indio_dev);
 376         if (ret < 0)
 377                 goto err_cleanup_buffer;
 378
 379         platform_set_drvdata(pdev, indio_dev);
 380
 381         return 0;
 382
 383 err_cleanup_buffer:
 384         iio_triggered_buffer_cleanup(indio_dev);
 385 err_disable_clk:
 386         clk_disable_unprepare(adc_dev->adc_clk);
 387 err_disable_reg:
 388         regulator_disable(adc_dev->reg);
 389         return ret;
 390 }
 391
 392 static int cc10001_adc_remove(struct platform_device *pdev)
 393 {
 394         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 395         struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
 396
 397         iio_device_unregister(indio_dev);
 398         iio_triggered_buffer_cleanup(indio_dev);
 399         clk_disable_unprepare(adc_dev->adc_clk);
 400         regulator_disable(adc_dev->reg);
 401
 402         return 0;
 403 }
 404
 405 static const struct of_device_id cc10001_adc_dt_ids[] = {
 406         { .compatible = "cosmic,10001-adc", },
 407         { }
 408 };
 409 MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids);
 410
 411 static struct platform_driver cc10001_adc_driver = {
 412         .driver = {
 413                 .name   = "cc10001-adc",
 414                 .of_match_table = cc10001_adc_dt_ids,
 415         },
 416         .probe  = cc10001_adc_probe,
 417         .remove = cc10001_adc_remove,
 418 };
 419 module_platform_driver(cc10001_adc_driver);
 420
 421 MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>");
 422 MODULE_DESCRIPTION("Cosmic Circuits ADC driver");
 423 MODULE_LICENSE("GPL v2");