drivers/iio/adc/vf610_adc.c

   1 /*
   2  * Freescale Vybrid vf610 ADC driver
   3  *
   4  * Copyright 2013 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include <linux/io.h>
  28 #include <linux/clk.h>
  29 #include <linux/completion.h>
  30 #include <linux/of.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/regulator/consumer.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/err.h>
  35
  36 #include <linux/iio/iio.h>
  37 #include <linux/iio/sysfs.h>
  38 #include <linux/iio/driver.h>
  39
  40 /* This will be the driver name the kernel reports */
  41 #define DRIVER_NAME "vf610-adc"
  42
  43 /* Vybrid/IMX ADC registers */
  44 #define VF610_REG_ADC_HC0               0x00
  45 #define VF610_REG_ADC_HC1               0x04
  46 #define VF610_REG_ADC_HS                0x08
  47 #define VF610_REG_ADC_R0                0x0c
  48 #define VF610_REG_ADC_R1                0x10
  49 #define VF610_REG_ADC_CFG               0x14
  50 #define VF610_REG_ADC_GC                0x18
  51 #define VF610_REG_ADC_GS                0x1c
  52 #define VF610_REG_ADC_CV                0x20
  53 #define VF610_REG_ADC_OFS               0x24
  54 #define VF610_REG_ADC_CAL               0x28
  55 #define VF610_REG_ADC_PCTL              0x30
  56
  57 /* Configuration register field define */
  58 #define VF610_ADC_MODE_BIT8             0x00
  59 #define VF610_ADC_MODE_BIT10            0x04
  60 #define VF610_ADC_MODE_BIT12            0x08
  61 #define VF610_ADC_MODE_MASK             0x0c
  62 #define VF610_ADC_BUSCLK2_SEL           0x01
  63 #define VF610_ADC_ALTCLK_SEL            0x02
  64 #define VF610_ADC_ADACK_SEL             0x03
  65 #define VF610_ADC_ADCCLK_MASK           0x03
  66 #define VF610_ADC_CLK_DIV2              0x20
  67 #define VF610_ADC_CLK_DIV4              0x40
  68 #define VF610_ADC_CLK_DIV8              0x60
  69 #define VF610_ADC_CLK_MASK              0x60
  70 #define VF610_ADC_ADLSMP_LONG           0x10
  71 #define VF610_ADC_ADSTS_MASK            0x300
  72 #define VF610_ADC_ADLPC_EN              0x80
  73 #define VF610_ADC_ADHSC_EN              0x400
  74 #define VF610_ADC_REFSEL_VALT           0x100
  75 #define VF610_ADC_REFSEL_VBG            0x1000
  76 #define VF610_ADC_ADTRG_HARD            0x2000
  77 #define VF610_ADC_AVGS_8                0x4000
  78 #define VF610_ADC_AVGS_16               0x8000
  79 #define VF610_ADC_AVGS_32               0xC000
  80 #define VF610_ADC_AVGS_MASK             0xC000
  81 #define VF610_ADC_OVWREN                0x10000
  82
  83 /* General control register field define */
  84 #define VF610_ADC_ADACKEN               0x1
  85 #define VF610_ADC_DMAEN                 0x2
  86 #define VF610_ADC_ACREN                 0x4
  87 #define VF610_ADC_ACFGT                 0x8
  88 #define VF610_ADC_ACFE                  0x10
  89 #define VF610_ADC_AVGEN                 0x20
  90 #define VF610_ADC_ADCON                 0x40
  91 #define VF610_ADC_CAL                   0x80
  92
  93 /* Other field define */
  94 #define VF610_ADC_ADCHC(x)              ((x) & 0x1F)
  95 #define VF610_ADC_AIEN                  (0x1 << 7)
  96 #define VF610_ADC_CONV_DISABLE          0x1F
  97 #define VF610_ADC_HS_COCO0              0x1
  98 #define VF610_ADC_CALF                  0x2
  99 #define VF610_ADC_TIMEOUT               msecs_to_jiffies(100)
 100
 101 enum clk_sel {
 102         VF610_ADCIOC_BUSCLK_SET,
 103         VF610_ADCIOC_ALTCLK_SET,
 104         VF610_ADCIOC_ADACK_SET,
 105 };
 106
 107 enum vol_ref {
 108         VF610_ADCIOC_VR_VREF_SET,
 109         VF610_ADCIOC_VR_VALT_SET,
 110         VF610_ADCIOC_VR_VBG_SET,
 111 };
 112
 113 enum average_sel {
 114         VF610_ADC_SAMPLE_1,
 115         VF610_ADC_SAMPLE_4,
 116         VF610_ADC_SAMPLE_8,
 117         VF610_ADC_SAMPLE_16,
 118         VF610_ADC_SAMPLE_32,
 119 };
 120
 121 struct vf610_adc_feature {
 122         enum clk_sel    clk_sel;
 123         enum vol_ref    vol_ref;
 124
 125         int     clk_div;
 126         int     sample_rate;
 127         int     res_mode;
 128
 129         bool    lpm;
 130         bool    calibration;
 131         bool    ovwren;
 132 };
 133
 134 struct vf610_adc {
 135         struct device *dev;
 136         void __iomem *regs;
 137         struct clk *clk;
 138
 139         u32 vref_uv;
 140         u32 value;
 141         struct regulator *vref;
 142         struct vf610_adc_feature adc_feature;
 143
 144         u32 sample_freq_avail[5];
 145
 146         struct completion completion;
 147 };
 148
 149 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
 150
 151 #define VF610_ADC_CHAN(_idx, _chan_type) {                      \
 152         .type = (_chan_type),                                   \
 153         .indexed = 1,                                           \
 154         .channel = (_idx),                                      \
 155         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 156         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  \
 157                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
 158 }
 159
 160 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) {  \
 161         .type = (_chan_type),   \
 162         .channel = (_idx),              \
 163         .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),     \
 164 }
 165
 166 static const struct iio_chan_spec vf610_adc_iio_channels[] = {
 167         VF610_ADC_CHAN(0, IIO_VOLTAGE),
 168         VF610_ADC_CHAN(1, IIO_VOLTAGE),
 169         VF610_ADC_CHAN(2, IIO_VOLTAGE),
 170         VF610_ADC_CHAN(3, IIO_VOLTAGE),
 171         VF610_ADC_CHAN(4, IIO_VOLTAGE),
 172         VF610_ADC_CHAN(5, IIO_VOLTAGE),
 173         VF610_ADC_CHAN(6, IIO_VOLTAGE),
 174         VF610_ADC_CHAN(7, IIO_VOLTAGE),
 175         VF610_ADC_CHAN(8, IIO_VOLTAGE),
 176         VF610_ADC_CHAN(9, IIO_VOLTAGE),
 177         VF610_ADC_CHAN(10, IIO_VOLTAGE),
 178         VF610_ADC_CHAN(11, IIO_VOLTAGE),
 179         VF610_ADC_CHAN(12, IIO_VOLTAGE),
 180         VF610_ADC_CHAN(13, IIO_VOLTAGE),
 181         VF610_ADC_CHAN(14, IIO_VOLTAGE),
 182         VF610_ADC_CHAN(15, IIO_VOLTAGE),
 183         VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
 184         /* sentinel */
 185 };
 186
 187 static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
 188 {
 189         unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
 190         int i;
 191
 192         /*
 193          * Calculate ADC sample frequencies
 194          * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
 195          * which is the same as bus clock.
 196          *
 197          * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
 198          * SFCAdder: fixed to 6 ADCK cycles
 199          * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
 200          * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
 201          * LSTAdder(Long Sample Time): fixed to 3 ADCK cycles
 202          */
 203         adck_rate = ipg_rate / info->adc_feature.clk_div;
 204         for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
 205                 info->sample_freq_avail[i] =
 206                         adck_rate / (6 + vf610_hw_avgs[i] * (25 + 3));
 207 }
 208
 209 static inline void vf610_adc_cfg_init(struct vf610_adc *info)
 210 {
 211         struct vf610_adc_feature *adc_feature = &info->adc_feature;
 212
 213         /* set default Configuration for ADC controller */
 214         adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
 215         adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
 216
 217         adc_feature->calibration = true;
 218         adc_feature->ovwren = true;
 219
 220         adc_feature->res_mode = 12;
 221         adc_feature->sample_rate = 1;
 222         adc_feature->lpm = true;
 223
 224         /* Use a save ADCK which is below 20MHz on all devices */
 225         adc_feature->clk_div = 8;
 226
 227         vf610_adc_calculate_rates(info);
 228 }
 229
 230 static void vf610_adc_cfg_post_set(struct vf610_adc *info)
 231 {
 232         struct vf610_adc_feature *adc_feature = &info->adc_feature;
 233         int cfg_data = 0;
 234         int gc_data = 0;
 235
 236         switch (adc_feature->clk_sel) {
 237         case VF610_ADCIOC_ALTCLK_SET:
 238                 cfg_data |= VF610_ADC_ALTCLK_SEL;
 239                 break;
 240         case VF610_ADCIOC_ADACK_SET:
 241                 cfg_data |= VF610_ADC_ADACK_SEL;
 242                 break;
 243         default:
 244                 break;
 245         }
 246
 247         /* low power set for calibration */
 248         cfg_data |= VF610_ADC_ADLPC_EN;
 249
 250         /* enable high speed for calibration */
 251         cfg_data |= VF610_ADC_ADHSC_EN;
 252
 253         /* voltage reference */
 254         switch (adc_feature->vol_ref) {
 255         case VF610_ADCIOC_VR_VREF_SET:
 256                 break;
 257         case VF610_ADCIOC_VR_VALT_SET:
 258                 cfg_data |= VF610_ADC_REFSEL_VALT;
 259                 break;
 260         case VF610_ADCIOC_VR_VBG_SET:
 261                 cfg_data |= VF610_ADC_REFSEL_VBG;
 262                 break;
 263         default:
 264                 dev_err(info->dev, "error voltage reference\n");
 265         }
 266
 267         /* data overwrite enable */
 268         if (adc_feature->ovwren)
 269                 cfg_data |= VF610_ADC_OVWREN;
 270
 271         writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
 272         writel(gc_data, info->regs + VF610_REG_ADC_GC);
 273 }
 274
 275 static void vf610_adc_calibration(struct vf610_adc *info)
 276 {
 277         int adc_gc, hc_cfg;
 278         int timeout;
 279
 280         if (!info->adc_feature.calibration)
 281                 return;
 282
 283         /* enable calibration interrupt */
 284         hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
 285         writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 286
 287         adc_gc = readl(info->regs + VF610_REG_ADC_GC);
 288         writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
 289
 290         timeout = wait_for_completion_timeout
 291                         (&info->completion, VF610_ADC_TIMEOUT);
 292         if (timeout == 0)
 293                 dev_err(info->dev, "Timeout for adc calibration\n");
 294
 295         adc_gc = readl(info->regs + VF610_REG_ADC_GS);
 296         if (adc_gc & VF610_ADC_CALF)
 297                 dev_err(info->dev, "ADC calibration failed\n");
 298
 299         info->adc_feature.calibration = false;
 300 }
 301
 302 static void vf610_adc_cfg_set(struct vf610_adc *info)
 303 {
 304         struct vf610_adc_feature *adc_feature = &(info->adc_feature);
 305         int cfg_data;
 306
 307         cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
 308
 309         cfg_data &= ~VF610_ADC_ADLPC_EN;
 310         if (adc_feature->lpm)
 311                 cfg_data |= VF610_ADC_ADLPC_EN;
 312
 313         cfg_data &= ~VF610_ADC_ADHSC_EN;
 314
 315         writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
 316 }
 317
 318 static void vf610_adc_sample_set(struct vf610_adc *info)
 319 {
 320         struct vf610_adc_feature *adc_feature = &(info->adc_feature);
 321         int cfg_data, gc_data;
 322
 323         cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
 324         gc_data = readl(info->regs + VF610_REG_ADC_GC);
 325
 326         /* resolution mode */
 327         cfg_data &= ~VF610_ADC_MODE_MASK;
 328         switch (adc_feature->res_mode) {
 329         case 8:
 330                 cfg_data |= VF610_ADC_MODE_BIT8;
 331                 break;
 332         case 10:
 333                 cfg_data |= VF610_ADC_MODE_BIT10;
 334                 break;
 335         case 12:
 336                 cfg_data |= VF610_ADC_MODE_BIT12;
 337                 break;
 338         default:
 339                 dev_err(info->dev, "error resolution mode\n");
 340                 break;
 341         }
 342
 343         /* clock select and clock divider */
 344         cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
 345         switch (adc_feature->clk_div) {
 346         case 1:
 347                 break;
 348         case 2:
 349                 cfg_data |= VF610_ADC_CLK_DIV2;
 350                 break;
 351         case 4:
 352                 cfg_data |= VF610_ADC_CLK_DIV4;
 353                 break;
 354         case 8:
 355                 cfg_data |= VF610_ADC_CLK_DIV8;
 356                 break;
 357         case 16:
 358                 switch (adc_feature->clk_sel) {
 359                 case VF610_ADCIOC_BUSCLK_SET:
 360                         cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
 361                         break;
 362                 default:
 363                         dev_err(info->dev, "error clk divider\n");
 364                         break;
 365                 }
 366                 break;
 367         }
 368
 369         /* Use the short sample mode */
 370         cfg_data &= ~(VF610_ADC_ADLSMP_LONG | VF610_ADC_ADSTS_MASK);
 371
 372         /* update hardware average selection */
 373         cfg_data &= ~VF610_ADC_AVGS_MASK;
 374         gc_data &= ~VF610_ADC_AVGEN;
 375         switch (adc_feature->sample_rate) {
 376         case VF610_ADC_SAMPLE_1:
 377                 break;
 378         case VF610_ADC_SAMPLE_4:
 379                 gc_data |= VF610_ADC_AVGEN;
 380                 break;
 381         case VF610_ADC_SAMPLE_8:
 382                 gc_data |= VF610_ADC_AVGEN;
 383                 cfg_data |= VF610_ADC_AVGS_8;
 384                 break;
 385         case VF610_ADC_SAMPLE_16:
 386                 gc_data |= VF610_ADC_AVGEN;
 387                 cfg_data |= VF610_ADC_AVGS_16;
 388                 break;
 389         case VF610_ADC_SAMPLE_32:
 390                 gc_data |= VF610_ADC_AVGEN;
 391                 cfg_data |= VF610_ADC_AVGS_32;
 392                 break;
 393         default:
 394                 dev_err(info->dev,
 395                         "error hardware sample average select\n");
 396         }
 397
 398         writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
 399         writel(gc_data, info->regs + VF610_REG_ADC_GC);
 400 }
 401
 402 static void vf610_adc_hw_init(struct vf610_adc *info)
 403 {
 404         /* CFG: Feature set */
 405         vf610_adc_cfg_post_set(info);
 406         vf610_adc_sample_set(info);
 407
 408         /* adc calibration */
 409         vf610_adc_calibration(info);
 410
 411         /* CFG: power and speed set */
 412         vf610_adc_cfg_set(info);
 413 }
 414
 415 static int vf610_adc_read_data(struct vf610_adc *info)
 416 {
 417         int result;
 418
 419         result = readl(info->regs + VF610_REG_ADC_R0);
 420
 421         switch (info->adc_feature.res_mode) {
 422         case 8:
 423                 result &= 0xFF;
 424                 break;
 425         case 10:
 426                 result &= 0x3FF;
 427                 break;
 428         case 12:
 429                 result &= 0xFFF;
 430                 break;
 431         default:
 432                 break;
 433         }
 434
 435         return result;
 436 }
 437
 438 static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
 439 {
 440         struct vf610_adc *info = (struct vf610_adc *)dev_id;
 441         int coco;
 442
 443         coco = readl(info->regs + VF610_REG_ADC_HS);
 444         if (coco & VF610_ADC_HS_COCO0) {
 445                 info->value = vf610_adc_read_data(info);
 446                 complete(&info->completion);
 447         }
 448
 449         return IRQ_HANDLED;
 450 }
 451
 452 static ssize_t vf610_show_samp_freq_avail(struct device *dev,
 453                                 struct device_attribute *attr, char *buf)
 454 {
 455         struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
 456         size_t len = 0;
 457         int i;
 458
 459         for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
 460                 len += scnprintf(buf + len, PAGE_SIZE - len,
 461                         "%u ", info->sample_freq_avail[i]);
 462
 463         /* replace trailing space by newline */
 464         buf[len - 1] = '\n';
 465
 466         return len;
 467 }
 468
 469 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
 470
 471 static struct attribute *vf610_attributes[] = {
 472         &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
 473         NULL
 474 };
 475
 476 static const struct attribute_group vf610_attribute_group = {
 477         .attrs = vf610_attributes,
 478 };
 479
 480 static int vf610_read_raw(struct iio_dev *indio_dev,
 481                         struct iio_chan_spec const *chan,
 482                         int *val,
 483                         int *val2,
 484                         long mask)
 485 {
 486         struct vf610_adc *info = iio_priv(indio_dev);
 487         unsigned int hc_cfg;
 488         long ret;
 489
 490         switch (mask) {
 491         case IIO_CHAN_INFO_RAW:
 492         case IIO_CHAN_INFO_PROCESSED:
 493                 mutex_lock(&indio_dev->mlock);
 494                 reinit_completion(&info->completion);
 495
 496                 hc_cfg = VF610_ADC_ADCHC(chan->channel);
 497                 hc_cfg |= VF610_ADC_AIEN;
 498                 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 499                 ret = wait_for_completion_interruptible_timeout
 500                                 (&info->completion, VF610_ADC_TIMEOUT);
 501                 if (ret == 0) {
 502                         mutex_unlock(&indio_dev->mlock);
 503                         return -ETIMEDOUT;
 504                 }
 505                 if (ret < 0) {
 506                         mutex_unlock(&indio_dev->mlock);
 507                         return ret;
 508                 }
 509
 510                 switch (chan->type) {
 511                 case IIO_VOLTAGE:
 512                         *val = info->value;
 513                         break;
 514                 case IIO_TEMP:
 515                         /*
 516                         * Calculate in degree Celsius times 1000
 517                         * Using sensor slope of 1.84 mV/°C and
 518                         * V at 25°C of 696 mV
 519                         */
 520                         *val = 25000 - ((int)info->value - 864) * 1000000 / 1840;
 521                         break;
 522                 default:
 523                         mutex_unlock(&indio_dev->mlock);
 524                         return -EINVAL;
 525                 }
 526
 527                 mutex_unlock(&indio_dev->mlock);
 528                 return IIO_VAL_INT;
 529
 530         case IIO_CHAN_INFO_SCALE:
 531                 *val = info->vref_uv / 1000;
 532                 *val2 = info->adc_feature.res_mode;
 533                 return IIO_VAL_FRACTIONAL_LOG2;
 534
 535         case IIO_CHAN_INFO_SAMP_FREQ:
 536                 *val = info->sample_freq_avail[info->adc_feature.sample_rate];
 537                 *val2 = 0;
 538                 return IIO_VAL_INT;
 539
 540         default:
 541                 break;
 542         }
 543
 544         return -EINVAL;
 545 }
 546
 547 static int vf610_write_raw(struct iio_dev *indio_dev,
 548                         struct iio_chan_spec const *chan,
 549                         int val,
 550                         int val2,
 551                         long mask)
 552 {
 553         struct vf610_adc *info = iio_priv(indio_dev);
 554         int i;
 555
 556         switch (mask) {
 557                 case IIO_CHAN_INFO_SAMP_FREQ:
 558                         for (i = 0;
 559                                 i < ARRAY_SIZE(info->sample_freq_avail);
 560                                 i++)
 561                                 if (val == info->sample_freq_avail[i]) {
 562                                         info->adc_feature.sample_rate = i;
 563                                         vf610_adc_sample_set(info);
 564                                         return 0;
 565                                 }
 566                         break;
 567
 568                 default:
 569                         break;
 570         }
 571
 572         return -EINVAL;
 573 }
 574
 575 static int vf610_adc_reg_access(struct iio_dev *indio_dev,
 576                         unsigned reg, unsigned writeval,
 577                         unsigned *readval)
 578 {
 579         struct vf610_adc *info = iio_priv(indio_dev);
 580
 581         if ((readval == NULL) ||
 582                 (!(reg % 4) || (reg > VF610_REG_ADC_PCTL)))
 583                 return -EINVAL;
 584
 585         *readval = readl(info->regs + reg);
 586
 587         return 0;
 588 }
 589
 590 static const struct iio_info vf610_adc_iio_info = {
 591         .driver_module = THIS_MODULE,
 592         .read_raw = &vf610_read_raw,
 593         .write_raw = &vf610_write_raw,
 594         .debugfs_reg_access = &vf610_adc_reg_access,
 595         .attrs = &vf610_attribute_group,
 596 };
 597
 598 static const struct of_device_id vf610_adc_match[] = {
 599         { .compatible = "fsl,vf610-adc", },
 600         { /* sentinel */ }
 601 };
 602 MODULE_DEVICE_TABLE(of, vf610_adc_match);
 603
 604 static int vf610_adc_probe(struct platform_device *pdev)
 605 {
 606         struct vf610_adc *info;
 607         struct iio_dev *indio_dev;
 608         struct resource *mem;
 609         int irq;
 610         int ret;
 611
 612         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
 613         if (!indio_dev) {
 614                 dev_err(&pdev->dev, "Failed allocating iio device\n");
 615                 return -ENOMEM;
 616         }
 617
 618         info = iio_priv(indio_dev);
 619         info->dev = &pdev->dev;
 620
 621         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 622         info->regs = devm_ioremap_resource(&pdev->dev, mem);
 623         if (IS_ERR(info->regs))
 624                 return PTR_ERR(info->regs);
 625
 626         irq = platform_get_irq(pdev, 0);
 627         if (irq < 0) {
 628                 dev_err(&pdev->dev, "no irq resource?\n");
 629                 return irq;
 630         }
 631
 632         ret = devm_request_irq(info->dev, irq,
 633                                 vf610_adc_isr, 0,
 634                                 dev_name(&pdev->dev), info);
 635         if (ret < 0) {
 636                 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
 637                 return ret;
 638         }
 639
 640         info->clk = devm_clk_get(&pdev->dev, "adc");
 641         if (IS_ERR(info->clk)) {
 642                 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
 643                                                 PTR_ERR(info->clk));
 644                 return PTR_ERR(info->clk);
 645         }
 646
 647         info->vref = devm_regulator_get(&pdev->dev, "vref");
 648         if (IS_ERR(info->vref))
 649                 return PTR_ERR(info->vref);
 650
 651         ret = regulator_enable(info->vref);
 652         if (ret)
 653                 return ret;
 654
 655         info->vref_uv = regulator_get_voltage(info->vref);
 656
 657         platform_set_drvdata(pdev, indio_dev);
 658
 659         init_completion(&info->completion);
 660
 661         indio_dev->name = dev_name(&pdev->dev);
 662         indio_dev->dev.parent = &pdev->dev;
 663         indio_dev->dev.of_node = pdev->dev.of_node;
 664         indio_dev->info = &vf610_adc_iio_info;
 665         indio_dev->modes = INDIO_DIRECT_MODE;
 666         indio_dev->channels = vf610_adc_iio_channels;
 667         indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
 668
 669         ret = clk_prepare_enable(info->clk);
 670         if (ret) {
 671                 dev_err(&pdev->dev,
 672                         "Could not prepare or enable the clock.\n");
 673                 goto error_adc_clk_enable;
 674         }
 675
 676         vf610_adc_cfg_init(info);
 677         vf610_adc_hw_init(info);
 678
 679         ret = iio_device_register(indio_dev);
 680         if (ret) {
 681                 dev_err(&pdev->dev, "Couldn't register the device.\n");
 682                 goto error_iio_device_register;
 683         }
 684
 685         return 0;
 686
 687
 688 error_iio_device_register:
 689         clk_disable_unprepare(info->clk);
 690 error_adc_clk_enable:
 691         regulator_disable(info->vref);
 692
 693         return ret;
 694 }
 695
 696 static int vf610_adc_remove(struct platform_device *pdev)
 697 {
 698         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 699         struct vf610_adc *info = iio_priv(indio_dev);
 700
 701         iio_device_unregister(indio_dev);
 702         regulator_disable(info->vref);
 703         clk_disable_unprepare(info->clk);
 704
 705         return 0;
 706 }
 707
 708 #ifdef CONFIG_PM_SLEEP
 709 static int vf610_adc_suspend(struct device *dev)
 710 {
 711         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 712         struct vf610_adc *info = iio_priv(indio_dev);
 713         int hc_cfg;
 714
 715         /* ADC controller enters to stop mode */
 716         hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
 717         hc_cfg |= VF610_ADC_CONV_DISABLE;
 718         writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 719
 720         clk_disable_unprepare(info->clk);
 721         regulator_disable(info->vref);
 722
 723         return 0;
 724 }
 725
 726 static int vf610_adc_resume(struct device *dev)
 727 {
 728         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 729         struct vf610_adc *info = iio_priv(indio_dev);
 730         int ret;
 731
 732         ret = regulator_enable(info->vref);
 733         if (ret)
 734                 return ret;
 735
 736         ret = clk_prepare_enable(info->clk);
 737         if (ret)
 738                 goto disable_reg;
 739
 740         vf610_adc_hw_init(info);
 741
 742         return 0;
 743
 744 disable_reg:
 745         regulator_disable(info->vref);
 746         return ret;
 747 }
 748 #endif
 749
 750 static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
 751
 752 static struct platform_driver vf610_adc_driver = {
 753         .probe          = vf610_adc_probe,
 754         .remove         = vf610_adc_remove,
 755         .driver         = {
 756                 .name   = DRIVER_NAME,
 757                 .of_match_table = vf610_adc_match,
 758                 .pm     = &vf610_adc_pm_ops,
 759         },
 760 };
 761
 762 module_platform_driver(vf610_adc_driver);
 763
 764 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
 765 MODULE_DESCRIPTION("Freescale VF610 ADC driver");
 766 MODULE_LICENSE("GPL v2");