drivers/iio/frequency/adf4350.c

   1 /*
   2  * ADF4350/ADF4351 SPI Wideband Synthesizer driver
   3  *
   4  * Copyright 2012 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2.
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/sysfs.h>
  13 #include <linux/spi/spi.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/err.h>
  16 #include <linux/module.h>
  17 #include <linux/gcd.h>
  18 #include <linux/gpio.h>
  19 #include <asm/div64.h>
  20
  21 #include <linux/iio/iio.h>
  22 #include <linux/iio/sysfs.h>
  23 #include <linux/iio/frequency/adf4350.h>
  24
  25 enum {
  26         ADF4350_FREQ,
  27         ADF4350_FREQ_REFIN,
  28         ADF4350_FREQ_RESOLUTION,
  29         ADF4350_PWRDOWN,
  30 };
  31
  32 struct adf4350_state {
  33         struct spi_device               *spi;
  34         struct regulator                *reg;
  35         struct adf4350_platform_data    *pdata;
  36         unsigned long                   clkin;
  37         unsigned long                   chspc; /* Channel Spacing */
  38         unsigned long                   fpfd; /* Phase Frequency Detector */
  39         unsigned long                   min_out_freq;
  40         unsigned                        r0_fract;
  41         unsigned                        r0_int;
  42         unsigned                        r1_mod;
  43         unsigned                        r4_rf_div_sel;
  44         unsigned long                   regs[6];
  45         unsigned long                   regs_hw[6];
  46
  47         /*
  48          * DMA (thus cache coherency maintenance) requires the
  49          * transfer buffers to live in their own cache lines.
  50          */
  51         __be32                          val ____cacheline_aligned;
  52 };
  53
  54 static struct adf4350_platform_data default_pdata = {
  55         .clkin = 122880000,
  56         .channel_spacing = 10000,
  57         .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS |
  58                             ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500),
  59         .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0),
  60         .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) |
  61                             ADF4350_REG4_MUTE_TILL_LOCK_EN,
  62         .gpio_lock_detect = -1,
  63 };
  64
  65 static int adf4350_sync_config(struct adf4350_state *st)
  66 {
  67         int ret, i, doublebuf = 0;
  68
  69         for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) {
  70                 if ((st->regs_hw[i] != st->regs[i]) ||
  71                         ((i == ADF4350_REG0) && doublebuf)) {
  72
  73                         switch (i) {
  74                         case ADF4350_REG1:
  75                         case ADF4350_REG4:
  76                                 doublebuf = 1;
  77                                 break;
  78                         }
  79
  80                         st->val  = cpu_to_be32(st->regs[i] | i);
  81                         ret = spi_write(st->spi, &st->val, 4);
  82                         if (ret < 0)
  83                                 return ret;
  84                         st->regs_hw[i] = st->regs[i];
  85                         dev_dbg(&st->spi->dev, "[%d] 0x%X\n",
  86                                 i, (u32)st->regs[i] | i);
  87                 }
  88         }
  89         return 0;
  90 }
  91
  92 static int adf4350_reg_access(struct iio_dev *indio_dev,
  93                               unsigned reg, unsigned writeval,
  94                               unsigned *readval)
  95 {
  96         struct adf4350_state *st = iio_priv(indio_dev);
  97         int ret;
  98
  99         if (reg > ADF4350_REG5)
 100                 return -EINVAL;
 101
 102         mutex_lock(&indio_dev->mlock);
 103         if (readval == NULL) {
 104                 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2));
 105                 ret = adf4350_sync_config(st);
 106         } else {
 107                 *readval =  st->regs_hw[reg];
 108                 ret = 0;
 109         }
 110         mutex_unlock(&indio_dev->mlock);
 111
 112         return ret;
 113 }
 114
 115 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt)
 116 {
 117         struct adf4350_platform_data *pdata = st->pdata;
 118
 119         do {
 120                 r_cnt++;
 121                 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) /
 122                            (r_cnt * (pdata->ref_div2_en ? 2 : 1));
 123         } while (st->fpfd > ADF4350_MAX_FREQ_PFD);
 124
 125         return r_cnt;
 126 }
 127
 128 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
 129 {
 130         struct adf4350_platform_data *pdata = st->pdata;
 131         u64 tmp;
 132         u32 div_gcd, prescaler;
 133         u16 mdiv, r_cnt = 0;
 134         u8 band_sel_div;
 135
 136         if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq)
 137                 return -EINVAL;
 138
 139         if (freq > ADF4350_MAX_FREQ_45_PRESC) {
 140                 prescaler = ADF4350_REG1_PRESCALER;
 141                 mdiv = 75;
 142         } else {
 143                 prescaler = 0;
 144                 mdiv = 23;
 145         }
 146
 147         st->r4_rf_div_sel = 0;
 148
 149         while (freq < ADF4350_MIN_VCO_FREQ) {
 150                 freq <<= 1;
 151                 st->r4_rf_div_sel++;
 152         }
 153
 154         /*
 155          * Allow a predefined reference division factor
 156          * if not set, compute our own
 157          */
 158         if (pdata->ref_div_factor)
 159                 r_cnt = pdata->ref_div_factor - 1;
 160
 161         do  {
 162                 r_cnt = adf4350_tune_r_cnt(st, r_cnt);
 163
 164                 st->r1_mod = st->fpfd / st->chspc;
 165                 while (st->r1_mod > ADF4350_MAX_MODULUS) {
 166                         r_cnt = adf4350_tune_r_cnt(st, r_cnt);
 167                         st->r1_mod = st->fpfd / st->chspc;
 168                 }
 169
 170                 tmp = freq * (u64)st->r1_mod + (st->fpfd > 1);
 171                 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */
 172                 st->r0_fract = do_div(tmp, st->r1_mod);
 173                 st->r0_int = tmp;
 174         } while (mdiv > st->r0_int);
 175
 176         band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK);
 177
 178         if (st->r0_fract && st->r1_mod) {
 179                 div_gcd = gcd(st->r1_mod, st->r0_fract);
 180                 st->r1_mod /= div_gcd;
 181                 st->r0_fract /= div_gcd;
 182         } else {
 183                 st->r0_fract = 0;
 184                 st->r1_mod = 1;
 185         }
 186
 187         dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n"
 188                 "REF_DIV %d, R0_INT %d, R0_FRACT %d\n"
 189                 "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n",
 190                 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod,
 191                 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5",
 192                 band_sel_div);
 193
 194         st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) |
 195                                  ADF4350_REG0_FRACT(st->r0_fract);
 196
 197         st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(0) |
 198                                  ADF4350_REG1_MOD(st->r1_mod) |
 199                                  prescaler;
 200
 201         st->regs[ADF4350_REG2] =
 202                 ADF4350_REG2_10BIT_R_CNT(r_cnt) |
 203                 ADF4350_REG2_DOUBLE_BUFF_EN |
 204                 (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) |
 205                 (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) |
 206                 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS |
 207                 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N |
 208                 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) |
 209                 ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x9)));
 210
 211         st->regs[ADF4350_REG3] = pdata->r3_user_settings &
 212                                  (ADF4350_REG3_12BIT_CLKDIV(0xFFF) |
 213                                  ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) |
 214                                  ADF4350_REG3_12BIT_CSR_EN |
 215                                  ADF4351_REG3_CHARGE_CANCELLATION_EN |
 216                                  ADF4351_REG3_ANTI_BACKLASH_3ns_EN |
 217                                  ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH);
 218
 219         st->regs[ADF4350_REG4] =
 220                 ADF4350_REG4_FEEDBACK_FUND |
 221                 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) |
 222                 ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) |
 223                 ADF4350_REG4_RF_OUT_EN |
 224                 (pdata->r4_user_settings &
 225                 (ADF4350_REG4_OUTPUT_PWR(0x3) |
 226                 ADF4350_REG4_AUX_OUTPUT_PWR(0x3) |
 227                 ADF4350_REG4_AUX_OUTPUT_EN |
 228                 ADF4350_REG4_AUX_OUTPUT_FUND |
 229                 ADF4350_REG4_MUTE_TILL_LOCK_EN));
 230
 231         st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL;
 232
 233         return adf4350_sync_config(st);
 234 }
 235
 236 static ssize_t adf4350_write(struct iio_dev *indio_dev,
 237                                     uintptr_t private,
 238                                     const struct iio_chan_spec *chan,
 239                                     const char *buf, size_t len)
 240 {
 241         struct adf4350_state *st = iio_priv(indio_dev);
 242         unsigned long long readin;
 243         int ret;
 244
 245         ret = kstrtoull(buf, 10, &readin);
 246         if (ret)
 247                 return ret;
 248
 249         mutex_lock(&indio_dev->mlock);
 250         switch ((u32)private) {
 251         case ADF4350_FREQ:
 252                 ret = adf4350_set_freq(st, readin);
 253                 break;
 254         case ADF4350_FREQ_REFIN:
 255                 if (readin > ADF4350_MAX_FREQ_REFIN)
 256                         ret = -EINVAL;
 257                 else
 258                         st->clkin = readin;
 259                 break;
 260         case ADF4350_FREQ_RESOLUTION:
 261                 if (readin == 0)
 262                         ret = -EINVAL;
 263                 else
 264                         st->chspc = readin;
 265                 break;
 266         case ADF4350_PWRDOWN:
 267                 if (readin)
 268                         st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
 269                 else
 270                         st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;
 271
 272                 adf4350_sync_config(st);
 273                 break;
 274         default:
 275                 ret = -EINVAL;
 276         }
 277         mutex_unlock(&indio_dev->mlock);
 278
 279         return ret ? ret : len;
 280 }
 281
 282 static ssize_t adf4350_read(struct iio_dev *indio_dev,
 283                                    uintptr_t private,
 284                                    const struct iio_chan_spec *chan,
 285                                    char *buf)
 286 {
 287         struct adf4350_state *st = iio_priv(indio_dev);
 288         unsigned long long val;
 289         int ret = 0;
 290
 291         mutex_lock(&indio_dev->mlock);
 292         switch ((u32)private) {
 293         case ADF4350_FREQ:
 294                 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) *
 295                         (u64)st->fpfd;
 296                 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel));
 297                 /* PLL unlocked? return error */
 298                 if (gpio_is_valid(st->pdata->gpio_lock_detect))
 299                         if (!gpio_get_value(st->pdata->gpio_lock_detect)) {
 300                                 dev_dbg(&st->spi->dev, "PLL un-locked\n");
 301                                 ret = -EBUSY;
 302                         }
 303                 break;
 304         case ADF4350_FREQ_REFIN:
 305                 val = st->clkin;
 306                 break;
 307         case ADF4350_FREQ_RESOLUTION:
 308                 val = st->chspc;
 309                 break;
 310         case ADF4350_PWRDOWN:
 311                 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
 312                 break;
 313         default:
 314                 ret = -EINVAL;
 315         }
 316         mutex_unlock(&indio_dev->mlock);
 317
 318         return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
 319 }
 320
 321 #define _ADF4350_EXT_INFO(_name, _ident) { \
 322         .name = _name, \
 323         .read = adf4350_read, \
 324         .write = adf4350_write, \
 325         .private = _ident, \
 326 }
 327
 328 static const struct iio_chan_spec_ext_info adf4350_ext_info[] = {
 329         /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
 330          * values > 2^32 in order to support the entire frequency range
 331          * in Hz. Using scale is a bit ugly.
 332          */
 333         _ADF4350_EXT_INFO("frequency", ADF4350_FREQ),
 334         _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION),
 335         _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN),
 336         _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN),
 337         { },
 338 };
 339
 340 static const struct iio_chan_spec adf4350_chan = {
 341         .type = IIO_ALTVOLTAGE,
 342         .indexed = 1,
 343         .output = 1,
 344         .ext_info = adf4350_ext_info,
 345 };
 346
 347 static const struct iio_info adf4350_info = {
 348         .debugfs_reg_access = &adf4350_reg_access,
 349         .driver_module = THIS_MODULE,
 350 };
 351
 352 static int __devinit adf4350_probe(struct spi_device *spi)
 353 {
 354         struct adf4350_platform_data *pdata = spi->dev.platform_data;
 355         struct iio_dev *indio_dev;
 356         struct adf4350_state *st;
 357         int ret;
 358
 359         if (!pdata) {
 360                 dev_warn(&spi->dev, "no platform data? using default\n");
 361
 362                 pdata = &default_pdata;
 363         }
 364
 365         indio_dev = iio_device_alloc(sizeof(*st));
 366         if (indio_dev == NULL)
 367                 return -ENOMEM;
 368
 369         st = iio_priv(indio_dev);
 370
 371         st->reg = regulator_get(&spi->dev, "vcc");
 372         if (!IS_ERR(st->reg)) {
 373                 ret = regulator_enable(st->reg);
 374                 if (ret)
 375                         goto error_put_reg;
 376         }
 377
 378         spi_set_drvdata(spi, indio_dev);
 379         st->spi = spi;
 380         st->pdata = pdata;
 381
 382         indio_dev->dev.parent = &spi->dev;
 383         indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
 384                 spi_get_device_id(spi)->name;
 385
 386         indio_dev->info = &adf4350_info;
 387         indio_dev->modes = INDIO_DIRECT_MODE;
 388         indio_dev->channels = &adf4350_chan;
 389         indio_dev->num_channels = 1;
 390
 391         st->chspc = pdata->channel_spacing;
 392         st->clkin = pdata->clkin;
 393
 394         st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ?
 395                 ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ;
 396
 397         memset(st->regs_hw, 0xFF, sizeof(st->regs_hw));
 398
 399         if (gpio_is_valid(pdata->gpio_lock_detect)) {
 400                 ret = gpio_request(pdata->gpio_lock_detect, indio_dev->name);
 401                 if (ret) {
 402                         dev_err(&spi->dev, "fail to request lock detect GPIO-%d",
 403                                 pdata->gpio_lock_detect);
 404                         goto error_disable_reg;
 405                 }
 406                 gpio_direction_input(pdata->gpio_lock_detect);
 407         }
 408
 409         if (pdata->power_up_frequency) {
 410                 ret = adf4350_set_freq(st, pdata->power_up_frequency);
 411                 if (ret)
 412                         goto error_free_gpio;
 413         }
 414
 415         ret = iio_device_register(indio_dev);
 416         if (ret)
 417                 goto error_free_gpio;
 418
 419         return 0;
 420
 421 error_free_gpio:
 422         if (gpio_is_valid(pdata->gpio_lock_detect))
 423                 gpio_free(pdata->gpio_lock_detect);
 424
 425 error_disable_reg:
 426         if (!IS_ERR(st->reg))
 427                 regulator_disable(st->reg);
 428 error_put_reg:
 429         if (!IS_ERR(st->reg))
 430                 regulator_put(st->reg);
 431
 432         iio_device_free(indio_dev);
 433
 434         return ret;
 435 }
 436
 437 static int __devexit adf4350_remove(struct spi_device *spi)
 438 {
 439         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 440         struct adf4350_state *st = iio_priv(indio_dev);
 441         struct regulator *reg = st->reg;
 442
 443         st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
 444         adf4350_sync_config(st);
 445
 446         iio_device_unregister(indio_dev);
 447
 448         if (!IS_ERR(reg)) {
 449                 regulator_disable(reg);
 450                 regulator_put(reg);
 451         }
 452
 453         if (gpio_is_valid(st->pdata->gpio_lock_detect))
 454                 gpio_free(st->pdata->gpio_lock_detect);
 455
 456         iio_device_free(indio_dev);
 457
 458         return 0;
 459 }
 460
 461 static const struct spi_device_id adf4350_id[] = {
 462         {"adf4350", 4350},
 463         {"adf4351", 4351},
 464         {}
 465 };
 466
 467 static struct spi_driver adf4350_driver = {
 468         .driver = {
 469                 .name   = "adf4350",
 470                 .owner  = THIS_MODULE,
 471         },
 472         .probe          = adf4350_probe,
 473         .remove         = __devexit_p(adf4350_remove),
 474         .id_table       = adf4350_id,
 475 };
 476 module_spi_driver(adf4350_driver);
 477
 478 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 479 MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL");
 480 MODULE_LICENSE("GPL v2");