drivers/iio/frequency/adf4350.c

   1 /*
   2  * ADF4350/ADF4351 SPI Wideband Synthesizer driver
   3  *
   4  * Copyright 2012-2013 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2.
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/sysfs.h>
  13 #include <linux/spi/spi.h>
  14 #include <linux/regulator/consumer.h>
  15 #include <linux/err.h>
  16 #include <linux/module.h>
  17 #include <linux/gcd.h>
  18 #include <linux/gpio.h>
  19 #include <asm/div64.h>
  20 #include <linux/clk.h>
  21 #include <linux/of.h>
  22 #include <linux/of_gpio.h>
  23
  24 #include <linux/iio/iio.h>
  25 #include <linux/iio/sysfs.h>
  26 #include <linux/iio/frequency/adf4350.h>
  27
  28 enum {
  29         ADF4350_FREQ,
  30         ADF4350_FREQ_REFIN,
  31         ADF4350_FREQ_RESOLUTION,
  32         ADF4350_PWRDOWN,
  33 };
  34
  35 struct adf4350_state {
  36         struct spi_device               *spi;
  37         struct regulator                *reg;
  38         struct adf4350_platform_data    *pdata;
  39         struct clk                      *clk;
  40         unsigned long                   clkin;
  41         unsigned long                   chspc; /* Channel Spacing */
  42         unsigned long                   fpfd; /* Phase Frequency Detector */
  43         unsigned long                   min_out_freq;
  44         unsigned                        r0_fract;
  45         unsigned                        r0_int;
  46         unsigned                        r1_mod;
  47         unsigned                        r4_rf_div_sel;
  48         unsigned long                   regs[6];
  49         unsigned long                   regs_hw[6];
  50         unsigned long long              freq_req;
  51         /*
  52          * DMA (thus cache coherency maintenance) requires the
  53          * transfer buffers to live in their own cache lines.
  54          */
  55         __be32                          val ____cacheline_aligned;
  56 };
  57
  58 static struct adf4350_platform_data default_pdata = {
  59         .channel_spacing = 10000,
  60         .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS |
  61                             ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500),
  62         .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0),
  63         .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) |
  64                             ADF4350_REG4_MUTE_TILL_LOCK_EN,
  65         .gpio_lock_detect = -1,
  66 };
  67
  68 static int adf4350_sync_config(struct adf4350_state *st)
  69 {
  70         int ret, i, doublebuf = 0;
  71
  72         for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) {
  73                 if ((st->regs_hw[i] != st->regs[i]) ||
  74                         ((i == ADF4350_REG0) && doublebuf)) {
  75                         switch (i) {
  76                         case ADF4350_REG1:
  77                         case ADF4350_REG4:
  78                                 doublebuf = 1;
  79                                 break;
  80                         }
  81
  82                         st->val  = cpu_to_be32(st->regs[i] | i);
  83                         ret = spi_write(st->spi, &st->val, 4);
  84                         if (ret < 0)
  85                                 return ret;
  86                         st->regs_hw[i] = st->regs[i];
  87                         dev_dbg(&st->spi->dev, "[%d] 0x%X\n",
  88                                 i, (u32)st->regs[i] | i);
  89                 }
  90         }
  91         return 0;
  92 }
  93
  94 static int adf4350_reg_access(struct iio_dev *indio_dev,
  95                               unsigned reg, unsigned writeval,
  96                               unsigned *readval)
  97 {
  98         struct adf4350_state *st = iio_priv(indio_dev);
  99         int ret;
 100
 101         if (reg > ADF4350_REG5)
 102                 return -EINVAL;
 103
 104         mutex_lock(&indio_dev->mlock);
 105         if (readval == NULL) {
 106                 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2));
 107                 ret = adf4350_sync_config(st);
 108         } else {
 109                 *readval =  st->regs_hw[reg];
 110                 ret = 0;
 111         }
 112         mutex_unlock(&indio_dev->mlock);
 113
 114         return ret;
 115 }
 116
 117 static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt)
 118 {
 119         struct adf4350_platform_data *pdata = st->pdata;
 120
 121         do {
 122                 r_cnt++;
 123                 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) /
 124                            (r_cnt * (pdata->ref_div2_en ? 2 : 1));
 125         } while (st->fpfd > ADF4350_MAX_FREQ_PFD);
 126
 127         return r_cnt;
 128 }
 129
 130 static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
 131 {
 132         struct adf4350_platform_data *pdata = st->pdata;
 133         u64 tmp;
 134         u32 div_gcd, prescaler, chspc;
 135         u16 mdiv, r_cnt = 0;
 136         u8 band_sel_div;
 137
 138         if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq)
 139                 return -EINVAL;
 140
 141         if (freq > ADF4350_MAX_FREQ_45_PRESC) {
 142                 prescaler = ADF4350_REG1_PRESCALER;
 143                 mdiv = 75;
 144         } else {
 145                 prescaler = 0;
 146                 mdiv = 23;
 147         }
 148
 149         st->r4_rf_div_sel = 0;
 150
 151         while (freq < ADF4350_MIN_VCO_FREQ) {
 152                 freq <<= 1;
 153                 st->r4_rf_div_sel++;
 154         }
 155
 156         /*
 157          * Allow a predefined reference division factor
 158          * if not set, compute our own
 159          */
 160         if (pdata->ref_div_factor)
 161                 r_cnt = pdata->ref_div_factor - 1;
 162
 163         chspc = st->chspc;
 164
 165         do  {
 166                 do {
 167                         do {
 168                                 r_cnt = adf4350_tune_r_cnt(st, r_cnt);
 169                                 st->r1_mod = st->fpfd / chspc;
 170                                 if (r_cnt > ADF4350_MAX_R_CNT) {
 171                                         /* try higher spacing values */
 172                                         chspc++;
 173                                         r_cnt = 0;
 174                                 }
 175                         } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt);
 176                 } while (r_cnt == 0);
 177
 178                 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1);
 179                 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */
 180                 st->r0_fract = do_div(tmp, st->r1_mod);
 181                 st->r0_int = tmp;
 182         } while (mdiv > st->r0_int);
 183
 184         band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK);
 185
 186         if (st->r0_fract && st->r1_mod) {
 187                 div_gcd = gcd(st->r1_mod, st->r0_fract);
 188                 st->r1_mod /= div_gcd;
 189                 st->r0_fract /= div_gcd;
 190         } else {
 191                 st->r0_fract = 0;
 192                 st->r1_mod = 1;
 193         }
 194
 195         dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n"
 196                 "REF_DIV %d, R0_INT %d, R0_FRACT %d\n"
 197                 "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n",
 198                 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod,
 199                 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5",
 200                 band_sel_div);
 201
 202         st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) |
 203                                  ADF4350_REG0_FRACT(st->r0_fract);
 204
 205         st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) |
 206                                  ADF4350_REG1_MOD(st->r1_mod) |
 207                                  prescaler;
 208
 209         st->regs[ADF4350_REG2] =
 210                 ADF4350_REG2_10BIT_R_CNT(r_cnt) |
 211                 ADF4350_REG2_DOUBLE_BUFF_EN |
 212                 (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) |
 213                 (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) |
 214                 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS |
 215                 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N |
 216                 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) |
 217                 ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3)));
 218
 219         st->regs[ADF4350_REG3] = pdata->r3_user_settings &
 220                                  (ADF4350_REG3_12BIT_CLKDIV(0xFFF) |
 221                                  ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) |
 222                                  ADF4350_REG3_12BIT_CSR_EN |
 223                                  ADF4351_REG3_CHARGE_CANCELLATION_EN |
 224                                  ADF4351_REG3_ANTI_BACKLASH_3ns_EN |
 225                                  ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH);
 226
 227         st->regs[ADF4350_REG4] =
 228                 ADF4350_REG4_FEEDBACK_FUND |
 229                 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) |
 230                 ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) |
 231                 ADF4350_REG4_RF_OUT_EN |
 232                 (pdata->r4_user_settings &
 233                 (ADF4350_REG4_OUTPUT_PWR(0x3) |
 234                 ADF4350_REG4_AUX_OUTPUT_PWR(0x3) |
 235                 ADF4350_REG4_AUX_OUTPUT_EN |
 236                 ADF4350_REG4_AUX_OUTPUT_FUND |
 237                 ADF4350_REG4_MUTE_TILL_LOCK_EN));
 238
 239         st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL;
 240         st->freq_req = freq;
 241
 242         return adf4350_sync_config(st);
 243 }
 244
 245 static ssize_t adf4350_write(struct iio_dev *indio_dev,
 246                                     uintptr_t private,
 247                                     const struct iio_chan_spec *chan,
 248                                     const char *buf, size_t len)
 249 {
 250         struct adf4350_state *st = iio_priv(indio_dev);
 251         unsigned long long readin;
 252         unsigned long tmp;
 253         int ret;
 254
 255         ret = kstrtoull(buf, 10, &readin);
 256         if (ret)
 257                 return ret;
 258
 259         mutex_lock(&indio_dev->mlock);
 260         switch ((u32)private) {
 261         case ADF4350_FREQ:
 262                 ret = adf4350_set_freq(st, readin);
 263                 break;
 264         case ADF4350_FREQ_REFIN:
 265                 if (readin > ADF4350_MAX_FREQ_REFIN) {
 266                         ret = -EINVAL;
 267                         break;
 268                 }
 269
 270                 if (st->clk) {
 271                         tmp = clk_round_rate(st->clk, readin);
 272                         if (tmp != readin) {
 273                                 ret = -EINVAL;
 274                                 break;
 275                         }
 276                         ret = clk_set_rate(st->clk, tmp);
 277                         if (ret < 0)
 278                                 break;
 279                 }
 280                 st->clkin = readin;
 281                 ret = adf4350_set_freq(st, st->freq_req);
 282                 break;
 283         case ADF4350_FREQ_RESOLUTION:
 284                 if (readin == 0)
 285                         ret = -EINVAL;
 286                 else
 287                         st->chspc = readin;
 288                 break;
 289         case ADF4350_PWRDOWN:
 290                 if (readin)
 291                         st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
 292                 else
 293                         st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;
 294
 295                 adf4350_sync_config(st);
 296                 break;
 297         default:
 298                 ret = -EINVAL;
 299         }
 300         mutex_unlock(&indio_dev->mlock);
 301
 302         return ret ? ret : len;
 303 }
 304
 305 static ssize_t adf4350_read(struct iio_dev *indio_dev,
 306                                    uintptr_t private,
 307                                    const struct iio_chan_spec *chan,
 308                                    char *buf)
 309 {
 310         struct adf4350_state *st = iio_priv(indio_dev);
 311         unsigned long long val;
 312         int ret = 0;
 313
 314         mutex_lock(&indio_dev->mlock);
 315         switch ((u32)private) {
 316         case ADF4350_FREQ:
 317                 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) *
 318                         (u64)st->fpfd;
 319                 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel));
 320                 /* PLL unlocked? return error */
 321                 if (gpio_is_valid(st->pdata->gpio_lock_detect))
 322                         if (!gpio_get_value(st->pdata->gpio_lock_detect)) {
 323                                 dev_dbg(&st->spi->dev, "PLL un-locked\n");
 324                                 ret = -EBUSY;
 325                         }
 326                 break;
 327         case ADF4350_FREQ_REFIN:
 328                 if (st->clk)
 329                         st->clkin = clk_get_rate(st->clk);
 330
 331                 val = st->clkin;
 332                 break;
 333         case ADF4350_FREQ_RESOLUTION:
 334                 val = st->chspc;
 335                 break;
 336         case ADF4350_PWRDOWN:
 337                 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
 338                 break;
 339         default:
 340                 ret = -EINVAL;
 341                 val = 0;
 342         }
 343         mutex_unlock(&indio_dev->mlock);
 344
 345         return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
 346 }
 347
 348 #define _ADF4350_EXT_INFO(_name, _ident) { \
 349         .name = _name, \
 350         .read = adf4350_read, \
 351         .write = adf4350_write, \
 352         .private = _ident, \
 353         .shared = IIO_SEPARATE, \
 354 }
 355
 356 static const struct iio_chan_spec_ext_info adf4350_ext_info[] = {
 357         /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
 358          * values > 2^32 in order to support the entire frequency range
 359          * in Hz. Using scale is a bit ugly.
 360          */
 361         _ADF4350_EXT_INFO("frequency", ADF4350_FREQ),
 362         _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION),
 363         _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN),
 364         _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN),
 365         { },
 366 };
 367
 368 static const struct iio_chan_spec adf4350_chan = {
 369         .type = IIO_ALTVOLTAGE,
 370         .indexed = 1,
 371         .output = 1,
 372         .ext_info = adf4350_ext_info,
 373 };
 374
 375 static const struct iio_info adf4350_info = {
 376         .debugfs_reg_access = &adf4350_reg_access,
 377         .driver_module = THIS_MODULE,
 378 };
 379
 380 #ifdef CONFIG_OF
 381 static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev)
 382 {
 383         struct device_node *np = dev->of_node;
 384         struct adf4350_platform_data *pdata;
 385         unsigned int tmp;
 386         int ret;
 387
 388         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 389         if (!pdata)
 390                 return NULL;
 391
 392         strncpy(&pdata->name[0], np->name, SPI_NAME_SIZE - 1);
 393
 394         tmp = 10000;
 395         of_property_read_u32(np, "adi,channel-spacing", &tmp);
 396         pdata->channel_spacing = tmp;
 397
 398         tmp = 0;
 399         of_property_read_u32(np, "adi,power-up-frequency", &tmp);
 400         pdata->power_up_frequency = tmp;
 401
 402         tmp = 0;
 403         of_property_read_u32(np, "adi,reference-div-factor", &tmp);
 404         pdata->ref_div_factor = tmp;
 405
 406         ret = of_get_gpio(np, 0);
 407         if (ret < 0)
 408                 pdata->gpio_lock_detect = -1;
 409         else
 410                 pdata->gpio_lock_detect = ret;
 411
 412         pdata->ref_doubler_en = of_property_read_bool(np,
 413                         "adi,reference-doubler-enable");
 414         pdata->ref_div2_en = of_property_read_bool(np,
 415                         "adi,reference-div2-enable");
 416
 417         /* r2_user_settings */
 418         pdata->r2_user_settings = of_property_read_bool(np,
 419                         "adi,phase-detector-polarity-positive-enable") ?
 420                         ADF4350_REG2_PD_POLARITY_POS : 0;
 421         pdata->r2_user_settings |= of_property_read_bool(np,
 422                         "adi,lock-detect-precision-6ns-enable") ?
 423                         ADF4350_REG2_LDP_6ns : 0;
 424         pdata->r2_user_settings |= of_property_read_bool(np,
 425                         "adi,lock-detect-function-integer-n-enable") ?
 426                         ADF4350_REG2_LDF_INT_N : 0;
 427
 428         tmp = 2500;
 429         of_property_read_u32(np, "adi,charge-pump-current", &tmp);
 430         pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp);
 431
 432         tmp = 0;
 433         of_property_read_u32(np, "adi,muxout-select", &tmp);
 434         pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp);
 435
 436         pdata->r2_user_settings |= of_property_read_bool(np,
 437                         "adi,low-spur-mode-enable") ?
 438                         ADF4350_REG2_NOISE_MODE(0x3) : 0;
 439
 440         /* r3_user_settings */
 441
 442         pdata->r3_user_settings = of_property_read_bool(np,
 443                         "adi,cycle-slip-reduction-enable") ?
 444                         ADF4350_REG3_12BIT_CSR_EN : 0;
 445         pdata->r3_user_settings |= of_property_read_bool(np,
 446                         "adi,charge-cancellation-enable") ?
 447                         ADF4351_REG3_CHARGE_CANCELLATION_EN : 0;
 448
 449         pdata->r3_user_settings |= of_property_read_bool(np,
 450                         "adi,anti-backlash-3ns-enable") ?
 451                         ADF4351_REG3_ANTI_BACKLASH_3ns_EN : 0;
 452         pdata->r3_user_settings |= of_property_read_bool(np,
 453                         "adi,band-select-clock-mode-high-enable") ?
 454                         ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH : 0;
 455
 456         tmp = 0;
 457         of_property_read_u32(np, "adi,12bit-clk-divider", &tmp);
 458         pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp);
 459
 460         tmp = 0;
 461         of_property_read_u32(np, "adi,clk-divider-mode", &tmp);
 462         pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp);
 463
 464         /* r4_user_settings */
 465
 466         pdata->r4_user_settings = of_property_read_bool(np,
 467                         "adi,aux-output-enable") ?
 468                         ADF4350_REG4_AUX_OUTPUT_EN : 0;
 469         pdata->r4_user_settings |= of_property_read_bool(np,
 470                         "adi,aux-output-fundamental-enable") ?
 471                         ADF4350_REG4_AUX_OUTPUT_FUND : 0;
 472         pdata->r4_user_settings |= of_property_read_bool(np,
 473                         "adi,mute-till-lock-enable") ?
 474                         ADF4350_REG4_MUTE_TILL_LOCK_EN : 0;
 475
 476         tmp = 0;
 477         of_property_read_u32(np, "adi,output-power", &tmp);
 478         pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp);
 479
 480         tmp = 0;
 481         of_property_read_u32(np, "adi,aux-output-power", &tmp);
 482         pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp);
 483
 484         return pdata;
 485 }
 486 #else
 487 static
 488 struct adf4350_platform_data *adf4350_parse_dt(struct device *dev)
 489 {
 490         return NULL;
 491 }
 492 #endif
 493
 494 static int adf4350_probe(struct spi_device *spi)
 495 {
 496         struct adf4350_platform_data *pdata;
 497         struct iio_dev *indio_dev;
 498         struct adf4350_state *st;
 499         struct clk *clk = NULL;
 500         int ret;
 501
 502         if (spi->dev.of_node) {
 503                 pdata = adf4350_parse_dt(&spi->dev);
 504                 if (pdata == NULL)
 505                         return -EINVAL;
 506         } else {
 507                 pdata = spi->dev.platform_data;
 508         }
 509
 510         if (!pdata) {
 511                 dev_warn(&spi->dev, "no platform data? using default\n");
 512                 pdata = &default_pdata;
 513         }
 514
 515         if (!pdata->clkin) {
 516                 clk = devm_clk_get(&spi->dev, "clkin");
 517                 if (IS_ERR(clk))
 518                         return -EPROBE_DEFER;
 519
 520                 ret = clk_prepare_enable(clk);
 521                 if (ret < 0)
 522                         return ret;
 523         }
 524
 525         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 526         if (indio_dev == NULL) {
 527                 ret =  -ENOMEM;
 528                 goto error_disable_clk;
 529         }
 530
 531         st = iio_priv(indio_dev);
 532
 533         st->reg = devm_regulator_get(&spi->dev, "vcc");
 534         if (!IS_ERR(st->reg)) {
 535                 ret = regulator_enable(st->reg);
 536                 if (ret)
 537                         goto error_disable_clk;
 538         }
 539
 540         spi_set_drvdata(spi, indio_dev);
 541         st->spi = spi;
 542         st->pdata = pdata;
 543
 544         indio_dev->dev.parent = &spi->dev;
 545         indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
 546                 spi_get_device_id(spi)->name;
 547
 548         indio_dev->info = &adf4350_info;
 549         indio_dev->modes = INDIO_DIRECT_MODE;
 550         indio_dev->channels = &adf4350_chan;
 551         indio_dev->num_channels = 1;
 552
 553         st->chspc = pdata->channel_spacing;
 554         if (clk) {
 555                 st->clk = clk;
 556                 st->clkin = clk_get_rate(clk);
 557         } else {
 558                 st->clkin = pdata->clkin;
 559         }
 560
 561         st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ?
 562                 ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ;
 563
 564         memset(st->regs_hw, 0xFF, sizeof(st->regs_hw));
 565
 566         if (gpio_is_valid(pdata->gpio_lock_detect)) {
 567                 ret = devm_gpio_request(&spi->dev, pdata->gpio_lock_detect,
 568                                         indio_dev->name);
 569                 if (ret) {
 570                         dev_err(&spi->dev, "fail to request lock detect GPIO-%d",
 571                                 pdata->gpio_lock_detect);
 572                         goto error_disable_reg;
 573                 }
 574                 gpio_direction_input(pdata->gpio_lock_detect);
 575         }
 576
 577         if (pdata->power_up_frequency) {
 578                 ret = adf4350_set_freq(st, pdata->power_up_frequency);
 579                 if (ret)
 580                         goto error_disable_reg;
 581         }
 582
 583         ret = iio_device_register(indio_dev);
 584         if (ret)
 585                 goto error_disable_reg;
 586
 587         return 0;
 588
 589 error_disable_reg:
 590         if (!IS_ERR(st->reg))
 591                 regulator_disable(st->reg);
 592 error_disable_clk:
 593         if (clk)
 594                 clk_disable_unprepare(clk);
 595
 596         return ret;
 597 }
 598
 599 static int adf4350_remove(struct spi_device *spi)
 600 {
 601         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 602         struct adf4350_state *st = iio_priv(indio_dev);
 603         struct regulator *reg = st->reg;
 604
 605         st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
 606         adf4350_sync_config(st);
 607
 608         iio_device_unregister(indio_dev);
 609
 610         if (st->clk)
 611                 clk_disable_unprepare(st->clk);
 612
 613         if (!IS_ERR(reg))
 614                 regulator_disable(reg);
 615
 616         return 0;
 617 }
 618
 619 static const struct of_device_id adf4350_of_match[] = {
 620         { .compatible = "adi,adf4350", },
 621         { .compatible = "adi,adf4351", },
 622         { /* sentinel */ },
 623 };
 624 MODULE_DEVICE_TABLE(of, adf4350_of_match);
 625
 626 static const struct spi_device_id adf4350_id[] = {
 627         {"adf4350", 4350},
 628         {"adf4351", 4351},
 629         {}
 630 };
 631 MODULE_DEVICE_TABLE(spi, adf4350_id);
 632
 633 static struct spi_driver adf4350_driver = {
 634         .driver = {
 635                 .name   = "adf4350",
 636                 .of_match_table = of_match_ptr(adf4350_of_match),
 637                 .owner  = THIS_MODULE,
 638         },
 639         .probe          = adf4350_probe,
 640         .remove         = adf4350_remove,
 641         .id_table       = adf4350_id,
 642 };
 643 module_spi_driver(adf4350_driver);
 644
 645 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
 646 MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL");
 647 MODULE_LICENSE("GPL v2");