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ea13efddf175b818747af7db1f024da9e2384639
[deliverable/linux.git] / drivers / infiniband / hw / ehca / ehca_qp.c
1 /*
2 * IBM eServer eHCA Infiniband device driver for Linux on POWER
3 *
4 * QP functions
5 *
6 * Authors: Joachim Fenkes <fenkes@de.ibm.com>
7 * Stefan Roscher <stefan.roscher@de.ibm.com>
8 * Waleri Fomin <fomin@de.ibm.com>
9 * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
10 * Reinhard Ernst <rernst@de.ibm.com>
11 * Heiko J Schick <schickhj@de.ibm.com>
12 *
13 * Copyright (c) 2005 IBM Corporation
14 *
15 * All rights reserved.
16 *
17 * This source code is distributed under a dual license of GPL v2.0 and OpenIB
18 * BSD.
19 *
20 * OpenIB BSD License
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
24 *
25 * Redistributions of source code must retain the above copyright notice, this
26 * list of conditions and the following disclaimer.
27 *
28 * Redistributions in binary form must reproduce the above copyright notice,
29 * this list of conditions and the following disclaimer in the documentation
30 * and/or other materials
31 * provided with the distribution.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
37 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
40 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
41 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 * POSSIBILITY OF SUCH DAMAGE.
44 */
45
46 #include "ehca_classes.h"
47 #include "ehca_tools.h"
48 #include "ehca_qes.h"
49 #include "ehca_iverbs.h"
50 #include "hcp_if.h"
51 #include "hipz_fns.h"
52
53 static struct kmem_cache *qp_cache;
54
55 /*
56 * attributes not supported by query qp
57 */
58 #define QP_ATTR_QUERY_NOT_SUPPORTED (IB_QP_MAX_DEST_RD_ATOMIC | \
59 IB_QP_MAX_QP_RD_ATOMIC | \
60 IB_QP_ACCESS_FLAGS | \
61 IB_QP_EN_SQD_ASYNC_NOTIFY)
62
63 /*
64 * ehca (internal) qp state values
65 */
66 enum ehca_qp_state {
67 EHCA_QPS_RESET = 1,
68 EHCA_QPS_INIT = 2,
69 EHCA_QPS_RTR = 3,
70 EHCA_QPS_RTS = 5,
71 EHCA_QPS_SQD = 6,
72 EHCA_QPS_SQE = 8,
73 EHCA_QPS_ERR = 128
74 };
75
76 /*
77 * qp state transitions as defined by IB Arch Rel 1.1 page 431
78 */
79 enum ib_qp_statetrans {
80 IB_QPST_ANY2RESET,
81 IB_QPST_ANY2ERR,
82 IB_QPST_RESET2INIT,
83 IB_QPST_INIT2RTR,
84 IB_QPST_INIT2INIT,
85 IB_QPST_RTR2RTS,
86 IB_QPST_RTS2SQD,
87 IB_QPST_RTS2RTS,
88 IB_QPST_SQD2RTS,
89 IB_QPST_SQE2RTS,
90 IB_QPST_SQD2SQD,
91 IB_QPST_MAX /* nr of transitions, this must be last!!! */
92 };
93
94 /*
95 * ib2ehca_qp_state maps IB to ehca qp_state
96 * returns ehca qp state corresponding to given ib qp state
97 */
98 static inline enum ehca_qp_state ib2ehca_qp_state(enum ib_qp_state ib_qp_state)
99 {
100 switch (ib_qp_state) {
101 case IB_QPS_RESET:
102 return EHCA_QPS_RESET;
103 case IB_QPS_INIT:
104 return EHCA_QPS_INIT;
105 case IB_QPS_RTR:
106 return EHCA_QPS_RTR;
107 case IB_QPS_RTS:
108 return EHCA_QPS_RTS;
109 case IB_QPS_SQD:
110 return EHCA_QPS_SQD;
111 case IB_QPS_SQE:
112 return EHCA_QPS_SQE;
113 case IB_QPS_ERR:
114 return EHCA_QPS_ERR;
115 default:
116 ehca_gen_err("invalid ib_qp_state=%x", ib_qp_state);
117 return -EINVAL;
118 }
119 }
120
121 /*
122 * ehca2ib_qp_state maps ehca to IB qp_state
123 * returns ib qp state corresponding to given ehca qp state
124 */
125 static inline enum ib_qp_state ehca2ib_qp_state(enum ehca_qp_state
126 ehca_qp_state)
127 {
128 switch (ehca_qp_state) {
129 case EHCA_QPS_RESET:
130 return IB_QPS_RESET;
131 case EHCA_QPS_INIT:
132 return IB_QPS_INIT;
133 case EHCA_QPS_RTR:
134 return IB_QPS_RTR;
135 case EHCA_QPS_RTS:
136 return IB_QPS_RTS;
137 case EHCA_QPS_SQD:
138 return IB_QPS_SQD;
139 case EHCA_QPS_SQE:
140 return IB_QPS_SQE;
141 case EHCA_QPS_ERR:
142 return IB_QPS_ERR;
143 default:
144 ehca_gen_err("invalid ehca_qp_state=%x", ehca_qp_state);
145 return -EINVAL;
146 }
147 }
148
149 /*
150 * ehca_qp_type used as index for req_attr and opt_attr of
151 * struct ehca_modqp_statetrans
152 */
153 enum ehca_qp_type {
154 QPT_RC = 0,
155 QPT_UC = 1,
156 QPT_UD = 2,
157 QPT_SQP = 3,
158 QPT_MAX
159 };
160
161 /*
162 * ib2ehcaqptype maps Ib to ehca qp_type
163 * returns ehca qp type corresponding to ib qp type
164 */
165 static inline enum ehca_qp_type ib2ehcaqptype(enum ib_qp_type ibqptype)
166 {
167 switch (ibqptype) {
168 case IB_QPT_SMI:
169 case IB_QPT_GSI:
170 return QPT_SQP;
171 case IB_QPT_RC:
172 return QPT_RC;
173 case IB_QPT_UC:
174 return QPT_UC;
175 case IB_QPT_UD:
176 return QPT_UD;
177 default:
178 ehca_gen_err("Invalid ibqptype=%x", ibqptype);
179 return -EINVAL;
180 }
181 }
182
183 static inline enum ib_qp_statetrans get_modqp_statetrans(int ib_fromstate,
184 int ib_tostate)
185 {
186 int index = -EINVAL;
187 switch (ib_tostate) {
188 case IB_QPS_RESET:
189 index = IB_QPST_ANY2RESET;
190 break;
191 case IB_QPS_INIT:
192 switch (ib_fromstate) {
193 case IB_QPS_RESET:
194 index = IB_QPST_RESET2INIT;
195 break;
196 case IB_QPS_INIT:
197 index = IB_QPST_INIT2INIT;
198 break;
199 }
200 break;
201 case IB_QPS_RTR:
202 if (ib_fromstate == IB_QPS_INIT)
203 index = IB_QPST_INIT2RTR;
204 break;
205 case IB_QPS_RTS:
206 switch (ib_fromstate) {
207 case IB_QPS_RTR:
208 index = IB_QPST_RTR2RTS;
209 break;
210 case IB_QPS_RTS:
211 index = IB_QPST_RTS2RTS;
212 break;
213 case IB_QPS_SQD:
214 index = IB_QPST_SQD2RTS;
215 break;
216 case IB_QPS_SQE:
217 index = IB_QPST_SQE2RTS;
218 break;
219 }
220 break;
221 case IB_QPS_SQD:
222 if (ib_fromstate == IB_QPS_RTS)
223 index = IB_QPST_RTS2SQD;
224 break;
225 case IB_QPS_SQE:
226 break;
227 case IB_QPS_ERR:
228 index = IB_QPST_ANY2ERR;
229 break;
230 default:
231 break;
232 }
233 return index;
234 }
235
236 /*
237 * ibqptype2servicetype returns hcp service type corresponding to given
238 * ib qp type used by create_qp()
239 */
240 static inline int ibqptype2servicetype(enum ib_qp_type ibqptype)
241 {
242 switch (ibqptype) {
243 case IB_QPT_SMI:
244 case IB_QPT_GSI:
245 return ST_UD;
246 case IB_QPT_RC:
247 return ST_RC;
248 case IB_QPT_UC:
249 return ST_UC;
250 case IB_QPT_UD:
251 return ST_UD;
252 case IB_QPT_RAW_IPV6:
253 return -EINVAL;
254 case IB_QPT_RAW_ETY:
255 return -EINVAL;
256 default:
257 ehca_gen_err("Invalid ibqptype=%x", ibqptype);
258 return -EINVAL;
259 }
260 }
261
262 /*
263 * init userspace queue info from ipz_queue data
264 */
265 static inline void queue2resp(struct ipzu_queue_resp *resp,
266 struct ipz_queue *queue)
267 {
268 resp->qe_size = queue->qe_size;
269 resp->act_nr_of_sg = queue->act_nr_of_sg;
270 resp->queue_length = queue->queue_length;
271 resp->pagesize = queue->pagesize;
272 resp->toggle_state = queue->toggle_state;
273 resp->offset = queue->offset;
274 }
275
276 /*
277 * init_qp_queue initializes/constructs r/squeue and registers queue pages.
278 */
279 static inline int init_qp_queue(struct ehca_shca *shca,
280 struct ehca_pd *pd,
281 struct ehca_qp *my_qp,
282 struct ipz_queue *queue,
283 int q_type,
284 u64 expected_hret,
285 struct ehca_alloc_queue_parms *parms,
286 int wqe_size)
287 {
288 int ret, cnt, ipz_rc, nr_q_pages;
289 void *vpage;
290 u64 rpage, h_ret;
291 struct ib_device *ib_dev = &shca->ib_device;
292 struct ipz_adapter_handle ipz_hca_handle = shca->ipz_hca_handle;
293
294 if (!parms->queue_size)
295 return 0;
296
297 if (parms->is_small) {
298 nr_q_pages = 1;
299 ipz_rc = ipz_queue_ctor(pd, queue, nr_q_pages,
300 128 << parms->page_size,
301 wqe_size, parms->act_nr_sges, 1);
302 } else {
303 nr_q_pages = parms->queue_size;
304 ipz_rc = ipz_queue_ctor(pd, queue, nr_q_pages,
305 EHCA_PAGESIZE, wqe_size,
306 parms->act_nr_sges, 0);
307 }
308
309 if (!ipz_rc) {
310 ehca_err(ib_dev, "Cannot allocate page for queue. ipz_rc=%i",
311 ipz_rc);
312 return -EBUSY;
313 }
314
315 /* register queue pages */
316 for (cnt = 0; cnt < nr_q_pages; cnt++) {
317 vpage = ipz_qpageit_get_inc(queue);
318 if (!vpage) {
319 ehca_err(ib_dev, "ipz_qpageit_get_inc() "
320 "failed p_vpage= %p", vpage);
321 ret = -EINVAL;
322 goto init_qp_queue1;
323 }
324 rpage = virt_to_abs(vpage);
325
326 h_ret = hipz_h_register_rpage_qp(ipz_hca_handle,
327 my_qp->ipz_qp_handle,
328 NULL, 0, q_type,
329 rpage, parms->is_small ? 0 : 1,
330 my_qp->galpas.kernel);
331 if (cnt == (nr_q_pages - 1)) { /* last page! */
332 if (h_ret != expected_hret) {
333 ehca_err(ib_dev, "hipz_qp_register_rpage() "
334 "h_ret=%li", h_ret);
335 ret = ehca2ib_return_code(h_ret);
336 goto init_qp_queue1;
337 }
338 vpage = ipz_qpageit_get_inc(&my_qp->ipz_rqueue);
339 if (vpage) {
340 ehca_err(ib_dev, "ipz_qpageit_get_inc() "
341 "should not succeed vpage=%p", vpage);
342 ret = -EINVAL;
343 goto init_qp_queue1;
344 }
345 } else {
346 if (h_ret != H_PAGE_REGISTERED) {
347 ehca_err(ib_dev, "hipz_qp_register_rpage() "
348 "h_ret=%li", h_ret);
349 ret = ehca2ib_return_code(h_ret);
350 goto init_qp_queue1;
351 }
352 }
353 }
354
355 ipz_qeit_reset(queue);
356
357 return 0;
358
359 init_qp_queue1:
360 ipz_queue_dtor(pd, queue);
361 return ret;
362 }
363
364 static inline int ehca_calc_wqe_size(int act_nr_sge, int is_llqp)
365 {
366 if (is_llqp)
367 return 128 << act_nr_sge;
368 else
369 return offsetof(struct ehca_wqe,
370 u.nud.sg_list[act_nr_sge]);
371 }
372
373 static void ehca_determine_small_queue(struct ehca_alloc_queue_parms *queue,
374 int req_nr_sge, int is_llqp)
375 {
376 u32 wqe_size, q_size;
377 int act_nr_sge = req_nr_sge;
378
379 if (!is_llqp)
380 /* round up #SGEs so WQE size is a power of 2 */
381 for (act_nr_sge = 4; act_nr_sge <= 252;
382 act_nr_sge = 4 + 2 * act_nr_sge)
383 if (act_nr_sge >= req_nr_sge)
384 break;
385
386 wqe_size = ehca_calc_wqe_size(act_nr_sge, is_llqp);
387 q_size = wqe_size * (queue->max_wr + 1);
388
389 if (q_size <= 512)
390 queue->page_size = 2;
391 else if (q_size <= 1024)
392 queue->page_size = 3;
393 else
394 queue->page_size = 0;
395
396 queue->is_small = (queue->page_size != 0);
397 }
398
399 /*
400 * Create an ib_qp struct that is either a QP or an SRQ, depending on
401 * the value of the is_srq parameter. If init_attr and srq_init_attr share
402 * fields, the field out of init_attr is used.
403 */
404 static struct ehca_qp *internal_create_qp(
405 struct ib_pd *pd,
406 struct ib_qp_init_attr *init_attr,
407 struct ib_srq_init_attr *srq_init_attr,
408 struct ib_udata *udata, int is_srq)
409 {
410 struct ehca_qp *my_qp;
411 struct ehca_pd *my_pd = container_of(pd, struct ehca_pd, ib_pd);
412 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca,
413 ib_device);
414 struct ib_ucontext *context = NULL;
415 u64 h_ret;
416 int is_llqp = 0, has_srq = 0;
417 int qp_type, max_send_sge, max_recv_sge, ret;
418
419 /* h_call's out parameters */
420 struct ehca_alloc_qp_parms parms;
421 u32 swqe_size = 0, rwqe_size = 0, ib_qp_num;
422 unsigned long flags;
423
424 if (!atomic_add_unless(&shca->num_qps, 1, ehca_max_qp)) {
425 ehca_err(pd->device, "Unable to create QP, max number of %i "
426 "QPs reached.", ehca_max_qp);
427 ehca_err(pd->device, "To increase the maximum number of QPs "
428 "use the number_of_qps module parameter.\n");
429 return ERR_PTR(-ENOSPC);
430 }
431
432 if (init_attr->create_flags) {
433 atomic_dec(&shca->num_qps);
434 return ERR_PTR(-EINVAL);
435 }
436
437 memset(&parms, 0, sizeof(parms));
438 qp_type = init_attr->qp_type;
439
440 if (init_attr->sq_sig_type != IB_SIGNAL_REQ_WR &&
441 init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) {
442 ehca_err(pd->device, "init_attr->sg_sig_type=%x not allowed",
443 init_attr->sq_sig_type);
444 atomic_dec(&shca->num_qps);
445 return ERR_PTR(-EINVAL);
446 }
447
448 /* save LLQP info */
449 if (qp_type & 0x80) {
450 is_llqp = 1;
451 parms.ext_type = EQPT_LLQP;
452 parms.ll_comp_flags = qp_type & LLQP_COMP_MASK;
453 }
454 qp_type &= 0x1F;
455 init_attr->qp_type &= 0x1F;
456
457 /* handle SRQ base QPs */
458 if (init_attr->srq) {
459 struct ehca_qp *my_srq =
460 container_of(init_attr->srq, struct ehca_qp, ib_srq);
461
462 has_srq = 1;
463 parms.ext_type = EQPT_SRQBASE;
464 parms.srq_qpn = my_srq->real_qp_num;
465 }
466
467 if (is_llqp && has_srq) {
468 ehca_err(pd->device, "LLQPs can't have an SRQ");
469 atomic_dec(&shca->num_qps);
470 return ERR_PTR(-EINVAL);
471 }
472
473 /* handle SRQs */
474 if (is_srq) {
475 parms.ext_type = EQPT_SRQ;
476 parms.srq_limit = srq_init_attr->attr.srq_limit;
477 if (init_attr->cap.max_recv_sge > 3) {
478 ehca_err(pd->device, "no more than three SGEs "
479 "supported for SRQ pd=%p max_sge=%x",
480 pd, init_attr->cap.max_recv_sge);
481 atomic_dec(&shca->num_qps);
482 return ERR_PTR(-EINVAL);
483 }
484 }
485
486 /* check QP type */
487 if (qp_type != IB_QPT_UD &&
488 qp_type != IB_QPT_UC &&
489 qp_type != IB_QPT_RC &&
490 qp_type != IB_QPT_SMI &&
491 qp_type != IB_QPT_GSI) {
492 ehca_err(pd->device, "wrong QP Type=%x", qp_type);
493 atomic_dec(&shca->num_qps);
494 return ERR_PTR(-EINVAL);
495 }
496
497 if (is_llqp) {
498 switch (qp_type) {
499 case IB_QPT_RC:
500 if ((init_attr->cap.max_send_wr > 255) ||
501 (init_attr->cap.max_recv_wr > 255)) {
502 ehca_err(pd->device,
503 "Invalid Number of max_sq_wr=%x "
504 "or max_rq_wr=%x for RC LLQP",
505 init_attr->cap.max_send_wr,
506 init_attr->cap.max_recv_wr);
507 atomic_dec(&shca->num_qps);
508 return ERR_PTR(-EINVAL);
509 }
510 break;
511 case IB_QPT_UD:
512 if (!EHCA_BMASK_GET(HCA_CAP_UD_LL_QP, shca->hca_cap)) {
513 ehca_err(pd->device, "UD LLQP not supported "
514 "by this adapter");
515 atomic_dec(&shca->num_qps);
516 return ERR_PTR(-ENOSYS);
517 }
518 if (!(init_attr->cap.max_send_sge <= 5
519 && init_attr->cap.max_send_sge >= 1
520 && init_attr->cap.max_recv_sge <= 5
521 && init_attr->cap.max_recv_sge >= 1)) {
522 ehca_err(pd->device,
523 "Invalid Number of max_send_sge=%x "
524 "or max_recv_sge=%x for UD LLQP",
525 init_attr->cap.max_send_sge,
526 init_attr->cap.max_recv_sge);
527 atomic_dec(&shca->num_qps);
528 return ERR_PTR(-EINVAL);
529 } else if (init_attr->cap.max_send_wr > 255) {
530 ehca_err(pd->device,
531 "Invalid Number of "
532 "max_send_wr=%x for UD QP_TYPE=%x",
533 init_attr->cap.max_send_wr, qp_type);
534 atomic_dec(&shca->num_qps);
535 return ERR_PTR(-EINVAL);
536 }
537 break;
538 default:
539 ehca_err(pd->device, "unsupported LL QP Type=%x",
540 qp_type);
541 atomic_dec(&shca->num_qps);
542 return ERR_PTR(-EINVAL);
543 }
544 } else {
545 int max_sge = (qp_type == IB_QPT_UD || qp_type == IB_QPT_SMI
546 || qp_type == IB_QPT_GSI) ? 250 : 252;
547
548 if (init_attr->cap.max_send_sge > max_sge
549 || init_attr->cap.max_recv_sge > max_sge) {
550 ehca_err(pd->device, "Invalid number of SGEs requested "
551 "send_sge=%x recv_sge=%x max_sge=%x",
552 init_attr->cap.max_send_sge,
553 init_attr->cap.max_recv_sge, max_sge);
554 atomic_dec(&shca->num_qps);
555 return ERR_PTR(-EINVAL);
556 }
557 }
558
559 if (pd->uobject && udata)
560 context = pd->uobject->context;
561
562 my_qp = kmem_cache_zalloc(qp_cache, GFP_KERNEL);
563 if (!my_qp) {
564 ehca_err(pd->device, "pd=%p not enough memory to alloc qp", pd);
565 atomic_dec(&shca->num_qps);
566 return ERR_PTR(-ENOMEM);
567 }
568
569 atomic_set(&my_qp->nr_events, 0);
570 init_waitqueue_head(&my_qp->wait_completion);
571 spin_lock_init(&my_qp->spinlock_s);
572 spin_lock_init(&my_qp->spinlock_r);
573 my_qp->qp_type = qp_type;
574 my_qp->ext_type = parms.ext_type;
575 my_qp->state = IB_QPS_RESET;
576
577 if (init_attr->recv_cq)
578 my_qp->recv_cq =
579 container_of(init_attr->recv_cq, struct ehca_cq, ib_cq);
580 if (init_attr->send_cq)
581 my_qp->send_cq =
582 container_of(init_attr->send_cq, struct ehca_cq, ib_cq);
583
584 do {
585 if (!idr_pre_get(&ehca_qp_idr, GFP_KERNEL)) {
586 ret = -ENOMEM;
587 ehca_err(pd->device, "Can't reserve idr resources.");
588 goto create_qp_exit0;
589 }
590
591 write_lock_irqsave(&ehca_qp_idr_lock, flags);
592 ret = idr_get_new(&ehca_qp_idr, my_qp, &my_qp->token);
593 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
594 } while (ret == -EAGAIN);
595
596 if (ret) {
597 ret = -ENOMEM;
598 ehca_err(pd->device, "Can't allocate new idr entry.");
599 goto create_qp_exit0;
600 }
601
602 if (my_qp->token > 0x1FFFFFF) {
603 ret = -EINVAL;
604 ehca_err(pd->device, "Invalid number of qp");
605 goto create_qp_exit1;
606 }
607
608 if (has_srq)
609 parms.srq_token = my_qp->token;
610
611 parms.servicetype = ibqptype2servicetype(qp_type);
612 if (parms.servicetype < 0) {
613 ret = -EINVAL;
614 ehca_err(pd->device, "Invalid qp_type=%x", qp_type);
615 goto create_qp_exit1;
616 }
617
618 /* Always signal by WQE so we can hide circ. WQEs */
619 parms.sigtype = HCALL_SIGT_BY_WQE;
620
621 /* UD_AV CIRCUMVENTION */
622 max_send_sge = init_attr->cap.max_send_sge;
623 max_recv_sge = init_attr->cap.max_recv_sge;
624 if (parms.servicetype == ST_UD && !is_llqp) {
625 max_send_sge += 2;
626 max_recv_sge += 2;
627 }
628
629 parms.token = my_qp->token;
630 parms.eq_handle = shca->eq.ipz_eq_handle;
631 parms.pd = my_pd->fw_pd;
632 if (my_qp->send_cq)
633 parms.send_cq_handle = my_qp->send_cq->ipz_cq_handle;
634 if (my_qp->recv_cq)
635 parms.recv_cq_handle = my_qp->recv_cq->ipz_cq_handle;
636
637 parms.squeue.max_wr = init_attr->cap.max_send_wr;
638 parms.rqueue.max_wr = init_attr->cap.max_recv_wr;
639 parms.squeue.max_sge = max_send_sge;
640 parms.rqueue.max_sge = max_recv_sge;
641
642 /* RC QPs need one more SWQE for unsolicited ack circumvention */
643 if (qp_type == IB_QPT_RC)
644 parms.squeue.max_wr++;
645
646 if (EHCA_BMASK_GET(HCA_CAP_MINI_QP, shca->hca_cap)) {
647 if (HAS_SQ(my_qp))
648 ehca_determine_small_queue(
649 &parms.squeue, max_send_sge, is_llqp);
650 if (HAS_RQ(my_qp))
651 ehca_determine_small_queue(
652 &parms.rqueue, max_recv_sge, is_llqp);
653 parms.qp_storage =
654 (parms.squeue.is_small || parms.rqueue.is_small);
655 }
656
657 h_ret = hipz_h_alloc_resource_qp(shca->ipz_hca_handle, &parms);
658 if (h_ret != H_SUCCESS) {
659 ehca_err(pd->device, "h_alloc_resource_qp() failed h_ret=%li",
660 h_ret);
661 ret = ehca2ib_return_code(h_ret);
662 goto create_qp_exit1;
663 }
664
665 ib_qp_num = my_qp->real_qp_num = parms.real_qp_num;
666 my_qp->ipz_qp_handle = parms.qp_handle;
667 my_qp->galpas = parms.galpas;
668
669 swqe_size = ehca_calc_wqe_size(parms.squeue.act_nr_sges, is_llqp);
670 rwqe_size = ehca_calc_wqe_size(parms.rqueue.act_nr_sges, is_llqp);
671
672 switch (qp_type) {
673 case IB_QPT_RC:
674 if (is_llqp) {
675 parms.squeue.act_nr_sges = 1;
676 parms.rqueue.act_nr_sges = 1;
677 }
678 /* hide the extra WQE */
679 parms.squeue.act_nr_wqes--;
680 break;
681 case IB_QPT_UD:
682 case IB_QPT_GSI:
683 case IB_QPT_SMI:
684 /* UD circumvention */
685 if (is_llqp) {
686 parms.squeue.act_nr_sges = 1;
687 parms.rqueue.act_nr_sges = 1;
688 } else {
689 parms.squeue.act_nr_sges -= 2;
690 parms.rqueue.act_nr_sges -= 2;
691 }
692
693 if (IB_QPT_GSI == qp_type || IB_QPT_SMI == qp_type) {
694 parms.squeue.act_nr_wqes = init_attr->cap.max_send_wr;
695 parms.rqueue.act_nr_wqes = init_attr->cap.max_recv_wr;
696 parms.squeue.act_nr_sges = init_attr->cap.max_send_sge;
697 parms.rqueue.act_nr_sges = init_attr->cap.max_recv_sge;
698 ib_qp_num = (qp_type == IB_QPT_SMI) ? 0 : 1;
699 }
700
701 break;
702
703 default:
704 break;
705 }
706
707 /* initialize r/squeue and register queue pages */
708 if (HAS_SQ(my_qp)) {
709 ret = init_qp_queue(
710 shca, my_pd, my_qp, &my_qp->ipz_squeue, 0,
711 HAS_RQ(my_qp) ? H_PAGE_REGISTERED : H_SUCCESS,
712 &parms.squeue, swqe_size);
713 if (ret) {
714 ehca_err(pd->device, "Couldn't initialize squeue "
715 "and pages ret=%i", ret);
716 goto create_qp_exit2;
717 }
718 }
719
720 if (HAS_RQ(my_qp)) {
721 ret = init_qp_queue(
722 shca, my_pd, my_qp, &my_qp->ipz_rqueue, 1,
723 H_SUCCESS, &parms.rqueue, rwqe_size);
724 if (ret) {
725 ehca_err(pd->device, "Couldn't initialize rqueue "
726 "and pages ret=%i", ret);
727 goto create_qp_exit3;
728 }
729 }
730
731 if (is_srq) {
732 my_qp->ib_srq.pd = &my_pd->ib_pd;
733 my_qp->ib_srq.device = my_pd->ib_pd.device;
734
735 my_qp->ib_srq.srq_context = init_attr->qp_context;
736 my_qp->ib_srq.event_handler = init_attr->event_handler;
737 } else {
738 my_qp->ib_qp.qp_num = ib_qp_num;
739 my_qp->ib_qp.pd = &my_pd->ib_pd;
740 my_qp->ib_qp.device = my_pd->ib_pd.device;
741
742 my_qp->ib_qp.recv_cq = init_attr->recv_cq;
743 my_qp->ib_qp.send_cq = init_attr->send_cq;
744
745 my_qp->ib_qp.qp_type = qp_type;
746 my_qp->ib_qp.srq = init_attr->srq;
747
748 my_qp->ib_qp.qp_context = init_attr->qp_context;
749 my_qp->ib_qp.event_handler = init_attr->event_handler;
750 }
751
752 init_attr->cap.max_inline_data = 0; /* not supported yet */
753 init_attr->cap.max_recv_sge = parms.rqueue.act_nr_sges;
754 init_attr->cap.max_recv_wr = parms.rqueue.act_nr_wqes;
755 init_attr->cap.max_send_sge = parms.squeue.act_nr_sges;
756 init_attr->cap.max_send_wr = parms.squeue.act_nr_wqes;
757 my_qp->init_attr = *init_attr;
758
759 if (qp_type == IB_QPT_SMI || qp_type == IB_QPT_GSI) {
760 shca->sport[init_attr->port_num - 1].ibqp_sqp[qp_type] =
761 &my_qp->ib_qp;
762 if (ehca_nr_ports < 0) {
763 /* alloc array to cache subsequent modify qp parms
764 * for autodetect mode
765 */
766 my_qp->mod_qp_parm =
767 kzalloc(EHCA_MOD_QP_PARM_MAX *
768 sizeof(*my_qp->mod_qp_parm),
769 GFP_KERNEL);
770 if (!my_qp->mod_qp_parm) {
771 ehca_err(pd->device,
772 "Could not alloc mod_qp_parm");
773 goto create_qp_exit4;
774 }
775 }
776 }
777
778 /* NOTE: define_apq0() not supported yet */
779 if (qp_type == IB_QPT_GSI) {
780 h_ret = ehca_define_sqp(shca, my_qp, init_attr);
781 if (h_ret != H_SUCCESS) {
782 ret = ehca2ib_return_code(h_ret);
783 goto create_qp_exit5;
784 }
785 }
786
787 if (my_qp->send_cq) {
788 ret = ehca_cq_assign_qp(my_qp->send_cq, my_qp);
789 if (ret) {
790 ehca_err(pd->device,
791 "Couldn't assign qp to send_cq ret=%i", ret);
792 goto create_qp_exit5;
793 }
794 }
795
796 /* copy queues, galpa data to user space */
797 if (context && udata) {
798 struct ehca_create_qp_resp resp;
799 memset(&resp, 0, sizeof(resp));
800
801 resp.qp_num = my_qp->real_qp_num;
802 resp.token = my_qp->token;
803 resp.qp_type = my_qp->qp_type;
804 resp.ext_type = my_qp->ext_type;
805 resp.qkey = my_qp->qkey;
806 resp.real_qp_num = my_qp->real_qp_num;
807
808 if (HAS_SQ(my_qp))
809 queue2resp(&resp.ipz_squeue, &my_qp->ipz_squeue);
810 if (HAS_RQ(my_qp))
811 queue2resp(&resp.ipz_rqueue, &my_qp->ipz_rqueue);
812 resp.fw_handle_ofs = (u32)
813 (my_qp->galpas.user.fw_handle & (PAGE_SIZE - 1));
814
815 if (ib_copy_to_udata(udata, &resp, sizeof resp)) {
816 ehca_err(pd->device, "Copy to udata failed");
817 ret = -EINVAL;
818 goto create_qp_exit6;
819 }
820 }
821
822 return my_qp;
823
824 create_qp_exit6:
825 ehca_cq_unassign_qp(my_qp->send_cq, my_qp->real_qp_num);
826
827 create_qp_exit5:
828 kfree(my_qp->mod_qp_parm);
829
830 create_qp_exit4:
831 if (HAS_RQ(my_qp))
832 ipz_queue_dtor(my_pd, &my_qp->ipz_rqueue);
833
834 create_qp_exit3:
835 if (HAS_SQ(my_qp))
836 ipz_queue_dtor(my_pd, &my_qp->ipz_squeue);
837
838 create_qp_exit2:
839 hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
840
841 create_qp_exit1:
842 write_lock_irqsave(&ehca_qp_idr_lock, flags);
843 idr_remove(&ehca_qp_idr, my_qp->token);
844 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
845
846 create_qp_exit0:
847 kmem_cache_free(qp_cache, my_qp);
848 atomic_dec(&shca->num_qps);
849 return ERR_PTR(ret);
850 }
851
852 struct ib_qp *ehca_create_qp(struct ib_pd *pd,
853 struct ib_qp_init_attr *qp_init_attr,
854 struct ib_udata *udata)
855 {
856 struct ehca_qp *ret;
857
858 ret = internal_create_qp(pd, qp_init_attr, NULL, udata, 0);
859 return IS_ERR(ret) ? (struct ib_qp *)ret : &ret->ib_qp;
860 }
861
862 static int internal_destroy_qp(struct ib_device *dev, struct ehca_qp *my_qp,
863 struct ib_uobject *uobject);
864
865 struct ib_srq *ehca_create_srq(struct ib_pd *pd,
866 struct ib_srq_init_attr *srq_init_attr,
867 struct ib_udata *udata)
868 {
869 struct ib_qp_init_attr qp_init_attr;
870 struct ehca_qp *my_qp;
871 struct ib_srq *ret;
872 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca,
873 ib_device);
874 struct hcp_modify_qp_control_block *mqpcb;
875 u64 hret, update_mask;
876
877 /* For common attributes, internal_create_qp() takes its info
878 * out of qp_init_attr, so copy all common attrs there.
879 */
880 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
881 qp_init_attr.event_handler = srq_init_attr->event_handler;
882 qp_init_attr.qp_context = srq_init_attr->srq_context;
883 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
884 qp_init_attr.qp_type = IB_QPT_RC;
885 qp_init_attr.cap.max_recv_wr = srq_init_attr->attr.max_wr;
886 qp_init_attr.cap.max_recv_sge = srq_init_attr->attr.max_sge;
887
888 my_qp = internal_create_qp(pd, &qp_init_attr, srq_init_attr, udata, 1);
889 if (IS_ERR(my_qp))
890 return (struct ib_srq *)my_qp;
891
892 /* copy back return values */
893 srq_init_attr->attr.max_wr = qp_init_attr.cap.max_recv_wr;
894 srq_init_attr->attr.max_sge = 3;
895
896 /* drive SRQ into RTR state */
897 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
898 if (!mqpcb) {
899 ehca_err(pd->device, "Could not get zeroed page for mqpcb "
900 "ehca_qp=%p qp_num=%x ", my_qp, my_qp->real_qp_num);
901 ret = ERR_PTR(-ENOMEM);
902 goto create_srq1;
903 }
904
905 mqpcb->qp_state = EHCA_QPS_INIT;
906 mqpcb->prim_phys_port = 1;
907 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
908 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
909 my_qp->ipz_qp_handle,
910 &my_qp->pf,
911 update_mask,
912 mqpcb, my_qp->galpas.kernel);
913 if (hret != H_SUCCESS) {
914 ehca_err(pd->device, "Could not modify SRQ to INIT "
915 "ehca_qp=%p qp_num=%x h_ret=%li",
916 my_qp, my_qp->real_qp_num, hret);
917 goto create_srq2;
918 }
919
920 mqpcb->qp_enable = 1;
921 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
922 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
923 my_qp->ipz_qp_handle,
924 &my_qp->pf,
925 update_mask,
926 mqpcb, my_qp->galpas.kernel);
927 if (hret != H_SUCCESS) {
928 ehca_err(pd->device, "Could not enable SRQ "
929 "ehca_qp=%p qp_num=%x h_ret=%li",
930 my_qp, my_qp->real_qp_num, hret);
931 goto create_srq2;
932 }
933
934 mqpcb->qp_state = EHCA_QPS_RTR;
935 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
936 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
937 my_qp->ipz_qp_handle,
938 &my_qp->pf,
939 update_mask,
940 mqpcb, my_qp->galpas.kernel);
941 if (hret != H_SUCCESS) {
942 ehca_err(pd->device, "Could not modify SRQ to RTR "
943 "ehca_qp=%p qp_num=%x h_ret=%li",
944 my_qp, my_qp->real_qp_num, hret);
945 goto create_srq2;
946 }
947
948 ehca_free_fw_ctrlblock(mqpcb);
949
950 return &my_qp->ib_srq;
951
952 create_srq2:
953 ret = ERR_PTR(ehca2ib_return_code(hret));
954 ehca_free_fw_ctrlblock(mqpcb);
955
956 create_srq1:
957 internal_destroy_qp(pd->device, my_qp, my_qp->ib_srq.uobject);
958
959 return ret;
960 }
961
962 /*
963 * prepare_sqe_rts called by internal_modify_qp() at trans sqe -> rts
964 * set purge bit of bad wqe and subsequent wqes to avoid reentering sqe
965 * returns total number of bad wqes in bad_wqe_cnt
966 */
967 static int prepare_sqe_rts(struct ehca_qp *my_qp, struct ehca_shca *shca,
968 int *bad_wqe_cnt)
969 {
970 u64 h_ret;
971 struct ipz_queue *squeue;
972 void *bad_send_wqe_p, *bad_send_wqe_v;
973 u64 q_ofs;
974 struct ehca_wqe *wqe;
975 int qp_num = my_qp->ib_qp.qp_num;
976
977 /* get send wqe pointer */
978 h_ret = hipz_h_disable_and_get_wqe(shca->ipz_hca_handle,
979 my_qp->ipz_qp_handle, &my_qp->pf,
980 &bad_send_wqe_p, NULL, 2);
981 if (h_ret != H_SUCCESS) {
982 ehca_err(&shca->ib_device, "hipz_h_disable_and_get_wqe() failed"
983 " ehca_qp=%p qp_num=%x h_ret=%li",
984 my_qp, qp_num, h_ret);
985 return ehca2ib_return_code(h_ret);
986 }
987 bad_send_wqe_p = (void *)((u64)bad_send_wqe_p & (~(1L << 63)));
988 ehca_dbg(&shca->ib_device, "qp_num=%x bad_send_wqe_p=%p",
989 qp_num, bad_send_wqe_p);
990 /* convert wqe pointer to vadr */
991 bad_send_wqe_v = abs_to_virt((u64)bad_send_wqe_p);
992 if (ehca_debug_level >= 2)
993 ehca_dmp(bad_send_wqe_v, 32, "qp_num=%x bad_wqe", qp_num);
994 squeue = &my_qp->ipz_squeue;
995 if (ipz_queue_abs_to_offset(squeue, (u64)bad_send_wqe_p, &q_ofs)) {
996 ehca_err(&shca->ib_device, "failed to get wqe offset qp_num=%x"
997 " bad_send_wqe_p=%p", qp_num, bad_send_wqe_p);
998 return -EFAULT;
999 }
1000
1001 /* loop sets wqe's purge bit */
1002 wqe = (struct ehca_wqe *)ipz_qeit_calc(squeue, q_ofs);
1003 *bad_wqe_cnt = 0;
1004 while (wqe->optype != 0xff && wqe->wqef != 0xff) {
1005 if (ehca_debug_level >= 2)
1006 ehca_dmp(wqe, 32, "qp_num=%x wqe", qp_num);
1007 wqe->nr_of_data_seg = 0; /* suppress data access */
1008 wqe->wqef = WQEF_PURGE; /* WQE to be purged */
1009 q_ofs = ipz_queue_advance_offset(squeue, q_ofs);
1010 wqe = (struct ehca_wqe *)ipz_qeit_calc(squeue, q_ofs);
1011 *bad_wqe_cnt = (*bad_wqe_cnt)+1;
1012 }
1013 /*
1014 * bad wqe will be reprocessed and ignored when pol_cq() is called,
1015 * i.e. nr of wqes with flush error status is one less
1016 */
1017 ehca_dbg(&shca->ib_device, "qp_num=%x flusherr_wqe_cnt=%x",
1018 qp_num, (*bad_wqe_cnt)-1);
1019 wqe->wqef = 0;
1020
1021 return 0;
1022 }
1023
1024 /*
1025 * internal_modify_qp with circumvention to handle aqp0 properly
1026 * smi_reset2init indicates if this is an internal reset-to-init-call for
1027 * smi. This flag must always be zero if called from ehca_modify_qp()!
1028 * This internal func was intorduced to avoid recursion of ehca_modify_qp()!
1029 */
1030 static int internal_modify_qp(struct ib_qp *ibqp,
1031 struct ib_qp_attr *attr,
1032 int attr_mask, int smi_reset2init)
1033 {
1034 enum ib_qp_state qp_cur_state, qp_new_state;
1035 int cnt, qp_attr_idx, ret = 0;
1036 enum ib_qp_statetrans statetrans;
1037 struct hcp_modify_qp_control_block *mqpcb;
1038 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
1039 struct ehca_shca *shca =
1040 container_of(ibqp->pd->device, struct ehca_shca, ib_device);
1041 u64 update_mask;
1042 u64 h_ret;
1043 int bad_wqe_cnt = 0;
1044 int squeue_locked = 0;
1045 unsigned long flags = 0;
1046
1047 /* do query_qp to obtain current attr values */
1048 mqpcb = ehca_alloc_fw_ctrlblock(GFP_ATOMIC);
1049 if (!mqpcb) {
1050 ehca_err(ibqp->device, "Could not get zeroed page for mqpcb "
1051 "ehca_qp=%p qp_num=%x ", my_qp, ibqp->qp_num);
1052 return -ENOMEM;
1053 }
1054
1055 h_ret = hipz_h_query_qp(shca->ipz_hca_handle,
1056 my_qp->ipz_qp_handle,
1057 &my_qp->pf,
1058 mqpcb, my_qp->galpas.kernel);
1059 if (h_ret != H_SUCCESS) {
1060 ehca_err(ibqp->device, "hipz_h_query_qp() failed "
1061 "ehca_qp=%p qp_num=%x h_ret=%li",
1062 my_qp, ibqp->qp_num, h_ret);
1063 ret = ehca2ib_return_code(h_ret);
1064 goto modify_qp_exit1;
1065 }
1066
1067 qp_cur_state = ehca2ib_qp_state(mqpcb->qp_state);
1068
1069 if (qp_cur_state == -EINVAL) { /* invalid qp state */
1070 ret = -EINVAL;
1071 ehca_err(ibqp->device, "Invalid current ehca_qp_state=%x "
1072 "ehca_qp=%p qp_num=%x",
1073 mqpcb->qp_state, my_qp, ibqp->qp_num);
1074 goto modify_qp_exit1;
1075 }
1076 /*
1077 * circumvention to set aqp0 initial state to init
1078 * as expected by IB spec
1079 */
1080 if (smi_reset2init == 0 &&
1081 ibqp->qp_type == IB_QPT_SMI &&
1082 qp_cur_state == IB_QPS_RESET &&
1083 (attr_mask & IB_QP_STATE) &&
1084 attr->qp_state == IB_QPS_INIT) { /* RESET -> INIT */
1085 struct ib_qp_attr smiqp_attr = {
1086 .qp_state = IB_QPS_INIT,
1087 .port_num = my_qp->init_attr.port_num,
1088 .pkey_index = 0,
1089 .qkey = 0
1090 };
1091 int smiqp_attr_mask = IB_QP_STATE | IB_QP_PORT |
1092 IB_QP_PKEY_INDEX | IB_QP_QKEY;
1093 int smirc = internal_modify_qp(
1094 ibqp, &smiqp_attr, smiqp_attr_mask, 1);
1095 if (smirc) {
1096 ehca_err(ibqp->device, "SMI RESET -> INIT failed. "
1097 "ehca_modify_qp() rc=%i", smirc);
1098 ret = H_PARAMETER;
1099 goto modify_qp_exit1;
1100 }
1101 qp_cur_state = IB_QPS_INIT;
1102 ehca_dbg(ibqp->device, "SMI RESET -> INIT succeeded");
1103 }
1104 /* is transmitted current state equal to "real" current state */
1105 if ((attr_mask & IB_QP_CUR_STATE) &&
1106 qp_cur_state != attr->cur_qp_state) {
1107 ret = -EINVAL;
1108 ehca_err(ibqp->device,
1109 "Invalid IB_QP_CUR_STATE attr->curr_qp_state=%x <>"
1110 " actual cur_qp_state=%x. ehca_qp=%p qp_num=%x",
1111 attr->cur_qp_state, qp_cur_state, my_qp, ibqp->qp_num);
1112 goto modify_qp_exit1;
1113 }
1114
1115 ehca_dbg(ibqp->device, "ehca_qp=%p qp_num=%x current qp_state=%x "
1116 "new qp_state=%x attribute_mask=%x",
1117 my_qp, ibqp->qp_num, qp_cur_state, attr->qp_state, attr_mask);
1118
1119 qp_new_state = attr_mask & IB_QP_STATE ? attr->qp_state : qp_cur_state;
1120 if (!smi_reset2init &&
1121 !ib_modify_qp_is_ok(qp_cur_state, qp_new_state, ibqp->qp_type,
1122 attr_mask)) {
1123 ret = -EINVAL;
1124 ehca_err(ibqp->device,
1125 "Invalid qp transition new_state=%x cur_state=%x "
1126 "ehca_qp=%p qp_num=%x attr_mask=%x", qp_new_state,
1127 qp_cur_state, my_qp, ibqp->qp_num, attr_mask);
1128 goto modify_qp_exit1;
1129 }
1130
1131 mqpcb->qp_state = ib2ehca_qp_state(qp_new_state);
1132 if (mqpcb->qp_state)
1133 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
1134 else {
1135 ret = -EINVAL;
1136 ehca_err(ibqp->device, "Invalid new qp state=%x "
1137 "ehca_qp=%p qp_num=%x",
1138 qp_new_state, my_qp, ibqp->qp_num);
1139 goto modify_qp_exit1;
1140 }
1141
1142 /* retrieve state transition struct to get req and opt attrs */
1143 statetrans = get_modqp_statetrans(qp_cur_state, qp_new_state);
1144 if (statetrans < 0) {
1145 ret = -EINVAL;
1146 ehca_err(ibqp->device, "<INVALID STATE CHANGE> qp_cur_state=%x "
1147 "new_qp_state=%x State_xsition=%x ehca_qp=%p "
1148 "qp_num=%x", qp_cur_state, qp_new_state,
1149 statetrans, my_qp, ibqp->qp_num);
1150 goto modify_qp_exit1;
1151 }
1152
1153 qp_attr_idx = ib2ehcaqptype(ibqp->qp_type);
1154
1155 if (qp_attr_idx < 0) {
1156 ret = qp_attr_idx;
1157 ehca_err(ibqp->device,
1158 "Invalid QP type=%x ehca_qp=%p qp_num=%x",
1159 ibqp->qp_type, my_qp, ibqp->qp_num);
1160 goto modify_qp_exit1;
1161 }
1162
1163 ehca_dbg(ibqp->device,
1164 "ehca_qp=%p qp_num=%x <VALID STATE CHANGE> qp_state_xsit=%x",
1165 my_qp, ibqp->qp_num, statetrans);
1166
1167 /* eHCA2 rev2 and higher require the SEND_GRH_FLAG to be set
1168 * in non-LL UD QPs.
1169 */
1170 if ((my_qp->qp_type == IB_QPT_UD) &&
1171 (my_qp->ext_type != EQPT_LLQP) &&
1172 (statetrans == IB_QPST_INIT2RTR) &&
1173 (shca->hw_level >= 0x22)) {
1174 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
1175 mqpcb->send_grh_flag = 1;
1176 }
1177
1178 /* sqe -> rts: set purge bit of bad wqe before actual trans */
1179 if ((my_qp->qp_type == IB_QPT_UD ||
1180 my_qp->qp_type == IB_QPT_GSI ||
1181 my_qp->qp_type == IB_QPT_SMI) &&
1182 statetrans == IB_QPST_SQE2RTS) {
1183 /* mark next free wqe if kernel */
1184 if (!ibqp->uobject) {
1185 struct ehca_wqe *wqe;
1186 /* lock send queue */
1187 spin_lock_irqsave(&my_qp->spinlock_s, flags);
1188 squeue_locked = 1;
1189 /* mark next free wqe */
1190 wqe = (struct ehca_wqe *)
1191 ipz_qeit_get(&my_qp->ipz_squeue);
1192 wqe->optype = wqe->wqef = 0xff;
1193 ehca_dbg(ibqp->device, "qp_num=%x next_free_wqe=%p",
1194 ibqp->qp_num, wqe);
1195 }
1196 ret = prepare_sqe_rts(my_qp, shca, &bad_wqe_cnt);
1197 if (ret) {
1198 ehca_err(ibqp->device, "prepare_sqe_rts() failed "
1199 "ehca_qp=%p qp_num=%x ret=%i",
1200 my_qp, ibqp->qp_num, ret);
1201 goto modify_qp_exit2;
1202 }
1203 }
1204
1205 /*
1206 * enable RDMA_Atomic_Control if reset->init und reliable con
1207 * this is necessary since gen2 does not provide that flag,
1208 * but pHyp requires it
1209 */
1210 if (statetrans == IB_QPST_RESET2INIT &&
1211 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_UC)) {
1212 mqpcb->rdma_atomic_ctrl = 3;
1213 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RDMA_ATOMIC_CTRL, 1);
1214 }
1215 /* circ. pHyp requires #RDMA/Atomic Resp Res for UC INIT -> RTR */
1216 if (statetrans == IB_QPST_INIT2RTR &&
1217 (ibqp->qp_type == IB_QPT_UC) &&
1218 !(attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)) {
1219 mqpcb->rdma_nr_atomic_resp_res = 1; /* default to 1 */
1220 update_mask |=
1221 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
1222 }
1223
1224 if (attr_mask & IB_QP_PKEY_INDEX) {
1225 if (attr->pkey_index >= 16) {
1226 ret = -EINVAL;
1227 ehca_err(ibqp->device, "Invalid pkey_index=%x. "
1228 "ehca_qp=%p qp_num=%x max_pkey_index=f",
1229 attr->pkey_index, my_qp, ibqp->qp_num);
1230 goto modify_qp_exit2;
1231 }
1232 mqpcb->prim_p_key_idx = attr->pkey_index;
1233 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_P_KEY_IDX, 1);
1234 }
1235 if (attr_mask & IB_QP_PORT) {
1236 struct ehca_sport *sport;
1237 struct ehca_qp *aqp1;
1238 if (attr->port_num < 1 || attr->port_num > shca->num_ports) {
1239 ret = -EINVAL;
1240 ehca_err(ibqp->device, "Invalid port=%x. "
1241 "ehca_qp=%p qp_num=%x num_ports=%x",
1242 attr->port_num, my_qp, ibqp->qp_num,
1243 shca->num_ports);
1244 goto modify_qp_exit2;
1245 }
1246 sport = &shca->sport[attr->port_num - 1];
1247 if (!sport->ibqp_sqp[IB_QPT_GSI]) {
1248 /* should not occur */
1249 ret = -EFAULT;
1250 ehca_err(ibqp->device, "AQP1 was not created for "
1251 "port=%x", attr->port_num);
1252 goto modify_qp_exit2;
1253 }
1254 aqp1 = container_of(sport->ibqp_sqp[IB_QPT_GSI],
1255 struct ehca_qp, ib_qp);
1256 if (ibqp->qp_type != IB_QPT_GSI &&
1257 ibqp->qp_type != IB_QPT_SMI &&
1258 aqp1->mod_qp_parm) {
1259 /*
1260 * firmware will reject this modify_qp() because
1261 * port is not activated/initialized fully
1262 */
1263 ret = -EFAULT;
1264 ehca_warn(ibqp->device, "Couldn't modify qp port=%x: "
1265 "either port is being activated (try again) "
1266 "or cabling issue", attr->port_num);
1267 goto modify_qp_exit2;
1268 }
1269 mqpcb->prim_phys_port = attr->port_num;
1270 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_PHYS_PORT, 1);
1271 }
1272 if (attr_mask & IB_QP_QKEY) {
1273 mqpcb->qkey = attr->qkey;
1274 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_QKEY, 1);
1275 }
1276 if (attr_mask & IB_QP_AV) {
1277 mqpcb->dlid = attr->ah_attr.dlid;
1278 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID, 1);
1279 mqpcb->source_path_bits = attr->ah_attr.src_path_bits;
1280 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS, 1);
1281 mqpcb->service_level = attr->ah_attr.sl;
1282 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL, 1);
1283
1284 if (ehca_calc_ipd(shca, mqpcb->prim_phys_port,
1285 attr->ah_attr.static_rate,
1286 &mqpcb->max_static_rate)) {
1287 ret = -EINVAL;
1288 goto modify_qp_exit2;
1289 }
1290 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE, 1);
1291
1292 /*
1293 * Always supply the GRH flag, even if it's zero, to give the
1294 * hypervisor a clear "yes" or "no" instead of a "perhaps"
1295 */
1296 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
1297
1298 /*
1299 * only if GRH is TRUE we might consider SOURCE_GID_IDX
1300 * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
1301 */
1302 if (attr->ah_attr.ah_flags == IB_AH_GRH) {
1303 mqpcb->send_grh_flag = 1;
1304
1305 mqpcb->source_gid_idx = attr->ah_attr.grh.sgid_index;
1306 update_mask |=
1307 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX, 1);
1308
1309 for (cnt = 0; cnt < 16; cnt++)
1310 mqpcb->dest_gid.byte[cnt] =
1311 attr->ah_attr.grh.dgid.raw[cnt];
1312
1313 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_GID, 1);
1314 mqpcb->flow_label = attr->ah_attr.grh.flow_label;
1315 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL, 1);
1316 mqpcb->hop_limit = attr->ah_attr.grh.hop_limit;
1317 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT, 1);
1318 mqpcb->traffic_class = attr->ah_attr.grh.traffic_class;
1319 update_mask |=
1320 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS, 1);
1321 }
1322 }
1323
1324 if (attr_mask & IB_QP_PATH_MTU) {
1325 /* store ld(MTU) */
1326 my_qp->mtu_shift = attr->path_mtu + 7;
1327 mqpcb->path_mtu = attr->path_mtu;
1328 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PATH_MTU, 1);
1329 }
1330 if (attr_mask & IB_QP_TIMEOUT) {
1331 mqpcb->timeout = attr->timeout;
1332 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT, 1);
1333 }
1334 if (attr_mask & IB_QP_RETRY_CNT) {
1335 mqpcb->retry_count = attr->retry_cnt;
1336 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT, 1);
1337 }
1338 if (attr_mask & IB_QP_RNR_RETRY) {
1339 mqpcb->rnr_retry_count = attr->rnr_retry;
1340 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT, 1);
1341 }
1342 if (attr_mask & IB_QP_RQ_PSN) {
1343 mqpcb->receive_psn = attr->rq_psn;
1344 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RECEIVE_PSN, 1);
1345 }
1346 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1347 mqpcb->rdma_nr_atomic_resp_res = attr->max_dest_rd_atomic < 3 ?
1348 attr->max_dest_rd_atomic : 2;
1349 update_mask |=
1350 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
1351 }
1352 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1353 mqpcb->rdma_atomic_outst_dest_qp = attr->max_rd_atomic < 3 ?
1354 attr->max_rd_atomic : 2;
1355 update_mask |=
1356 EHCA_BMASK_SET
1357 (MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP, 1);
1358 }
1359 if (attr_mask & IB_QP_ALT_PATH) {
1360 if (attr->alt_port_num < 1
1361 || attr->alt_port_num > shca->num_ports) {
1362 ret = -EINVAL;
1363 ehca_err(ibqp->device, "Invalid alt_port=%x. "
1364 "ehca_qp=%p qp_num=%x num_ports=%x",
1365 attr->alt_port_num, my_qp, ibqp->qp_num,
1366 shca->num_ports);
1367 goto modify_qp_exit2;
1368 }
1369 mqpcb->alt_phys_port = attr->alt_port_num;
1370
1371 if (attr->alt_pkey_index >= 16) {
1372 ret = -EINVAL;
1373 ehca_err(ibqp->device, "Invalid alt_pkey_index=%x. "
1374 "ehca_qp=%p qp_num=%x max_pkey_index=f",
1375 attr->pkey_index, my_qp, ibqp->qp_num);
1376 goto modify_qp_exit2;
1377 }
1378 mqpcb->alt_p_key_idx = attr->alt_pkey_index;
1379
1380 mqpcb->timeout_al = attr->alt_timeout;
1381 mqpcb->dlid_al = attr->alt_ah_attr.dlid;
1382 mqpcb->source_path_bits_al = attr->alt_ah_attr.src_path_bits;
1383 mqpcb->service_level_al = attr->alt_ah_attr.sl;
1384
1385 if (ehca_calc_ipd(shca, mqpcb->alt_phys_port,
1386 attr->alt_ah_attr.static_rate,
1387 &mqpcb->max_static_rate_al)) {
1388 ret = -EINVAL;
1389 goto modify_qp_exit2;
1390 }
1391
1392 /* OpenIB doesn't support alternate retry counts - copy them */
1393 mqpcb->retry_count_al = mqpcb->retry_count;
1394 mqpcb->rnr_retry_count_al = mqpcb->rnr_retry_count;
1395
1396 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_ALT_PHYS_PORT, 1)
1397 | EHCA_BMASK_SET(MQPCB_MASK_ALT_P_KEY_IDX, 1)
1398 | EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT_AL, 1)
1399 | EHCA_BMASK_SET(MQPCB_MASK_DLID_AL, 1)
1400 | EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS_AL, 1)
1401 | EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL_AL, 1)
1402 | EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE_AL, 1)
1403 | EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT_AL, 1)
1404 | EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT_AL, 1);
1405
1406 /*
1407 * Always supply the GRH flag, even if it's zero, to give the
1408 * hypervisor a clear "yes" or "no" instead of a "perhaps"
1409 */
1410 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG_AL, 1);
1411
1412 /*
1413 * only if GRH is TRUE we might consider SOURCE_GID_IDX
1414 * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
1415 */
1416 if (attr->alt_ah_attr.ah_flags == IB_AH_GRH) {
1417 mqpcb->send_grh_flag_al = 1;
1418
1419 for (cnt = 0; cnt < 16; cnt++)
1420 mqpcb->dest_gid_al.byte[cnt] =
1421 attr->alt_ah_attr.grh.dgid.raw[cnt];
1422 mqpcb->source_gid_idx_al =
1423 attr->alt_ah_attr.grh.sgid_index;
1424 mqpcb->flow_label_al = attr->alt_ah_attr.grh.flow_label;
1425 mqpcb->hop_limit_al = attr->alt_ah_attr.grh.hop_limit;
1426 mqpcb->traffic_class_al =
1427 attr->alt_ah_attr.grh.traffic_class;
1428
1429 update_mask |=
1430 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX_AL, 1)
1431 | EHCA_BMASK_SET(MQPCB_MASK_DEST_GID_AL, 1)
1432 | EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL_AL, 1)
1433 | EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT_AL, 1) |
1434 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS_AL, 1);
1435 }
1436 }
1437
1438 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1439 mqpcb->min_rnr_nak_timer_field = attr->min_rnr_timer;
1440 update_mask |=
1441 EHCA_BMASK_SET(MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD, 1);
1442 }
1443
1444 if (attr_mask & IB_QP_SQ_PSN) {
1445 mqpcb->send_psn = attr->sq_psn;
1446 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_PSN, 1);
1447 }
1448
1449 if (attr_mask & IB_QP_DEST_QPN) {
1450 mqpcb->dest_qp_nr = attr->dest_qp_num;
1451 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_QP_NR, 1);
1452 }
1453
1454 if (attr_mask & IB_QP_PATH_MIG_STATE) {
1455 if (attr->path_mig_state != IB_MIG_REARM
1456 && attr->path_mig_state != IB_MIG_MIGRATED) {
1457 ret = -EINVAL;
1458 ehca_err(ibqp->device, "Invalid mig_state=%x",
1459 attr->path_mig_state);
1460 goto modify_qp_exit2;
1461 }
1462 mqpcb->path_migration_state = attr->path_mig_state + 1;
1463 if (attr->path_mig_state == IB_MIG_REARM)
1464 my_qp->mig_armed = 1;
1465 update_mask |=
1466 EHCA_BMASK_SET(MQPCB_MASK_PATH_MIGRATION_STATE, 1);
1467 }
1468
1469 if (attr_mask & IB_QP_CAP) {
1470 mqpcb->max_nr_outst_send_wr = attr->cap.max_send_wr+1;
1471 update_mask |=
1472 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_SEND_WR, 1);
1473 mqpcb->max_nr_outst_recv_wr = attr->cap.max_recv_wr+1;
1474 update_mask |=
1475 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_RECV_WR, 1);
1476 /* no support for max_send/recv_sge yet */
1477 }
1478
1479 if (ehca_debug_level >= 2)
1480 ehca_dmp(mqpcb, 4*70, "qp_num=%x", ibqp->qp_num);
1481
1482 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
1483 my_qp->ipz_qp_handle,
1484 &my_qp->pf,
1485 update_mask,
1486 mqpcb, my_qp->galpas.kernel);
1487
1488 if (h_ret != H_SUCCESS) {
1489 ret = ehca2ib_return_code(h_ret);
1490 ehca_err(ibqp->device, "hipz_h_modify_qp() failed h_ret=%li "
1491 "ehca_qp=%p qp_num=%x", h_ret, my_qp, ibqp->qp_num);
1492 goto modify_qp_exit2;
1493 }
1494
1495 if ((my_qp->qp_type == IB_QPT_UD ||
1496 my_qp->qp_type == IB_QPT_GSI ||
1497 my_qp->qp_type == IB_QPT_SMI) &&
1498 statetrans == IB_QPST_SQE2RTS) {
1499 /* doorbell to reprocessing wqes */
1500 iosync(); /* serialize GAL register access */
1501 hipz_update_sqa(my_qp, bad_wqe_cnt-1);
1502 ehca_gen_dbg("doorbell for %x wqes", bad_wqe_cnt);
1503 }
1504
1505 if (statetrans == IB_QPST_RESET2INIT ||
1506 statetrans == IB_QPST_INIT2INIT) {
1507 mqpcb->qp_enable = 1;
1508 mqpcb->qp_state = EHCA_QPS_INIT;
1509 update_mask = 0;
1510 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
1511
1512 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
1513 my_qp->ipz_qp_handle,
1514 &my_qp->pf,
1515 update_mask,
1516 mqpcb,
1517 my_qp->galpas.kernel);
1518
1519 if (h_ret != H_SUCCESS) {
1520 ret = ehca2ib_return_code(h_ret);
1521 ehca_err(ibqp->device, "ENABLE in context of "
1522 "RESET_2_INIT failed! Maybe you didn't get "
1523 "a LID h_ret=%li ehca_qp=%p qp_num=%x",
1524 h_ret, my_qp, ibqp->qp_num);
1525 goto modify_qp_exit2;
1526 }
1527 }
1528
1529 if (statetrans == IB_QPST_ANY2RESET) {
1530 ipz_qeit_reset(&my_qp->ipz_rqueue);
1531 ipz_qeit_reset(&my_qp->ipz_squeue);
1532 }
1533
1534 if (attr_mask & IB_QP_QKEY)
1535 my_qp->qkey = attr->qkey;
1536
1537 my_qp->state = qp_new_state;
1538
1539 modify_qp_exit2:
1540 if (squeue_locked) { /* this means: sqe -> rts */
1541 spin_unlock_irqrestore(&my_qp->spinlock_s, flags);
1542 my_qp->sqerr_purgeflag = 1;
1543 }
1544
1545 modify_qp_exit1:
1546 ehca_free_fw_ctrlblock(mqpcb);
1547
1548 return ret;
1549 }
1550
1551 int ehca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
1552 struct ib_udata *udata)
1553 {
1554 struct ehca_shca *shca = container_of(ibqp->device, struct ehca_shca,
1555 ib_device);
1556 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
1557
1558 /* The if-block below caches qp_attr to be modified for GSI and SMI
1559 * qps during the initialization by ib_mad. When the respective port
1560 * is activated, ie we got an event PORT_ACTIVE, we'll replay the
1561 * cached modify calls sequence, see ehca_recover_sqs() below.
1562 * Why that is required:
1563 * 1) If one port is connected, older code requires that port one
1564 * to be connected and module option nr_ports=1 to be given by
1565 * user, which is very inconvenient for end user.
1566 * 2) Firmware accepts modify_qp() only if respective port has become
1567 * active. Older code had a wait loop of 30sec create_qp()/
1568 * define_aqp1(), which is not appropriate in practice. This
1569 * code now removes that wait loop, see define_aqp1(), and always
1570 * reports all ports to ib_mad resp. users. Only activated ports
1571 * will then usable for the users.
1572 */
1573 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1574 int port = my_qp->init_attr.port_num;
1575 struct ehca_sport *sport = &shca->sport[port - 1];
1576 unsigned long flags;
1577 spin_lock_irqsave(&sport->mod_sqp_lock, flags);
1578 /* cache qp_attr only during init */
1579 if (my_qp->mod_qp_parm) {
1580 struct ehca_mod_qp_parm *p;
1581 if (my_qp->mod_qp_parm_idx >= EHCA_MOD_QP_PARM_MAX) {
1582 ehca_err(&shca->ib_device,
1583 "mod_qp_parm overflow state=%x port=%x"
1584 " type=%x", attr->qp_state,
1585 my_qp->init_attr.port_num,
1586 ibqp->qp_type);
1587 spin_unlock_irqrestore(&sport->mod_sqp_lock,
1588 flags);
1589 return -EINVAL;
1590 }
1591 p = &my_qp->mod_qp_parm[my_qp->mod_qp_parm_idx];
1592 p->mask = attr_mask;
1593 p->attr = *attr;
1594 my_qp->mod_qp_parm_idx++;
1595 ehca_dbg(&shca->ib_device,
1596 "Saved qp_attr for state=%x port=%x type=%x",
1597 attr->qp_state, my_qp->init_attr.port_num,
1598 ibqp->qp_type);
1599 spin_unlock_irqrestore(&sport->mod_sqp_lock, flags);
1600 return 0;
1601 }
1602 spin_unlock_irqrestore(&sport->mod_sqp_lock, flags);
1603 }
1604
1605 return internal_modify_qp(ibqp, attr, attr_mask, 0);
1606 }
1607
1608 void ehca_recover_sqp(struct ib_qp *sqp)
1609 {
1610 struct ehca_qp *my_sqp = container_of(sqp, struct ehca_qp, ib_qp);
1611 int port = my_sqp->init_attr.port_num;
1612 struct ib_qp_attr attr;
1613 struct ehca_mod_qp_parm *qp_parm;
1614 int i, qp_parm_idx, ret;
1615 unsigned long flags, wr_cnt;
1616
1617 if (!my_sqp->mod_qp_parm)
1618 return;
1619 ehca_dbg(sqp->device, "SQP port=%x qp_num=%x", port, sqp->qp_num);
1620
1621 qp_parm = my_sqp->mod_qp_parm;
1622 qp_parm_idx = my_sqp->mod_qp_parm_idx;
1623 for (i = 0; i < qp_parm_idx; i++) {
1624 attr = qp_parm[i].attr;
1625 ret = internal_modify_qp(sqp, &attr, qp_parm[i].mask, 0);
1626 if (ret) {
1627 ehca_err(sqp->device, "Could not modify SQP port=%x "
1628 "qp_num=%x ret=%x", port, sqp->qp_num, ret);
1629 goto free_qp_parm;
1630 }
1631 ehca_dbg(sqp->device, "SQP port=%x qp_num=%x in state=%x",
1632 port, sqp->qp_num, attr.qp_state);
1633 }
1634
1635 /* re-trigger posted recv wrs */
1636 wr_cnt = my_sqp->ipz_rqueue.current_q_offset /
1637 my_sqp->ipz_rqueue.qe_size;
1638 if (wr_cnt) {
1639 spin_lock_irqsave(&my_sqp->spinlock_r, flags);
1640 hipz_update_rqa(my_sqp, wr_cnt);
1641 spin_unlock_irqrestore(&my_sqp->spinlock_r, flags);
1642 ehca_dbg(sqp->device, "doorbell port=%x qp_num=%x wr_cnt=%lx",
1643 port, sqp->qp_num, wr_cnt);
1644 }
1645
1646 free_qp_parm:
1647 kfree(qp_parm);
1648 /* this prevents subsequent calls to modify_qp() to cache qp_attr */
1649 my_sqp->mod_qp_parm = NULL;
1650 }
1651
1652 int ehca_query_qp(struct ib_qp *qp,
1653 struct ib_qp_attr *qp_attr,
1654 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1655 {
1656 struct ehca_qp *my_qp = container_of(qp, struct ehca_qp, ib_qp);
1657 struct ehca_shca *shca = container_of(qp->device, struct ehca_shca,
1658 ib_device);
1659 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle;
1660 struct hcp_modify_qp_control_block *qpcb;
1661 int cnt, ret = 0;
1662 u64 h_ret;
1663
1664 if (qp_attr_mask & QP_ATTR_QUERY_NOT_SUPPORTED) {
1665 ehca_err(qp->device, "Invalid attribute mask "
1666 "ehca_qp=%p qp_num=%x qp_attr_mask=%x ",
1667 my_qp, qp->qp_num, qp_attr_mask);
1668 return -EINVAL;
1669 }
1670
1671 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1672 if (!qpcb) {
1673 ehca_err(qp->device, "Out of memory for qpcb "
1674 "ehca_qp=%p qp_num=%x", my_qp, qp->qp_num);
1675 return -ENOMEM;
1676 }
1677
1678 h_ret = hipz_h_query_qp(adapter_handle,
1679 my_qp->ipz_qp_handle,
1680 &my_qp->pf,
1681 qpcb, my_qp->galpas.kernel);
1682
1683 if (h_ret != H_SUCCESS) {
1684 ret = ehca2ib_return_code(h_ret);
1685 ehca_err(qp->device, "hipz_h_query_qp() failed "
1686 "ehca_qp=%p qp_num=%x h_ret=%li",
1687 my_qp, qp->qp_num, h_ret);
1688 goto query_qp_exit1;
1689 }
1690
1691 qp_attr->cur_qp_state = ehca2ib_qp_state(qpcb->qp_state);
1692 qp_attr->qp_state = qp_attr->cur_qp_state;
1693
1694 if (qp_attr->cur_qp_state == -EINVAL) {
1695 ret = -EINVAL;
1696 ehca_err(qp->device, "Got invalid ehca_qp_state=%x "
1697 "ehca_qp=%p qp_num=%x",
1698 qpcb->qp_state, my_qp, qp->qp_num);
1699 goto query_qp_exit1;
1700 }
1701
1702 if (qp_attr->qp_state == IB_QPS_SQD)
1703 qp_attr->sq_draining = 1;
1704
1705 qp_attr->qkey = qpcb->qkey;
1706 qp_attr->path_mtu = qpcb->path_mtu;
1707 qp_attr->path_mig_state = qpcb->path_migration_state - 1;
1708 qp_attr->rq_psn = qpcb->receive_psn;
1709 qp_attr->sq_psn = qpcb->send_psn;
1710 qp_attr->min_rnr_timer = qpcb->min_rnr_nak_timer_field;
1711 qp_attr->cap.max_send_wr = qpcb->max_nr_outst_send_wr-1;
1712 qp_attr->cap.max_recv_wr = qpcb->max_nr_outst_recv_wr-1;
1713 /* UD_AV CIRCUMVENTION */
1714 if (my_qp->qp_type == IB_QPT_UD) {
1715 qp_attr->cap.max_send_sge =
1716 qpcb->actual_nr_sges_in_sq_wqe - 2;
1717 qp_attr->cap.max_recv_sge =
1718 qpcb->actual_nr_sges_in_rq_wqe - 2;
1719 } else {
1720 qp_attr->cap.max_send_sge =
1721 qpcb->actual_nr_sges_in_sq_wqe;
1722 qp_attr->cap.max_recv_sge =
1723 qpcb->actual_nr_sges_in_rq_wqe;
1724 }
1725
1726 qp_attr->cap.max_inline_data = my_qp->sq_max_inline_data_size;
1727 qp_attr->dest_qp_num = qpcb->dest_qp_nr;
1728
1729 qp_attr->pkey_index =
1730 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->prim_p_key_idx);
1731
1732 qp_attr->port_num =
1733 EHCA_BMASK_GET(MQPCB_PRIM_PHYS_PORT, qpcb->prim_phys_port);
1734
1735 qp_attr->timeout = qpcb->timeout;
1736 qp_attr->retry_cnt = qpcb->retry_count;
1737 qp_attr->rnr_retry = qpcb->rnr_retry_count;
1738
1739 qp_attr->alt_pkey_index =
1740 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->alt_p_key_idx);
1741
1742 qp_attr->alt_port_num = qpcb->alt_phys_port;
1743 qp_attr->alt_timeout = qpcb->timeout_al;
1744
1745 qp_attr->max_dest_rd_atomic = qpcb->rdma_nr_atomic_resp_res;
1746 qp_attr->max_rd_atomic = qpcb->rdma_atomic_outst_dest_qp;
1747
1748 /* primary av */
1749 qp_attr->ah_attr.sl = qpcb->service_level;
1750
1751 if (qpcb->send_grh_flag) {
1752 qp_attr->ah_attr.ah_flags = IB_AH_GRH;
1753 }
1754
1755 qp_attr->ah_attr.static_rate = qpcb->max_static_rate;
1756 qp_attr->ah_attr.dlid = qpcb->dlid;
1757 qp_attr->ah_attr.src_path_bits = qpcb->source_path_bits;
1758 qp_attr->ah_attr.port_num = qp_attr->port_num;
1759
1760 /* primary GRH */
1761 qp_attr->ah_attr.grh.traffic_class = qpcb->traffic_class;
1762 qp_attr->ah_attr.grh.hop_limit = qpcb->hop_limit;
1763 qp_attr->ah_attr.grh.sgid_index = qpcb->source_gid_idx;
1764 qp_attr->ah_attr.grh.flow_label = qpcb->flow_label;
1765
1766 for (cnt = 0; cnt < 16; cnt++)
1767 qp_attr->ah_attr.grh.dgid.raw[cnt] =
1768 qpcb->dest_gid.byte[cnt];
1769
1770 /* alternate AV */
1771 qp_attr->alt_ah_attr.sl = qpcb->service_level_al;
1772 if (qpcb->send_grh_flag_al) {
1773 qp_attr->alt_ah_attr.ah_flags = IB_AH_GRH;
1774 }
1775
1776 qp_attr->alt_ah_attr.static_rate = qpcb->max_static_rate_al;
1777 qp_attr->alt_ah_attr.dlid = qpcb->dlid_al;
1778 qp_attr->alt_ah_attr.src_path_bits = qpcb->source_path_bits_al;
1779
1780 /* alternate GRH */
1781 qp_attr->alt_ah_attr.grh.traffic_class = qpcb->traffic_class_al;
1782 qp_attr->alt_ah_attr.grh.hop_limit = qpcb->hop_limit_al;
1783 qp_attr->alt_ah_attr.grh.sgid_index = qpcb->source_gid_idx_al;
1784 qp_attr->alt_ah_attr.grh.flow_label = qpcb->flow_label_al;
1785
1786 for (cnt = 0; cnt < 16; cnt++)
1787 qp_attr->alt_ah_attr.grh.dgid.raw[cnt] =
1788 qpcb->dest_gid_al.byte[cnt];
1789
1790 /* return init attributes given in ehca_create_qp */
1791 if (qp_init_attr)
1792 *qp_init_attr = my_qp->init_attr;
1793
1794 if (ehca_debug_level >= 2)
1795 ehca_dmp(qpcb, 4*70, "qp_num=%x", qp->qp_num);
1796
1797 query_qp_exit1:
1798 ehca_free_fw_ctrlblock(qpcb);
1799
1800 return ret;
1801 }
1802
1803 int ehca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1804 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata)
1805 {
1806 struct ehca_qp *my_qp =
1807 container_of(ibsrq, struct ehca_qp, ib_srq);
1808 struct ehca_shca *shca =
1809 container_of(ibsrq->pd->device, struct ehca_shca, ib_device);
1810 struct hcp_modify_qp_control_block *mqpcb;
1811 u64 update_mask;
1812 u64 h_ret;
1813 int ret = 0;
1814
1815 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1816 if (!mqpcb) {
1817 ehca_err(ibsrq->device, "Could not get zeroed page for mqpcb "
1818 "ehca_qp=%p qp_num=%x ", my_qp, my_qp->real_qp_num);
1819 return -ENOMEM;
1820 }
1821
1822 update_mask = 0;
1823 if (attr_mask & IB_SRQ_LIMIT) {
1824 attr_mask &= ~IB_SRQ_LIMIT;
1825 update_mask |=
1826 EHCA_BMASK_SET(MQPCB_MASK_CURR_SRQ_LIMIT, 1)
1827 | EHCA_BMASK_SET(MQPCB_MASK_QP_AFF_ASYN_EV_LOG_REG, 1);
1828 mqpcb->curr_srq_limit =
1829 EHCA_BMASK_SET(MQPCB_CURR_SRQ_LIMIT, attr->srq_limit);
1830 mqpcb->qp_aff_asyn_ev_log_reg =
1831 EHCA_BMASK_SET(QPX_AAELOG_RESET_SRQ_LIMIT, 1);
1832 }
1833
1834 /* by now, all bits in attr_mask should have been cleared */
1835 if (attr_mask) {
1836 ehca_err(ibsrq->device, "invalid attribute mask bits set "
1837 "attr_mask=%x", attr_mask);
1838 ret = -EINVAL;
1839 goto modify_srq_exit0;
1840 }
1841
1842 if (ehca_debug_level >= 2)
1843 ehca_dmp(mqpcb, 4*70, "qp_num=%x", my_qp->real_qp_num);
1844
1845 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle, my_qp->ipz_qp_handle,
1846 NULL, update_mask, mqpcb,
1847 my_qp->galpas.kernel);
1848
1849 if (h_ret != H_SUCCESS) {
1850 ret = ehca2ib_return_code(h_ret);
1851 ehca_err(ibsrq->device, "hipz_h_modify_qp() failed h_ret=%li "
1852 "ehca_qp=%p qp_num=%x",
1853 h_ret, my_qp, my_qp->real_qp_num);
1854 }
1855
1856 modify_srq_exit0:
1857 ehca_free_fw_ctrlblock(mqpcb);
1858
1859 return ret;
1860 }
1861
1862 int ehca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr)
1863 {
1864 struct ehca_qp *my_qp = container_of(srq, struct ehca_qp, ib_srq);
1865 struct ehca_shca *shca = container_of(srq->device, struct ehca_shca,
1866 ib_device);
1867 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle;
1868 struct hcp_modify_qp_control_block *qpcb;
1869 int ret = 0;
1870 u64 h_ret;
1871
1872 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1873 if (!qpcb) {
1874 ehca_err(srq->device, "Out of memory for qpcb "
1875 "ehca_qp=%p qp_num=%x", my_qp, my_qp->real_qp_num);
1876 return -ENOMEM;
1877 }
1878
1879 h_ret = hipz_h_query_qp(adapter_handle, my_qp->ipz_qp_handle,
1880 NULL, qpcb, my_qp->galpas.kernel);
1881
1882 if (h_ret != H_SUCCESS) {
1883 ret = ehca2ib_return_code(h_ret);
1884 ehca_err(srq->device, "hipz_h_query_qp() failed "
1885 "ehca_qp=%p qp_num=%x h_ret=%li",
1886 my_qp, my_qp->real_qp_num, h_ret);
1887 goto query_srq_exit1;
1888 }
1889
1890 srq_attr->max_wr = qpcb->max_nr_outst_recv_wr - 1;
1891 srq_attr->max_sge = 3;
1892 srq_attr->srq_limit = EHCA_BMASK_GET(
1893 MQPCB_CURR_SRQ_LIMIT, qpcb->curr_srq_limit);
1894
1895 if (ehca_debug_level >= 2)
1896 ehca_dmp(qpcb, 4*70, "qp_num=%x", my_qp->real_qp_num);
1897
1898 query_srq_exit1:
1899 ehca_free_fw_ctrlblock(qpcb);
1900
1901 return ret;
1902 }
1903
1904 static int internal_destroy_qp(struct ib_device *dev, struct ehca_qp *my_qp,
1905 struct ib_uobject *uobject)
1906 {
1907 struct ehca_shca *shca = container_of(dev, struct ehca_shca, ib_device);
1908 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd,
1909 ib_pd);
1910 struct ehca_sport *sport = &shca->sport[my_qp->init_attr.port_num - 1];
1911 u32 qp_num = my_qp->real_qp_num;
1912 int ret;
1913 u64 h_ret;
1914 u8 port_num;
1915 enum ib_qp_type qp_type;
1916 unsigned long flags;
1917
1918 if (uobject) {
1919 if (my_qp->mm_count_galpa ||
1920 my_qp->mm_count_rqueue || my_qp->mm_count_squeue) {
1921 ehca_err(dev, "Resources still referenced in "
1922 "user space qp_num=%x", qp_num);
1923 return -EINVAL;
1924 }
1925 }
1926
1927 if (my_qp->send_cq) {
1928 ret = ehca_cq_unassign_qp(my_qp->send_cq, qp_num);
1929 if (ret) {
1930 ehca_err(dev, "Couldn't unassign qp from "
1931 "send_cq ret=%i qp_num=%x cq_num=%x", ret,
1932 qp_num, my_qp->send_cq->cq_number);
1933 return ret;
1934 }
1935 }
1936
1937 write_lock_irqsave(&ehca_qp_idr_lock, flags);
1938 idr_remove(&ehca_qp_idr, my_qp->token);
1939 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
1940
1941 /* now wait until all pending events have completed */
1942 wait_event(my_qp->wait_completion, !atomic_read(&my_qp->nr_events));
1943
1944 h_ret = hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
1945 if (h_ret != H_SUCCESS) {
1946 ehca_err(dev, "hipz_h_destroy_qp() failed h_ret=%li "
1947 "ehca_qp=%p qp_num=%x", h_ret, my_qp, qp_num);
1948 return ehca2ib_return_code(h_ret);
1949 }
1950
1951 port_num = my_qp->init_attr.port_num;
1952 qp_type = my_qp->init_attr.qp_type;
1953
1954 if (qp_type == IB_QPT_SMI || qp_type == IB_QPT_GSI) {
1955 spin_lock_irqsave(&sport->mod_sqp_lock, flags);
1956 kfree(my_qp->mod_qp_parm);
1957 my_qp->mod_qp_parm = NULL;
1958 shca->sport[port_num - 1].ibqp_sqp[qp_type] = NULL;
1959 spin_unlock_irqrestore(&sport->mod_sqp_lock, flags);
1960 }
1961
1962 /* no support for IB_QPT_SMI yet */
1963 if (qp_type == IB_QPT_GSI) {
1964 struct ib_event event;
1965 ehca_info(dev, "device %s: port %x is inactive.",
1966 shca->ib_device.name, port_num);
1967 event.device = &shca->ib_device;
1968 event.event = IB_EVENT_PORT_ERR;
1969 event.element.port_num = port_num;
1970 shca->sport[port_num - 1].port_state = IB_PORT_DOWN;
1971 ib_dispatch_event(&event);
1972 }
1973
1974 if (HAS_RQ(my_qp))
1975 ipz_queue_dtor(my_pd, &my_qp->ipz_rqueue);
1976 if (HAS_SQ(my_qp))
1977 ipz_queue_dtor(my_pd, &my_qp->ipz_squeue);
1978 kmem_cache_free(qp_cache, my_qp);
1979 atomic_dec(&shca->num_qps);
1980 return 0;
1981 }
1982
1983 int ehca_destroy_qp(struct ib_qp *qp)
1984 {
1985 return internal_destroy_qp(qp->device,
1986 container_of(qp, struct ehca_qp, ib_qp),
1987 qp->uobject);
1988 }
1989
1990 int ehca_destroy_srq(struct ib_srq *srq)
1991 {
1992 return internal_destroy_qp(srq->device,
1993 container_of(srq, struct ehca_qp, ib_srq),
1994 srq->uobject);
1995 }
1996
1997 int ehca_init_qp_cache(void)
1998 {
1999 qp_cache = kmem_cache_create("ehca_cache_qp",
2000 sizeof(struct ehca_qp), 0,
2001 SLAB_HWCACHE_ALIGN,
2002 NULL);
2003 if (!qp_cache)
2004 return -ENOMEM;
2005 return 0;
2006 }
2007
2008 void ehca_cleanup_qp_cache(void)
2009 {
2010 if (qp_cache)
2011 kmem_cache_destroy(qp_cache);
2012 }
Linux kernel - Deliverables
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