4 * Copyright(c) 2015, 2016 Intel Corporation.
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
26 * - Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
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29 * notice, this list of conditions and the following disclaimer in
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32 * - Neither the name of Intel Corporation nor the names of its
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36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
50 #include <linux/interrupt.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/mutex.h>
54 #include <linux/list.h>
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
59 #include <linux/completion.h>
60 #include <linux/kref.h>
61 #include <linux/sched.h>
62 #include <linux/cdev.h>
63 #include <linux/delay.h>
64 #include <linux/kthread.h>
65 #include <linux/i2c.h>
66 #include <linux/i2c-algo-bit.h>
67 #include <rdma/rdma_vt.h>
69 #include "chip_registers.h"
79 /* bumped 1 from s/w major version of TrueScale */
80 #define HFI1_CHIP_VERS_MAJ 3U
82 /* don't care about this except printing */
83 #define HFI1_CHIP_VERS_MIN 0U
85 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
86 #define HFI1_OUI 0x001175
87 #define HFI1_OUI_LSB 40
89 #define DROP_PACKET_OFF 0
90 #define DROP_PACKET_ON 1
92 extern unsigned long hfi1_cap_mask
;
93 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
94 #define HFI1_CAP_UGET_MASK(mask, cap) \
95 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
96 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
97 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
98 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
99 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
100 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
102 /* Offline Disabled Reason is 4-bits */
103 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
106 * Control context is always 0 and handles the error packets.
107 * It also handles the VL15 and multicast packets.
109 #define HFI1_CTRL_CTXT 0
112 * Driver context will store software counters for each of the events
113 * associated with these status registers
115 #define NUM_CCE_ERR_STATUS_COUNTERS 41
116 #define NUM_RCV_ERR_STATUS_COUNTERS 64
117 #define NUM_MISC_ERR_STATUS_COUNTERS 13
118 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
119 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
120 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
121 #define NUM_SEND_ERR_STATUS_COUNTERS 3
122 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
123 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
126 * per driver stats, either not device nor port-specific, or
127 * summed over all of the devices and ports.
128 * They are described by name via ipathfs filesystem, so layout
129 * and number of elements can change without breaking compatibility.
130 * If members are added or deleted hfi1_statnames[] in debugfs.c must
133 struct hfi1_ib_stats
{
134 __u64 sps_ints
; /* number of interrupts handled */
135 __u64 sps_errints
; /* number of error interrupts */
136 __u64 sps_txerrs
; /* tx-related packet errors */
137 __u64 sps_rcverrs
; /* non-crc rcv packet errors */
138 __u64 sps_hwerrs
; /* hardware errors reported (parity, etc.) */
139 __u64 sps_nopiobufs
; /* no pio bufs avail from kernel */
140 __u64 sps_ctxts
; /* number of contexts currently open */
141 __u64 sps_lenerrs
; /* number of kernel packets where RHF != LRH len */
146 extern struct hfi1_ib_stats hfi1_stats
;
147 extern const struct pci_error_handlers hfi1_pci_err_handler
;
150 * First-cut criterion for "device is active" is
151 * two thousand dwords combined Tx, Rx traffic per
152 * 5-second interval. SMA packets are 64 dwords,
153 * and occur "a few per second", presumably each way.
155 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
158 * Below contains all data related to a single context (formerly called port).
161 #ifdef CONFIG_DEBUG_FS
162 struct hfi1_opcode_stats_perctx
;
165 struct ctxt_eager_bufs
{
166 ssize_t size
; /* total size of eager buffers */
167 u32 count
; /* size of buffers array */
168 u32 numbufs
; /* number of buffers allocated */
169 u32 alloced
; /* number of rcvarray entries used */
170 u32 rcvtid_size
; /* size of each eager rcv tid */
171 u32 threshold
; /* head update threshold */
172 struct eager_buffer
{
184 struct list_head list
;
188 struct hfi1_ctxtdata
{
189 /* shadow the ctxt's RcvCtrl register */
191 /* rcvhdrq base, needs mmap before useful */
193 /* kernel virtual address where hdrqtail is updated */
194 volatile __le64
*rcvhdrtail_kvaddr
;
196 * Shared page for kernel to signal user processes that send buffers
197 * need disarming. The process should call HFI1_CMD_DISARM_BUFS
198 * or HFI1_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.
200 unsigned long *user_event_mask
;
201 /* when waiting for rcv or pioavail */
202 wait_queue_head_t wait
;
203 /* rcvhdrq size (for freeing) */
205 /* number of rcvhdrq entries */
207 /* size of each of the rcvhdrq entries */
209 /* mmap of hdrq, must fit in 44 bits */
210 dma_addr_t rcvhdrq_phys
;
211 dma_addr_t rcvhdrqtailaddr_phys
;
212 struct ctxt_eager_bufs egrbufs
;
213 /* this receive context's assigned PIO ACK send context */
214 struct send_context
*sc
;
216 /* dynamic receive available interrupt timeout */
217 u32 rcvavail_timeout
;
219 * number of opens (including slave sub-contexts) on this instance
220 * (ignoring forks, dup, etc. for now)
224 * how much space to leave at start of eager TID entries for
225 * protocol use, on each TID
227 /* instead of calculating it */
229 /* non-zero if ctxt is being shared. */
231 /* non-zero if ctxt is being shared. */
236 /* number of RcvArray groups for this context. */
237 u32 rcv_array_groups
;
238 /* index of first eager TID entry. */
240 /* number of expected TID entries */
242 /* index of first expected TID entry. */
245 struct exp_tid_set tid_group_list
;
246 struct exp_tid_set tid_used_list
;
247 struct exp_tid_set tid_full_list
;
249 /* lock protecting all Expected TID data */
250 struct mutex exp_lock
;
251 /* number of pio bufs for this ctxt (all procs, if shared) */
253 /* first pio buffer for this ctxt */
255 /* chip offset of PIO buffers for this ctxt */
257 /* per-context configuration flags */
259 /* per-context event flags for fileops/intr communication */
260 unsigned long event_flags
;
261 /* WAIT_RCV that timed out, no interrupt */
263 /* WAIT_PIO that timed out, no interrupt */
265 /* WAIT_RCV already happened, no wait */
267 /* WAIT_PIO already happened, no wait */
269 /* total number of polled urgent packets */
271 /* saved total number of polled urgent packets for poll edge trigger */
273 /* same size as task_struct .comm[], command that opened context */
274 char comm
[TASK_COMM_LEN
];
275 /* so file ops can get at unit */
276 struct hfi1_devdata
*dd
;
277 /* so functions that need physical port can get it easily */
278 struct hfi1_pportdata
*ppd
;
279 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
280 void *subctxt_uregbase
;
281 /* An array of pages for the eager receive buffers * N */
282 void *subctxt_rcvegrbuf
;
283 /* An array of pages for the eager header queue entries * N */
284 void *subctxt_rcvhdr_base
;
285 /* The version of the library which opened this ctxt */
287 /* Bitmask of active slaves */
289 /* Type of packets or conditions we want to poll for */
291 /* receive packet sequence counter */
294 /* ctxt rcvhdrq head offset */
297 /* QPs waiting for context processing */
298 struct list_head qp_wait_list
;
299 /* interrupt handling */
300 u64 imask
; /* clear interrupt mask */
301 int ireg
; /* clear interrupt register */
302 unsigned numa_id
; /* numa node of this context */
303 /* verbs stats per CTX */
304 struct hfi1_opcode_stats_perctx
*opstats
;
306 * This is the kernel thread that will keep making
307 * progress on the user sdma requests behind the scenes.
308 * There is one per context (shared contexts use the master's).
310 struct task_struct
*progress
;
311 struct list_head sdma_queues
;
312 /* protect sdma queues */
313 spinlock_t sdma_qlock
;
315 /* Is ASPM interrupt supported for this context */
316 bool aspm_intr_supported
;
317 /* ASPM state (enabled/disabled) for this context */
319 /* Timer for re-enabling ASPM if interrupt activity quietens down */
320 struct timer_list aspm_timer
;
321 /* Lock to serialize between intr, timer intr and user threads */
322 spinlock_t aspm_lock
;
323 /* Is ASPM processing enabled for this context (in intr context) */
324 bool aspm_intr_enable
;
325 /* Last interrupt timestamp */
326 ktime_t aspm_ts_last_intr
;
327 /* Last timestamp at which we scheduled a timer for this context */
328 ktime_t aspm_ts_timer_sched
;
331 * The interrupt handler for a particular receive context can vary
332 * throughout it's lifetime. This is not a lock protected data member so
333 * it must be updated atomically and the prev and new value must always
334 * be valid. Worst case is we process an extra interrupt and up to 64
335 * packets with the wrong interrupt handler.
337 int (*do_interrupt
)(struct hfi1_ctxtdata
*rcd
, int threaded
);
341 * Represents a single packet at a high level. Put commonly computed things in
342 * here so we do not have to keep doing them over and over. The rule of thumb is
343 * if something is used one time to derive some value, store that something in
344 * here. If it is used multiple times, then store the result of that derivation
350 struct hfi1_ctxtdata
*rcd
;
353 struct hfi1_other_headers
*ohdr
;
369 * Private data for snoop/capture support.
371 struct hfi1_snoop_data
{
374 struct device
*class_dev
;
375 /* protect snoop data */
376 spinlock_t snoop_lock
;
377 struct list_head queue
;
378 wait_queue_head_t waitq
;
380 int (*filter_callback
)(void *hdr
, void *data
, void *value
);
381 u64 dcc_cfg
; /* saved value of DCC Cfg register */
384 /* snoop mode_flag values */
385 #define HFI1_PORT_SNOOP_MODE 1U
386 #define HFI1_PORT_CAPTURE_MODE 2U
388 struct rvt_sge_state
;
391 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
392 * Mostly for MADs that set or query link parameters, also ipath
395 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
396 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
397 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
398 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
399 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
400 #define HFI1_IB_CFG_SPD 5 /* current Link spd */
401 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
402 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
403 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
404 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
405 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
406 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
407 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
408 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
409 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
410 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
411 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
412 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
413 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19
414 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
415 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
418 * HFI or Host Link States
420 * These describe the states the driver thinks the logical and physical
421 * states are in. Used as an argument to set_link_state(). Implemented
422 * as bits for easy multi-state checking. The actual state can only be
425 #define __HLS_UP_INIT_BP 0
426 #define __HLS_UP_ARMED_BP 1
427 #define __HLS_UP_ACTIVE_BP 2
428 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */
429 #define __HLS_DN_POLL_BP 4
430 #define __HLS_DN_DISABLE_BP 5
431 #define __HLS_DN_OFFLINE_BP 6
432 #define __HLS_VERIFY_CAP_BP 7
433 #define __HLS_GOING_UP_BP 8
434 #define __HLS_GOING_OFFLINE_BP 9
435 #define __HLS_LINK_COOLDOWN_BP 10
437 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
438 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
439 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
440 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
441 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
442 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
443 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
444 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
445 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
446 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
447 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
449 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
450 #define HLS_DOWN ~(HLS_UP)
452 /* use this MTU size if none other is given */
453 #define HFI1_DEFAULT_ACTIVE_MTU 10240
454 /* use this MTU size as the default maximum */
455 #define HFI1_DEFAULT_MAX_MTU 10240
456 /* default partition key */
457 #define DEFAULT_PKEY 0xffff
460 * Possible fabric manager config parameters for fm_{get,set}_table()
462 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */
463 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */
464 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */
465 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */
466 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */
467 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */
470 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
471 * these are bits so they can be combined, e.g.
472 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
474 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01
475 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02
476 #define HFI1_RCVCTRL_CTXT_ENB 0x04
477 #define HFI1_RCVCTRL_CTXT_DIS 0x08
478 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
479 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
480 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
481 #define HFI1_RCVCTRL_PKEY_DIS 0x80
482 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
483 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
484 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
485 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
486 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
487 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
488 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
489 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
491 /* partition enforcement flags */
492 #define HFI1_PART_ENFORCE_IN 0x1
493 #define HFI1_PART_ENFORCE_OUT 0x2
495 /* how often we check for synthetic counter wrap around */
496 #define SYNTH_CNT_TIME 2
499 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */
500 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */
501 #define CNTR_DISABLED 0x2 /* Disable this counter */
502 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */
503 #define CNTR_VL 0x8 /* Per VL counter */
504 #define CNTR_SDMA 0x10
505 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */
506 #define CNTR_MODE_W 0x0
507 #define CNTR_MODE_R 0x1
509 /* VLs Supported/Operational */
510 #define HFI1_MIN_VLS_SUPPORTED 1
511 #define HFI1_MAX_VLS_SUPPORTED 8
513 static inline void incr_cntr64(u64
*cntr
)
515 if (*cntr
< (u64
)-1LL)
519 static inline void incr_cntr32(u32
*cntr
)
521 if (*cntr
< (u32
)-1LL)
525 #define MAX_NAME_SIZE 64
526 struct hfi1_msix_entry
{
528 struct msix_entry msix
;
530 char name
[MAX_NAME_SIZE
];
534 /* per-SL CCA information */
536 struct hrtimer hrtimer
;
537 struct hfi1_pportdata
*ppd
; /* read-only */
538 int sl
; /* read-only */
539 u16 ccti
; /* read/write - current value of CCTI */
542 struct link_down_reason
{
544 * SMA-facing value. Should be set from .latest when
545 * HLS_UP_* -> HLS_DN_* transition actually occurs.
557 struct vl_arb_cache
{
558 /* protect vl arb cache */
560 struct ib_vl_weight_elem table
[VL_ARB_TABLE_SIZE
];
564 * The structure below encapsulates data relevant to a physical IB Port.
565 * Current chips support only one such port, but the separation
566 * clarifies things a bit. Note that to conform to IB conventions,
567 * port-numbers are one-based. The first or only port is port1.
569 struct hfi1_pportdata
{
570 struct hfi1_ibport ibport_data
;
572 struct hfi1_devdata
*dd
;
573 struct kobject pport_cc_kobj
;
574 struct kobject sc2vl_kobj
;
575 struct kobject sl2sc_kobj
;
576 struct kobject vl2mtu_kobj
;
580 struct qsfp_data qsfp_info
;
582 /* GUID for this interface, in host order */
584 /* GUID for peer interface, in host order */
587 /* up or down physical link state */
591 * this address is mapped read-only into user processes so they can
592 * get status cheaply, whenever they want. One qword of status per port
596 /* SendDMA related entries */
598 struct workqueue_struct
*hfi1_wq
;
600 /* move out of interrupt context */
601 struct work_struct link_vc_work
;
602 struct work_struct link_up_work
;
603 struct work_struct link_down_work
;
604 struct work_struct sma_message_work
;
605 struct work_struct freeze_work
;
606 struct work_struct link_downgrade_work
;
607 struct work_struct link_bounce_work
;
608 /* host link state variables */
609 struct mutex hls_lock
;
612 spinlock_t sdma_alllock ____cacheline_aligned_in_smp
;
614 u32 lstate
; /* logical link state */
616 /* these are the "32 bit" regs */
618 u32 ibmtu
; /* The MTU programmed for this unit */
620 * Current max size IB packet (in bytes) including IB headers, that
621 * we can send. Changes when ibmtu changes.
624 u32 current_egress_rate
; /* units [10^6 bits/sec] */
625 /* LID programmed for this instance */
627 /* list of pkeys programmed; 0 if not set */
628 u16 pkeys
[MAX_PKEY_VALUES
];
629 u16 link_width_supported
;
630 u16 link_width_downgrade_supported
;
631 u16 link_speed_supported
;
632 u16 link_width_enabled
;
633 u16 link_width_downgrade_enabled
;
634 u16 link_speed_enabled
;
635 u16 link_width_active
;
636 u16 link_width_downgrade_tx_active
;
637 u16 link_width_downgrade_rx_active
;
638 u16 link_speed_active
;
641 u8 actual_vls_operational
;
642 /* LID mask control */
644 /* Rx Polarity inversion (compensate for ~tx on partner) */
647 u8 hw_pidx
; /* physical port index */
648 u8 port
; /* IB port number and index into dd->pports - 1 */
649 /* type of neighbor node */
652 u8 neighbor_fm_security
; /* 1 if firmware checking is disabled */
653 u8 neighbor_port_number
;
654 u8 is_sm_config_started
;
655 u8 offline_disabled_reason
;
656 u8 is_active_optimize_enabled
;
657 u8 driver_link_ready
; /* driver ready for active link */
658 u8 link_enabled
; /* link enabled? */
660 u8 local_tx_rate
; /* rate given to 8051 firmware */
661 u8 last_pstate
; /* info only */
663 /* placeholders for IB MAD packet settings */
664 u8 overrun_threshold
;
665 u8 phy_error_threshold
;
667 /* Used to override LED behavior for things like maintenance beaconing*/
669 * Alternates per phase of blink
670 * [0] holds LED off duration, [1] holds LED on duration
672 unsigned long led_override_vals
[2];
673 u8 led_override_phase
; /* LSB picks from vals[] */
674 atomic_t led_override_timer_active
;
675 /* Used to flash LEDs in override mode */
676 struct timer_list led_override_timer
;
682 * cca_timer_lock protects access to the per-SL cca_timer
683 * structures (specifically the ccti member).
685 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp
;
686 struct cca_timer cca_timer
[OPA_MAX_SLS
];
688 /* List of congestion control table entries */
689 struct ib_cc_table_entry_shadow ccti_entries
[CC_TABLE_SHADOW_MAX
];
691 /* congestion entries, each entry corresponding to a SL */
692 struct opa_congestion_setting_entry_shadow
693 congestion_entries
[OPA_MAX_SLS
];
696 * cc_state_lock protects (write) access to the per-port
699 spinlock_t cc_state_lock ____cacheline_aligned_in_smp
;
701 struct cc_state __rcu
*cc_state
;
703 /* Total number of congestion control table entries */
706 /* Bit map identifying service level */
707 u32 cc_sl_control_map
;
709 /* CA's max number of 64 entry units in the congestion control table */
710 u8 cc_max_table_entries
;
713 * begin congestion log related entries
714 * cc_log_lock protects all congestion log related data
716 spinlock_t cc_log_lock ____cacheline_aligned_in_smp
;
717 u8 threshold_cong_event_map
[OPA_MAX_SLS
/ 8];
718 u16 threshold_event_counter
;
719 struct opa_hfi1_cong_log_event_internal cc_events
[OPA_CONG_LOG_ELEMS
];
720 int cc_log_idx
; /* index for logging events */
721 int cc_mad_idx
; /* index for reporting events */
722 /* end congestion log related entries */
724 struct vl_arb_cache vl_arb_cache
[MAX_PRIO_TABLE
];
726 /* port relative counter buffer */
728 /* port relative synthetic counter buffer */
730 /* port_xmit_discards are synthesized from different egress errors */
731 u64 port_xmit_discards
;
732 u64 port_xmit_discards_vl
[C_VL_COUNT
];
733 u64 port_xmit_constraint_errors
;
734 u64 port_rcv_constraint_errors
;
735 /* count of 'link_err' interrupts from DC */
737 /* number of times link retrained successfully */
739 /* number of times a link unknown frame was reported */
740 u64 unknown_frame_count
;
741 /* port_ltp_crc_mode is returned in 'portinfo' MADs */
742 u16 port_ltp_crc_mode
;
743 /* port_crc_mode_enabled is the crc we support */
744 u8 port_crc_mode_enabled
;
745 /* mgmt_allowed is also returned in 'portinfo' MADs */
747 u8 part_enforce
; /* partition enforcement flags */
748 struct link_down_reason local_link_down_reason
;
749 struct link_down_reason neigh_link_down_reason
;
750 /* Value to be sent to link peer on LinkDown .*/
751 u8 remote_link_down_reason
;
752 /* Error events that will cause a port bounce. */
753 u32 port_error_action
;
754 struct work_struct linkstate_active_work
;
755 /* Does this port need to prescan for FECNs */
759 typedef int (*rhf_rcv_function_ptr
)(struct hfi1_packet
*packet
);
761 typedef void (*opcode_handler
)(struct hfi1_packet
*packet
);
763 /* return values for the RHF receive functions */
764 #define RHF_RCV_CONTINUE 0 /* keep going */
765 #define RHF_RCV_DONE 1 /* stop, this packet processed */
766 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */
768 struct rcv_array_data
{
776 struct send_context
*sc
;
779 /* 16 to directly index */
780 #define PER_VL_SEND_CONTEXTS 16
782 struct err_info_rcvport
{
788 struct err_info_constraint
{
795 unsigned int curr
; /* current temperature */
796 unsigned int lo_lim
; /* low temperature limit */
797 unsigned int hi_lim
; /* high temperature limit */
798 unsigned int crit_lim
; /* critical temperature limit */
799 u8 triggers
; /* temperature triggers */
802 struct hfi1_i2c_bus
{
803 struct hfi1_devdata
*controlling_dd
; /* current controlling device */
804 struct i2c_adapter adapter
; /* bus details */
805 struct i2c_algo_bit_data algo
; /* bus algorithm details */
806 int num
; /* bus number, 0 or 1 */
809 /* common data between shared ASIC HFIs */
810 struct hfi1_asic_data
{
811 struct hfi1_devdata
*dds
[2]; /* back pointers */
812 struct mutex asic_resource_mutex
;
813 struct hfi1_i2c_bus
*i2c_bus0
;
814 struct hfi1_i2c_bus
*i2c_bus1
;
817 /* device data struct now contains only "general per-device" info.
818 * fields related to a physical IB port are in a hfi1_pportdata struct.
823 #define BOARD_VERS_MAX 96 /* how long the version string can be */
824 #define SERIAL_MAX 16 /* length of the serial number */
826 typedef int (*send_routine
)(struct rvt_qp
*, struct hfi1_pkt_state
*, u64
);
827 struct hfi1_devdata
{
828 struct hfi1_ibdev verbs_dev
; /* must be first */
829 struct list_head list
;
830 /* pointers to related structs for this device */
831 /* pci access data structure */
832 struct pci_dev
*pcidev
;
833 struct cdev user_cdev
;
834 struct cdev diag_cdev
;
836 struct device
*user_device
;
837 struct device
*diag_device
;
838 struct device
*ui_device
;
840 /* mem-mapped pointer to base of chip regs */
841 u8 __iomem
*kregbase
;
842 /* end of mem-mapped chip space excluding sendbuf and user regs */
844 /* physical address of chip for io_remap, etc. */
845 resource_size_t physaddr
;
846 /* receive context data */
847 struct hfi1_ctxtdata
**rcd
;
848 /* send context data */
849 struct send_context_info
*send_contexts
;
850 /* map hardware send contexts to software index */
852 /* spinlock for allocating and releasing send context resources */
854 /* Per VL data. Enough for all VLs but not all elements are set/used. */
855 struct per_vl_data vld
[PER_VL_SEND_CONTEXTS
];
856 /* lock for pio_map */
857 spinlock_t pio_map_lock
;
858 /* array of kernel send contexts */
859 struct send_context
**kernel_send_context
;
860 /* array of vl maps */
861 struct pio_vl_map __rcu
*pio_map
;
862 /* seqlock for sc2vl */
863 seqlock_t sc2vl_lock
;
865 /* Send Context initialization lock. */
866 spinlock_t sc_init_lock
;
868 /* fields common to all SDMA engines */
870 /* default flags to last descriptor */
872 volatile __le64
*sdma_heads_dma
; /* DMA'ed by chip */
873 dma_addr_t sdma_heads_phys
;
874 void *sdma_pad_dma
; /* DMA'ed by chip */
875 dma_addr_t sdma_pad_phys
;
876 /* for deallocation */
877 size_t sdma_heads_size
;
878 /* number from the chip */
879 u32 chip_sdma_engines
;
882 /* lock for sdma_map */
883 spinlock_t sde_map_lock
;
884 /* array of engines sized by num_sdma */
885 struct sdma_engine
*per_sdma
;
886 /* array of vl maps */
887 struct sdma_vl_map __rcu
*sdma_map
;
888 /* SPC freeze waitqueue and variable */
889 wait_queue_head_t sdma_unfreeze_wq
;
890 atomic_t sdma_unfreeze_count
;
892 /* common data between shared ASIC HFIs in this OS */
893 struct hfi1_asic_data
*asic_data
;
895 /* hfi1_pportdata, points to array of (physical) port-specific
896 * data structs, indexed by pidx (0..n-1)
898 struct hfi1_pportdata
*pport
;
900 /* mem-mapped pointer to base of PIO buffers */
901 void __iomem
*piobase
;
903 * write-combining mem-mapped pointer to base of RcvArray
906 void __iomem
*rcvarray_wc
;
908 * credit return base - a per-NUMA range of DMA address that
909 * the chip will use to update the per-context free counter
911 struct credit_return_base
*cr_base
;
913 /* send context numbers and sizes for each type */
914 struct sc_config_sizes sc_sizes
[SC_MAX
];
916 u32 lcb_access_count
; /* count of LCB users */
918 char *boardname
; /* human readable board info */
920 /* device (not port) flags, basically device capabilities */
927 /* percpu int_counter */
928 u64 __percpu
*int_counter
;
929 u64 __percpu
*rcv_limit
;
930 u64 __percpu
*send_schedule
;
931 /* number of receive contexts in use by the driver */
932 u32 num_rcv_contexts
;
933 /* number of pio send contexts in use by the driver */
934 u32 num_send_contexts
;
936 * number of ctxts available for PSM open
939 /* total number of available user/PSM contexts */
940 u32 num_user_contexts
;
941 /* base receive interrupt timeout, in CSR units */
942 u32 rcv_intr_timeout_csr
;
944 u64 __iomem
*egrtidbase
;
945 spinlock_t sendctrl_lock
; /* protect changes to SendCtrl */
946 spinlock_t rcvctrl_lock
; /* protect changes to RcvCtrl */
947 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */
948 spinlock_t uctxt_lock
; /* rcd and user context changes */
949 /* exclusive access to 8051 */
950 spinlock_t dc8051_lock
;
951 /* exclusive access to 8051 memory */
952 spinlock_t dc8051_memlock
;
953 int dc8051_timed_out
; /* remember if the 8051 timed out */
955 * A page that will hold event notification bitmaps for all
956 * contexts. This page will be mapped into all processes.
958 unsigned long *events
;
960 * per unit status, see also portdata statusp
961 * mapped read-only into user processes so they can get unit and
962 * IB link status cheaply
964 struct hfi1_status
*status
;
965 u32 freezelen
; /* max length of freezemsg */
967 /* revision register shadow */
969 /* Base GUID for device (network order) */
972 /* these are the "32 bit" regs */
974 /* value we put in kr_rcvhdrsize */
976 /* number of receive contexts the chip supports */
977 u32 chip_rcv_contexts
;
978 /* number of receive array entries */
979 u32 chip_rcv_array_count
;
980 /* number of PIO send contexts the chip supports */
981 u32 chip_send_contexts
;
982 /* number of bytes in the PIO memory buffer */
983 u32 chip_pio_mem_size
;
984 /* number of bytes in the SDMA memory buffer */
985 u32 chip_sdma_mem_size
;
987 /* size of each rcvegrbuffer */
990 u16 rcvegrbufsize_shift
;
991 /* both sides of the PCIe link are gen3 capable */
992 u8 link_gen3_capable
;
993 /* localbus width (1, 2,4,8,16,32) from config space */
995 /* localbus speed in MHz */
997 int unit
; /* unit # of this chip */
998 int node
; /* home node of this chip */
1000 /* save these PCI fields to restore after a reset */
1013 * ASCII serial number, from flash, large enough for original
1014 * all digit strings, and longer serial number format
1016 u8 serial
[SERIAL_MAX
];
1017 /* human readable board version */
1018 u8 boardversion
[BOARD_VERS_MAX
];
1019 u8 lbus_info
[32]; /* human readable localbus info */
1020 /* chip major rev, from CceRevision */
1022 /* chip minor rev, from CceRevision */
1026 /* implementation code */
1028 /* default link down value (poll/sleep) */
1030 /* vAU of this device */
1032 /* vCU of this device */
1034 /* link credits of this device */
1036 /* initial vl15 credits to use */
1039 /* Misc small ints */
1040 /* Number of physical ports available */
1042 /* Lowest context number which can be used by user processes */
1048 u16 rhf_offset
; /* offset of RHF within receive header entry */
1049 u16 irev
; /* implementation revision */
1050 u16 dc8051_ver
; /* 8051 firmware version */
1052 struct platform_config platform_config
;
1053 struct platform_config_cache pcfg_cache
;
1055 struct diag_client
*diag_client
;
1056 spinlock_t hfi1_diag_trans_lock
; /* protect diag observer ops */
1058 u8 psxmitwait_supported
;
1059 /* cycle length of PS* counters in HW (in picoseconds) */
1060 u16 psxmitwait_check_rate
;
1061 /* high volume overflow errors deferred to tasklet */
1062 struct tasklet_struct error_tasklet
;
1064 /* MSI-X information */
1065 struct hfi1_msix_entry
*msix_entries
;
1066 u32 num_msix_entries
;
1068 /* INTx information */
1069 u32 requested_intx_irq
; /* did we request one? */
1070 char intx_name
[MAX_NAME_SIZE
]; /* INTx name */
1072 /* general interrupt: mask of handled interrupts */
1073 u64 gi_mask
[CCE_NUM_INT_CSRS
];
1075 struct rcv_array_data rcv_entries
;
1078 * 64 bit synthetic counters
1080 struct timer_list synth_stats_timer
;
1086 size_t cntrnameslen
;
1092 * remembered values for synthetic counters
1101 char *portcntrnames
;
1102 size_t portcntrnameslen
;
1104 struct hfi1_snoop_data hfi1_snoop
;
1106 struct err_info_rcvport err_info_rcvport
;
1107 struct err_info_constraint err_info_rcv_constraint
;
1108 struct err_info_constraint err_info_xmit_constraint
;
1109 u8 err_info_uncorrectable
;
1110 u8 err_info_fmconfig
;
1112 atomic_t drop_packet
;
1116 * Software counters for the status bits defined by the
1117 * associated error status registers
1119 u64 cce_err_status_cnt
[NUM_CCE_ERR_STATUS_COUNTERS
];
1120 u64 rcv_err_status_cnt
[NUM_RCV_ERR_STATUS_COUNTERS
];
1121 u64 misc_err_status_cnt
[NUM_MISC_ERR_STATUS_COUNTERS
];
1122 u64 send_pio_err_status_cnt
[NUM_SEND_PIO_ERR_STATUS_COUNTERS
];
1123 u64 send_dma_err_status_cnt
[NUM_SEND_DMA_ERR_STATUS_COUNTERS
];
1124 u64 send_egress_err_status_cnt
[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS
];
1125 u64 send_err_status_cnt
[NUM_SEND_ERR_STATUS_COUNTERS
];
1127 /* Software counter that spans all contexts */
1128 u64 sw_ctxt_err_status_cnt
[NUM_SEND_CTXT_ERR_STATUS_COUNTERS
];
1129 /* Software counter that spans all DMA engines */
1130 u64 sw_send_dma_eng_err_status_cnt
[
1131 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS
];
1132 /* Software counter that aggregates all cce_err_status errors */
1133 u64 sw_cce_err_status_aggregate
;
1134 /* Software counter that aggregates all bypass packet rcv errors */
1135 u64 sw_rcv_bypass_packet_errors
;
1136 /* receive interrupt functions */
1137 rhf_rcv_function_ptr
*rhf_rcv_function_map
;
1138 rhf_rcv_function_ptr normal_rhf_rcv_functions
[8];
1141 * Handlers for outgoing data so that snoop/capture does not
1142 * have to have its hooks in the send path
1144 send_routine process_pio_send
;
1145 send_routine process_dma_send
;
1146 void (*pio_inline_send
)(struct hfi1_devdata
*dd
, struct pio_buf
*pbuf
,
1147 u64 pbc
, const void *from
, size_t count
);
1149 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1153 /* Timer and counter used to detect RcvBufOvflCnt changes */
1154 struct timer_list rcverr_timer
;
1157 wait_queue_head_t event_queue
;
1159 /* Save the enabled LCB error bits */
1163 /* receive context tail dummy address */
1164 __le64
*rcvhdrtail_dummy_kvaddr
;
1165 dma_addr_t rcvhdrtail_dummy_physaddr
;
1167 bool eprom_available
; /* true if EPROM is available for this device */
1168 bool aspm_supported
; /* Does HW support ASPM */
1169 bool aspm_enabled
; /* ASPM state: enabled/disabled */
1170 /* Serialize ASPM enable/disable between multiple verbs contexts */
1171 spinlock_t aspm_lock
;
1172 /* Number of verbs contexts which have disabled ASPM */
1173 atomic_t aspm_disabled_cnt
;
1175 struct hfi1_affinity
*affinity
;
1176 struct kobject kobj
;
1179 /* 8051 firmware version helper */
1180 #define dc8051_ver(a, b) ((a) << 8 | (b))
1181 #define dc8051_ver_maj(a) ((a & 0xff00) >> 8)
1182 #define dc8051_ver_min(a) (a & 0x00ff)
1184 /* f_put_tid types */
1185 #define PT_EXPECTED 0
1187 #define PT_INVALID 2
1191 struct mmu_rb_handler
;
1193 /* Private data for file operations */
1194 struct hfi1_filedata
{
1195 struct hfi1_ctxtdata
*uctxt
;
1197 struct hfi1_user_sdma_comp_q
*cq
;
1198 struct hfi1_user_sdma_pkt_q
*pq
;
1199 /* for cpu affinity; -1 if none */
1202 struct mmu_rb_handler
*handler
;
1203 struct tid_rb_node
**entry_to_rb
;
1204 spinlock_t tid_lock
; /* protect tid_[limit,used] counters */
1208 u32 invalid_tid_idx
;
1209 /* protect invalid_tids array and invalid_tid_idx */
1210 spinlock_t invalid_lock
;
1211 struct mm_struct
*mm
;
1214 extern struct list_head hfi1_dev_list
;
1215 extern spinlock_t hfi1_devs_lock
;
1216 struct hfi1_devdata
*hfi1_lookup(int unit
);
1217 extern u32 hfi1_cpulist_count
;
1218 extern unsigned long *hfi1_cpulist
;
1220 extern unsigned int snoop_drop_send
;
1221 extern unsigned int snoop_force_capture
;
1222 int hfi1_init(struct hfi1_devdata
*, int);
1223 int hfi1_count_units(int *npresentp
, int *nupp
);
1224 int hfi1_count_active_units(void);
1226 int hfi1_diag_add(struct hfi1_devdata
*);
1227 void hfi1_diag_remove(struct hfi1_devdata
*);
1228 void handle_linkup_change(struct hfi1_devdata
*dd
, u32 linkup
);
1230 void handle_user_interrupt(struct hfi1_ctxtdata
*rcd
);
1232 int hfi1_create_rcvhdrq(struct hfi1_devdata
*, struct hfi1_ctxtdata
*);
1233 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata
*);
1234 int hfi1_create_ctxts(struct hfi1_devdata
*dd
);
1235 struct hfi1_ctxtdata
*hfi1_create_ctxtdata(struct hfi1_pportdata
*, u32
, int);
1236 void hfi1_init_pportdata(struct pci_dev
*, struct hfi1_pportdata
*,
1237 struct hfi1_devdata
*, u8
, u8
);
1238 void hfi1_free_ctxtdata(struct hfi1_devdata
*, struct hfi1_ctxtdata
*);
1240 int handle_receive_interrupt(struct hfi1_ctxtdata
*, int);
1241 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata
*, int);
1242 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata
*, int);
1243 void set_all_slowpath(struct hfi1_devdata
*dd
);
1245 extern const struct pci_device_id hfi1_pci_tbl
[];
1247 /* receive packet handler dispositions */
1248 #define RCV_PKT_OK 0x0 /* keep going */
1249 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */
1250 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */
1252 /* calculate the current RHF address */
1253 static inline __le32
*get_rhf_addr(struct hfi1_ctxtdata
*rcd
)
1255 return (__le32
*)rcd
->rcvhdrq
+ rcd
->head
+ rcd
->dd
->rhf_offset
;
1258 int hfi1_reset_device(int);
1260 /* return the driver's idea of the logical OPA port state */
1261 static inline u32
driver_lstate(struct hfi1_pportdata
*ppd
)
1263 return ppd
->lstate
; /* use the cached value */
1266 void receive_interrupt_work(struct work_struct
*work
);
1268 /* extract service channel from header and rhf */
1269 static inline int hdr2sc(struct hfi1_message_header
*hdr
, u64 rhf
)
1271 return ((be16_to_cpu(hdr
->lrh
[0]) >> 12) & 0xf) |
1272 ((!!(rhf_dc_info(rhf
))) << 4);
1275 static inline u16
generate_jkey(kuid_t uid
)
1277 return from_kuid(current_user_ns(), uid
) & 0xffff;
1281 * active_egress_rate
1283 * returns the active egress rate in units of [10^6 bits/sec]
1285 static inline u32
active_egress_rate(struct hfi1_pportdata
*ppd
)
1287 u16 link_speed
= ppd
->link_speed_active
;
1288 u16 link_width
= ppd
->link_width_active
;
1291 if (link_speed
== OPA_LINK_SPEED_25G
)
1292 egress_rate
= 25000;
1293 else /* assume OPA_LINK_SPEED_12_5G */
1294 egress_rate
= 12500;
1296 switch (link_width
) {
1297 case OPA_LINK_WIDTH_4X
:
1300 case OPA_LINK_WIDTH_3X
:
1303 case OPA_LINK_WIDTH_2X
:
1307 /* assume IB_WIDTH_1X */
1317 * Returns the number of 'fabric clock cycles' to egress a packet
1318 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1319 * rate is (approximately) 805 MHz, the units of the returned value
1322 static inline u32
egress_cycles(u32 len
, u32 rate
)
1329 * (length) [bits] / (rate) [bits/sec]
1330 * ---------------------------------------------------
1331 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1334 cycles
= len
* 8; /* bits */
1341 void set_link_ipg(struct hfi1_pportdata
*ppd
);
1342 void process_becn(struct hfi1_pportdata
*ppd
, u8 sl
, u16 rlid
, u32 lqpn
,
1343 u32 rqpn
, u8 svc_type
);
1344 void return_cnp(struct hfi1_ibport
*ibp
, struct rvt_qp
*qp
, u32 remote_qpn
,
1345 u32 pkey
, u32 slid
, u32 dlid
, u8 sc5
,
1346 const struct ib_grh
*old_grh
);
1347 #define PKEY_CHECK_INVALID -1
1348 int egress_pkey_check(struct hfi1_pportdata
*ppd
, __be16
*lrh
, __be32
*bth
,
1349 u8 sc5
, int8_t s_pkey_index
);
1351 #define PACKET_EGRESS_TIMEOUT 350
1352 static inline void pause_for_credit_return(struct hfi1_devdata
*dd
)
1354 /* Pause at least 1us, to ensure chip returns all credits */
1355 u32 usec
= cclock_to_ns(dd
, PACKET_EGRESS_TIMEOUT
) / 1000;
1357 udelay(usec
? usec
: 1);
1361 * sc_to_vlt() reverse lookup sc to vl
1365 static inline u8
sc_to_vlt(struct hfi1_devdata
*dd
, u8 sc5
)
1370 if (sc5
>= OPA_MAX_SCS
)
1374 seq
= read_seqbegin(&dd
->sc2vl_lock
);
1375 rval
= *(((u8
*)dd
->sc2vl
) + sc5
);
1376 } while (read_seqretry(&dd
->sc2vl_lock
, seq
));
1381 #define PKEY_MEMBER_MASK 0x8000
1382 #define PKEY_LOW_15_MASK 0x7fff
1385 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1386 * being an entry from the ingress partition key table), return 0
1387 * otherwise. Use the matching criteria for ingress partition keys
1388 * specified in the OPAv1 spec., section 9.10.14.
1390 static inline int ingress_pkey_matches_entry(u16 pkey
, u16 ent
)
1392 u16 mkey
= pkey
& PKEY_LOW_15_MASK
;
1393 u16 ment
= ent
& PKEY_LOW_15_MASK
;
1397 * If pkey[15] is clear (limited partition member),
1398 * is bit 15 in the corresponding table element
1399 * clear (limited member)?
1401 if (!(pkey
& PKEY_MEMBER_MASK
))
1402 return !!(ent
& PKEY_MEMBER_MASK
);
1409 * ingress_pkey_table_search - search the entire pkey table for
1410 * an entry which matches 'pkey'. return 0 if a match is found,
1413 static int ingress_pkey_table_search(struct hfi1_pportdata
*ppd
, u16 pkey
)
1417 for (i
= 0; i
< MAX_PKEY_VALUES
; i
++) {
1418 if (ingress_pkey_matches_entry(pkey
, ppd
->pkeys
[i
]))
1425 * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1426 * i.e., increment port_rcv_constraint_errors for the port, and record
1427 * the 'error info' for this failure.
1429 static void ingress_pkey_table_fail(struct hfi1_pportdata
*ppd
, u16 pkey
,
1432 struct hfi1_devdata
*dd
= ppd
->dd
;
1434 incr_cntr64(&ppd
->port_rcv_constraint_errors
);
1435 if (!(dd
->err_info_rcv_constraint
.status
& OPA_EI_STATUS_SMASK
)) {
1436 dd
->err_info_rcv_constraint
.status
|= OPA_EI_STATUS_SMASK
;
1437 dd
->err_info_rcv_constraint
.slid
= slid
;
1438 dd
->err_info_rcv_constraint
.pkey
= pkey
;
1443 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1444 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1445 * is a hint as to the best place in the partition key table to begin
1446 * searching. This function should not be called on the data path because
1447 * of performance reasons. On datapath pkey check is expected to be done
1448 * by HW and rcv_pkey_check function should be called instead.
1450 static inline int ingress_pkey_check(struct hfi1_pportdata
*ppd
, u16 pkey
,
1451 u8 sc5
, u8 idx
, u16 slid
)
1453 if (!(ppd
->part_enforce
& HFI1_PART_ENFORCE_IN
))
1456 /* If SC15, pkey[0:14] must be 0x7fff */
1457 if ((sc5
== 0xf) && ((pkey
& PKEY_LOW_15_MASK
) != PKEY_LOW_15_MASK
))
1460 /* Is the pkey = 0x0, or 0x8000? */
1461 if ((pkey
& PKEY_LOW_15_MASK
) == 0)
1464 /* The most likely matching pkey has index 'idx' */
1465 if (ingress_pkey_matches_entry(pkey
, ppd
->pkeys
[idx
]))
1468 /* no match - try the whole table */
1469 if (!ingress_pkey_table_search(ppd
, pkey
))
1473 ingress_pkey_table_fail(ppd
, pkey
, slid
);
1478 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1479 * otherwise. It only ensures pkey is vlid for QP0. This function
1480 * should be called on the data path instead of ingress_pkey_check
1481 * as on data path, pkey check is done by HW (except for QP0).
1483 static inline int rcv_pkey_check(struct hfi1_pportdata
*ppd
, u16 pkey
,
1486 if (!(ppd
->part_enforce
& HFI1_PART_ENFORCE_IN
))
1489 /* If SC15, pkey[0:14] must be 0x7fff */
1490 if ((sc5
== 0xf) && ((pkey
& PKEY_LOW_15_MASK
) != PKEY_LOW_15_MASK
))
1495 ingress_pkey_table_fail(ppd
, pkey
, slid
);
1501 /* MTU enumeration, 256-4k match IB */
1503 #define OPA_MTU_256 1
1504 #define OPA_MTU_512 2
1505 #define OPA_MTU_1024 3
1506 #define OPA_MTU_2048 4
1507 #define OPA_MTU_4096 5
1509 u32
lrh_max_header_bytes(struct hfi1_devdata
*dd
);
1510 int mtu_to_enum(u32 mtu
, int default_if_bad
);
1511 u16
enum_to_mtu(int);
1512 static inline int valid_ib_mtu(unsigned int mtu
)
1514 return mtu
== 256 || mtu
== 512 ||
1515 mtu
== 1024 || mtu
== 2048 ||
1519 static inline int valid_opa_max_mtu(unsigned int mtu
)
1521 return mtu
>= 2048 &&
1522 (valid_ib_mtu(mtu
) || mtu
== 8192 || mtu
== 10240);
1525 int set_mtu(struct hfi1_pportdata
*);
1527 int hfi1_set_lid(struct hfi1_pportdata
*, u32
, u8
);
1528 void hfi1_disable_after_error(struct hfi1_devdata
*);
1529 int hfi1_set_uevent_bits(struct hfi1_pportdata
*, const int);
1530 int hfi1_rcvbuf_validate(u32
, u8
, u16
*);
1532 int fm_get_table(struct hfi1_pportdata
*, int, void *);
1533 int fm_set_table(struct hfi1_pportdata
*, int, void *);
1535 void set_up_vl15(struct hfi1_devdata
*dd
, u8 vau
, u16 vl15buf
);
1536 void reset_link_credits(struct hfi1_devdata
*dd
);
1537 void assign_remote_cm_au_table(struct hfi1_devdata
*dd
, u8 vcu
);
1539 int snoop_recv_handler(struct hfi1_packet
*packet
);
1540 int snoop_send_dma_handler(struct rvt_qp
*qp
, struct hfi1_pkt_state
*ps
,
1542 int snoop_send_pio_handler(struct rvt_qp
*qp
, struct hfi1_pkt_state
*ps
,
1544 void snoop_inline_pio_send(struct hfi1_devdata
*dd
, struct pio_buf
*pbuf
,
1545 u64 pbc
, const void *from
, size_t count
);
1546 int set_buffer_control(struct hfi1_pportdata
*ppd
, struct buffer_control
*bc
);
1548 static inline struct hfi1_devdata
*dd_from_ppd(struct hfi1_pportdata
*ppd
)
1553 static inline struct hfi1_devdata
*dd_from_dev(struct hfi1_ibdev
*dev
)
1555 return container_of(dev
, struct hfi1_devdata
, verbs_dev
);
1558 static inline struct hfi1_devdata
*dd_from_ibdev(struct ib_device
*ibdev
)
1560 return dd_from_dev(to_idev(ibdev
));
1563 static inline struct hfi1_pportdata
*ppd_from_ibp(struct hfi1_ibport
*ibp
)
1565 return container_of(ibp
, struct hfi1_pportdata
, ibport_data
);
1568 static inline struct hfi1_ibdev
*dev_from_rdi(struct rvt_dev_info
*rdi
)
1570 return container_of(rdi
, struct hfi1_ibdev
, rdi
);
1573 static inline struct hfi1_ibport
*to_iport(struct ib_device
*ibdev
, u8 port
)
1575 struct hfi1_devdata
*dd
= dd_from_ibdev(ibdev
);
1576 unsigned pidx
= port
- 1; /* IB number port from 1, hdw from 0 */
1578 WARN_ON(pidx
>= dd
->num_pports
);
1579 return &dd
->pport
[pidx
].ibport_data
;
1582 void hfi1_process_ecn_slowpath(struct rvt_qp
*qp
, struct hfi1_packet
*pkt
,
1584 static inline bool process_ecn(struct rvt_qp
*qp
, struct hfi1_packet
*pkt
,
1587 struct hfi1_other_headers
*ohdr
= pkt
->ohdr
;
1590 bth1
= be32_to_cpu(ohdr
->bth
[1]);
1591 if (unlikely(bth1
& (HFI1_BECN_SMASK
| HFI1_FECN_SMASK
))) {
1592 hfi1_process_ecn_slowpath(qp
, pkt
, do_cnp
);
1593 return bth1
& HFI1_FECN_SMASK
;
1599 * Return the indexed PKEY from the port PKEY table.
1601 static inline u16
hfi1_get_pkey(struct hfi1_ibport
*ibp
, unsigned index
)
1603 struct hfi1_pportdata
*ppd
= ppd_from_ibp(ibp
);
1606 if (index
>= ARRAY_SIZE(ppd
->pkeys
))
1609 ret
= ppd
->pkeys
[index
];
1615 * Called by readers of cc_state only, must call under rcu_read_lock().
1617 static inline struct cc_state
*get_cc_state(struct hfi1_pportdata
*ppd
)
1619 return rcu_dereference(ppd
->cc_state
);
1623 * Called by writers of cc_state only, must call under cc_state_lock.
1626 struct cc_state
*get_cc_state_protected(struct hfi1_pportdata
*ppd
)
1628 return rcu_dereference_protected(ppd
->cc_state
,
1629 lockdep_is_held(&ppd
->cc_state_lock
));
1633 * values for dd->flags (_device_ related flags)
1635 #define HFI1_INITTED 0x1 /* chip and driver up and initted */
1636 #define HFI1_PRESENT 0x2 /* chip accesses can be done */
1637 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */
1638 #define HFI1_HAS_SDMA_TIMEOUT 0x8
1639 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
1640 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
1642 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1643 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1645 /* ctxt_flag bit offsets */
1646 /* context has been setup */
1647 #define HFI1_CTXT_SETUP_DONE 1
1648 /* waiting for a packet to arrive */
1649 #define HFI1_CTXT_WAITING_RCV 2
1650 /* master has not finished initializing */
1651 #define HFI1_CTXT_MASTER_UNINIT 4
1652 /* waiting for an urgent packet to arrive */
1653 #define HFI1_CTXT_WAITING_URG 5
1655 /* free up any allocated data at closes */
1656 struct hfi1_devdata
*hfi1_init_dd(struct pci_dev
*,
1657 const struct pci_device_id
*);
1658 void hfi1_free_devdata(struct hfi1_devdata
*);
1659 void cc_state_reclaim(struct rcu_head
*rcu
);
1660 struct hfi1_devdata
*hfi1_alloc_devdata(struct pci_dev
*pdev
, size_t extra
);
1662 /* LED beaconing functions */
1663 void hfi1_start_led_override(struct hfi1_pportdata
*ppd
, unsigned int timeon
,
1664 unsigned int timeoff
);
1665 void shutdown_led_override(struct hfi1_pportdata
*ppd
);
1667 #define HFI1_CREDIT_RETURN_RATE (100)
1670 * The number of words for the KDETH protocol field. If this is
1671 * larger then the actual field used, then part of the payload
1672 * will be in the header.
1674 * Optimally, we want this sized so that a typical case will
1675 * use full cache lines. The typical local KDETH header would
1686 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
1688 #define DEFAULT_RCVHDRSIZE 9
1691 * Maximal header byte count:
1702 * We also want to maintain a cache line alignment to assist DMA'ing
1703 * of the header bytes. Round up to a good size.
1705 #define DEFAULT_RCVHDR_ENTSIZE 32
1707 bool hfi1_can_pin_pages(struct hfi1_devdata
*dd
, struct mm_struct
*mm
,
1708 u32 nlocked
, u32 npages
);
1709 int hfi1_acquire_user_pages(struct mm_struct
*mm
, unsigned long vaddr
,
1710 size_t npages
, bool writable
, struct page
**pages
);
1711 void hfi1_release_user_pages(struct mm_struct
*mm
, struct page
**p
,
1712 size_t npages
, bool dirty
);
1714 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata
*rcd
)
1716 *((u64
*)rcd
->rcvhdrtail_kvaddr
) = 0ULL;
1719 static inline u32
get_rcvhdrtail(const struct hfi1_ctxtdata
*rcd
)
1722 * volatile because it's a DMA target from the chip, routine is
1723 * inlined, and don't want register caching or reordering.
1725 return (u32
)le64_to_cpu(*rcd
->rcvhdrtail_kvaddr
);
1732 extern const char ib_hfi1_version
[];
1734 int hfi1_device_create(struct hfi1_devdata
*);
1735 void hfi1_device_remove(struct hfi1_devdata
*);
1737 int hfi1_create_port_files(struct ib_device
*ibdev
, u8 port_num
,
1738 struct kobject
*kobj
);
1739 int hfi1_verbs_register_sysfs(struct hfi1_devdata
*);
1740 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata
*);
1741 /* Hook for sysfs read of QSFP */
1742 int qsfp_dump(struct hfi1_pportdata
*ppd
, char *buf
, int len
);
1744 int hfi1_pcie_init(struct pci_dev
*, const struct pci_device_id
*);
1745 void hfi1_pcie_cleanup(struct pci_dev
*);
1746 int hfi1_pcie_ddinit(struct hfi1_devdata
*, struct pci_dev
*,
1747 const struct pci_device_id
*);
1748 void hfi1_pcie_ddcleanup(struct hfi1_devdata
*);
1749 void hfi1_pcie_flr(struct hfi1_devdata
*);
1750 int pcie_speeds(struct hfi1_devdata
*);
1751 void request_msix(struct hfi1_devdata
*, u32
*, struct hfi1_msix_entry
*);
1752 void hfi1_enable_intx(struct pci_dev
*);
1753 void restore_pci_variables(struct hfi1_devdata
*dd
);
1754 int do_pcie_gen3_transition(struct hfi1_devdata
*dd
);
1755 int parse_platform_config(struct hfi1_devdata
*dd
);
1756 int get_platform_config_field(struct hfi1_devdata
*dd
,
1757 enum platform_config_table_type_encoding
1758 table_type
, int table_index
, int field_index
,
1759 u32
*data
, u32 len
);
1761 const char *get_unit_name(int unit
);
1762 const char *get_card_name(struct rvt_dev_info
*rdi
);
1763 struct pci_dev
*get_pci_dev(struct rvt_dev_info
*rdi
);
1766 * Flush write combining store buffers (if present) and perform a write
1769 static inline void flush_wc(void)
1771 asm volatile("sfence" : : : "memory");
1774 void handle_eflags(struct hfi1_packet
*packet
);
1775 int process_receive_ib(struct hfi1_packet
*packet
);
1776 int process_receive_bypass(struct hfi1_packet
*packet
);
1777 int process_receive_error(struct hfi1_packet
*packet
);
1778 int kdeth_process_expected(struct hfi1_packet
*packet
);
1779 int kdeth_process_eager(struct hfi1_packet
*packet
);
1780 int process_receive_invalid(struct hfi1_packet
*packet
);
1782 extern rhf_rcv_function_ptr snoop_rhf_rcv_functions
[8];
1784 void update_sge(struct rvt_sge_state
*ss
, u32 length
);
1786 /* global module parameter variables */
1787 extern unsigned int hfi1_max_mtu
;
1788 extern unsigned int hfi1_cu
;
1789 extern unsigned int user_credit_return_threshold
;
1790 extern int num_user_contexts
;
1791 extern unsigned n_krcvqs
;
1792 extern uint krcvqs
[];
1793 extern int krcvqsset
;
1794 extern uint kdeth_qp
;
1795 extern uint loopback
;
1796 extern uint quick_linkup
;
1797 extern uint rcv_intr_timeout
;
1798 extern uint rcv_intr_count
;
1799 extern uint rcv_intr_dynamic
;
1800 extern ushort link_crc_mask
;
1802 extern struct mutex hfi1_mutex
;
1804 /* Number of seconds before our card status check... */
1805 #define STATUS_TIMEOUT 60
1807 #define DRIVER_NAME "hfi1"
1808 #define HFI1_USER_MINOR_BASE 0
1809 #define HFI1_TRACE_MINOR 127
1810 #define HFI1_DIAGPKT_MINOR 128
1811 #define HFI1_DIAG_MINOR_BASE 129
1812 #define HFI1_SNOOP_CAPTURE_BASE 200
1813 #define HFI1_NMINORS 255
1815 #define PCI_VENDOR_ID_INTEL 0x8086
1816 #define PCI_DEVICE_ID_INTEL0 0x24f0
1817 #define PCI_DEVICE_ID_INTEL1 0x24f1
1819 #define HFI1_PKT_USER_SC_INTEGRITY \
1820 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
1821 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
1822 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
1823 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
1825 #define HFI1_PKT_KERNEL_SC_INTEGRITY \
1826 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
1828 static inline u64
hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata
*dd
,
1831 u64 base_sc_integrity
=
1832 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1833 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
1834 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1835 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1836 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
1837 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
1838 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
1839 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
1840 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
1841 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
1842 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
1843 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1844 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
1845 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
1846 | SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
1847 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
1848 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK
;
1850 if (ctxt_type
== SC_USER
)
1851 base_sc_integrity
|= HFI1_PKT_USER_SC_INTEGRITY
;
1853 base_sc_integrity
|= HFI1_PKT_KERNEL_SC_INTEGRITY
;
1856 /* turn off send-side job key checks - A0 */
1857 return base_sc_integrity
&
1858 ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
;
1859 return base_sc_integrity
;
1862 static inline u64
hfi1_pkt_base_sdma_integrity(struct hfi1_devdata
*dd
)
1864 u64 base_sdma_integrity
=
1865 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1866 | SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
1867 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1868 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1869 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
1870 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
1871 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
1872 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
1873 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
1874 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
1875 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1876 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
1877 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
1878 | SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
1879 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
1880 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK
;
1883 /* turn off send-side job key checks - A0 */
1884 return base_sdma_integrity
&
1885 ~SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
;
1886 return base_sdma_integrity
;
1890 * hfi1_early_err is used (only!) to print early errors before devdata is
1891 * allocated, or when dd->pcidev may not be valid, and at the tail end of
1892 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is
1893 * the same as dd_dev_err, but is used when the message really needs
1894 * the IB port# to be definitive as to what's happening..
1896 #define hfi1_early_err(dev, fmt, ...) \
1897 dev_err(dev, fmt, ##__VA_ARGS__)
1899 #define hfi1_early_info(dev, fmt, ...) \
1900 dev_info(dev, fmt, ##__VA_ARGS__)
1902 #define dd_dev_emerg(dd, fmt, ...) \
1903 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
1904 get_unit_name((dd)->unit), ##__VA_ARGS__)
1905 #define dd_dev_err(dd, fmt, ...) \
1906 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1907 get_unit_name((dd)->unit), ##__VA_ARGS__)
1908 #define dd_dev_warn(dd, fmt, ...) \
1909 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
1910 get_unit_name((dd)->unit), ##__VA_ARGS__)
1912 #define dd_dev_warn_ratelimited(dd, fmt, ...) \
1913 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
1914 get_unit_name((dd)->unit), ##__VA_ARGS__)
1916 #define dd_dev_info(dd, fmt, ...) \
1917 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
1918 get_unit_name((dd)->unit), ##__VA_ARGS__)
1920 #define dd_dev_dbg(dd, fmt, ...) \
1921 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
1922 get_unit_name((dd)->unit), ##__VA_ARGS__)
1924 #define hfi1_dev_porterr(dd, port, fmt, ...) \
1925 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
1926 get_unit_name((dd)->unit), (port), ##__VA_ARGS__)
1929 * this is used for formatting hw error messages...
1931 struct hfi1_hwerror_msgs
{
1938 void hfi1_format_hwerrors(u64 hwerrs
,
1939 const struct hfi1_hwerror_msgs
*hwerrmsgs
,
1940 size_t nhwerrmsgs
, char *msg
, size_t lmsg
);
1942 #define USER_OPCODE_CHECK_VAL 0xC0
1943 #define USER_OPCODE_CHECK_MASK 0xC0
1944 #define OPCODE_CHECK_VAL_DISABLED 0x0
1945 #define OPCODE_CHECK_MASK_DISABLED 0x0
1947 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata
*dd
)
1949 struct hfi1_pportdata
*ppd
;
1952 dd
->z_int_counter
= get_all_cpu_total(dd
->int_counter
);
1953 dd
->z_rcv_limit
= get_all_cpu_total(dd
->rcv_limit
);
1954 dd
->z_send_schedule
= get_all_cpu_total(dd
->send_schedule
);
1956 ppd
= (struct hfi1_pportdata
*)(dd
+ 1);
1957 for (i
= 0; i
< dd
->num_pports
; i
++, ppd
++) {
1958 ppd
->ibport_data
.rvp
.z_rc_acks
=
1959 get_all_cpu_total(ppd
->ibport_data
.rvp
.rc_acks
);
1960 ppd
->ibport_data
.rvp
.z_rc_qacks
=
1961 get_all_cpu_total(ppd
->ibport_data
.rvp
.rc_qacks
);
1965 /* Control LED state */
1966 static inline void setextled(struct hfi1_devdata
*dd
, u32 on
)
1969 write_csr(dd
, DCC_CFG_LED_CNTRL
, 0x1F);
1971 write_csr(dd
, DCC_CFG_LED_CNTRL
, 0x10);
1974 /* return the i2c resource given the target */
1975 static inline u32
i2c_target(u32 target
)
1977 return target
? CR_I2C2
: CR_I2C1
;
1980 /* return the i2c chain chip resource that this HFI uses for QSFP */
1981 static inline u32
qsfp_resource(struct hfi1_devdata
*dd
)
1983 return i2c_target(dd
->hfi1_id
);
1986 int hfi1_tempsense_rd(struct hfi1_devdata
*dd
, struct hfi1_temp
*temp
);
1988 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
1989 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
1991 #define packettype_name(etype) { RHF_RCV_TYPE_##etype, #etype }
1992 #define show_packettype(etype) \
1993 __print_symbolic(etype, \
1994 packettype_name(EXPECTED), \
1995 packettype_name(EAGER), \
1996 packettype_name(IB), \
1997 packettype_name(ERROR), \
1998 packettype_name(BYPASS))
2000 #define ib_opcode_name(opcode) { IB_OPCODE_##opcode, #opcode }
2001 #define show_ib_opcode(opcode) \
2002 __print_symbolic(opcode, \
2003 ib_opcode_name(RC_SEND_FIRST), \
2004 ib_opcode_name(RC_SEND_MIDDLE), \
2005 ib_opcode_name(RC_SEND_LAST), \
2006 ib_opcode_name(RC_SEND_LAST_WITH_IMMEDIATE), \
2007 ib_opcode_name(RC_SEND_ONLY), \
2008 ib_opcode_name(RC_SEND_ONLY_WITH_IMMEDIATE), \
2009 ib_opcode_name(RC_RDMA_WRITE_FIRST), \
2010 ib_opcode_name(RC_RDMA_WRITE_MIDDLE), \
2011 ib_opcode_name(RC_RDMA_WRITE_LAST), \
2012 ib_opcode_name(RC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \
2013 ib_opcode_name(RC_RDMA_WRITE_ONLY), \
2014 ib_opcode_name(RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \
2015 ib_opcode_name(RC_RDMA_READ_REQUEST), \
2016 ib_opcode_name(RC_RDMA_READ_RESPONSE_FIRST), \
2017 ib_opcode_name(RC_RDMA_READ_RESPONSE_MIDDLE), \
2018 ib_opcode_name(RC_RDMA_READ_RESPONSE_LAST), \
2019 ib_opcode_name(RC_RDMA_READ_RESPONSE_ONLY), \
2020 ib_opcode_name(RC_ACKNOWLEDGE), \
2021 ib_opcode_name(RC_ATOMIC_ACKNOWLEDGE), \
2022 ib_opcode_name(RC_COMPARE_SWAP), \
2023 ib_opcode_name(RC_FETCH_ADD), \
2024 ib_opcode_name(UC_SEND_FIRST), \
2025 ib_opcode_name(UC_SEND_MIDDLE), \
2026 ib_opcode_name(UC_SEND_LAST), \
2027 ib_opcode_name(UC_SEND_LAST_WITH_IMMEDIATE), \
2028 ib_opcode_name(UC_SEND_ONLY), \
2029 ib_opcode_name(UC_SEND_ONLY_WITH_IMMEDIATE), \
2030 ib_opcode_name(UC_RDMA_WRITE_FIRST), \
2031 ib_opcode_name(UC_RDMA_WRITE_MIDDLE), \
2032 ib_opcode_name(UC_RDMA_WRITE_LAST), \
2033 ib_opcode_name(UC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \
2034 ib_opcode_name(UC_RDMA_WRITE_ONLY), \
2035 ib_opcode_name(UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \
2036 ib_opcode_name(UD_SEND_ONLY), \
2037 ib_opcode_name(UD_SEND_ONLY_WITH_IMMEDIATE), \
2038 ib_opcode_name(CNP))
2039 #endif /* _HFI1_KERNEL_H */