2 * Copyright(c) 2015, 2016 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 #include <linux/pci.h>
49 #include <linux/netdevice.h>
50 #include <linux/vmalloc.h>
51 #include <linux/delay.h>
52 #include <linux/idr.h>
53 #include <linux/module.h>
54 #include <linux/printk.h>
55 #include <linux/hrtimer.h>
56 #include <rdma/rdma_vt.h>
70 #define pr_fmt(fmt) DRIVER_NAME ": " fmt
73 * min buffers we want to have per context, after driver
75 #define HFI1_MIN_USER_CTXT_BUFCNT 7
77 #define HFI1_MIN_HDRQ_EGRBUF_CNT 2
78 #define HFI1_MAX_HDRQ_EGRBUF_CNT 16352
79 #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */
80 #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */
83 * Number of user receive contexts we are configured to use (to allow for more
84 * pio buffers per ctxt, etc.) Zero means use one user context per CPU.
86 int num_user_contexts
= -1;
87 module_param_named(num_user_contexts
, num_user_contexts
, uint
, S_IRUGO
);
89 num_user_contexts
, "Set max number of user contexts to use");
91 uint krcvqs
[RXE_NUM_DATA_VL
];
93 module_param_array(krcvqs
, uint
, &krcvqsset
, S_IRUGO
);
94 MODULE_PARM_DESC(krcvqs
, "Array of the number of non-control kernel receive queues by VL");
96 /* computed based on above array */
97 unsigned long n_krcvqs
;
99 static unsigned hfi1_rcvarr_split
= 25;
100 module_param_named(rcvarr_split
, hfi1_rcvarr_split
, uint
, S_IRUGO
);
101 MODULE_PARM_DESC(rcvarr_split
, "Percent of context's RcvArray entries used for Eager buffers");
103 static uint eager_buffer_size
= (2 << 20); /* 2MB */
104 module_param(eager_buffer_size
, uint
, S_IRUGO
);
105 MODULE_PARM_DESC(eager_buffer_size
, "Size of the eager buffers, default: 2MB");
107 static uint rcvhdrcnt
= 2048; /* 2x the max eager buffer count */
108 module_param_named(rcvhdrcnt
, rcvhdrcnt
, uint
, S_IRUGO
);
109 MODULE_PARM_DESC(rcvhdrcnt
, "Receive header queue count (default 2048)");
111 static uint hfi1_hdrq_entsize
= 32;
112 module_param_named(hdrq_entsize
, hfi1_hdrq_entsize
, uint
, S_IRUGO
);
113 MODULE_PARM_DESC(hdrq_entsize
, "Size of header queue entries: 2 - 8B, 16 - 64B (default), 32 - 128B");
115 unsigned int user_credit_return_threshold
= 33; /* default is 33% */
116 module_param(user_credit_return_threshold
, uint
, S_IRUGO
);
117 MODULE_PARM_DESC(user_credit_return_threshold
, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)");
119 static inline u64
encode_rcv_header_entry_size(u16
);
121 static struct idr hfi1_unit_table
;
122 u32 hfi1_cpulist_count
;
123 unsigned long *hfi1_cpulist
;
126 * Common code for creating the receive context array.
128 int hfi1_create_ctxts(struct hfi1_devdata
*dd
)
133 /* Control context has to be always 0 */
134 BUILD_BUG_ON(HFI1_CTRL_CTXT
!= 0);
136 dd
->rcd
= kzalloc_node(dd
->num_rcv_contexts
* sizeof(*dd
->rcd
),
137 GFP_KERNEL
, dd
->node
);
141 /* create one or more kernel contexts */
142 for (i
= 0; i
< dd
->first_user_ctxt
; ++i
) {
143 struct hfi1_pportdata
*ppd
;
144 struct hfi1_ctxtdata
*rcd
;
146 ppd
= dd
->pport
+ (i
% dd
->num_pports
);
147 rcd
= hfi1_create_ctxtdata(ppd
, i
, dd
->node
);
150 "Unable to allocate kernel receive context, failing\n");
154 * Set up the kernel context flags here and now because they
155 * use default values for all receive side memories. User
156 * contexts will be handled as they are created.
158 rcd
->flags
= HFI1_CAP_KGET(MULTI_PKT_EGR
) |
159 HFI1_CAP_KGET(NODROP_RHQ_FULL
) |
160 HFI1_CAP_KGET(NODROP_EGR_FULL
) |
161 HFI1_CAP_KGET(DMA_RTAIL
);
163 /* Control context must use DMA_RTAIL */
164 if (rcd
->ctxt
== HFI1_CTRL_CTXT
)
165 rcd
->flags
|= HFI1_CAP_DMA_RTAIL
;
168 rcd
->sc
= sc_alloc(dd
, SC_ACK
, rcd
->rcvhdrqentsize
, dd
->node
);
171 "Unable to allocate kernel send context, failing\n");
172 dd
->rcd
[rcd
->ctxt
] = NULL
;
173 hfi1_free_ctxtdata(dd
, rcd
);
177 ret
= hfi1_init_ctxt(rcd
->sc
);
180 "Failed to setup kernel receive context, failing\n");
182 dd
->rcd
[rcd
->ctxt
] = NULL
;
183 hfi1_free_ctxtdata(dd
, rcd
);
190 * Initialize aspm, to be done after gen3 transition and setting up
191 * contexts and before enabling interrupts
205 * Common code for user and kernel context setup.
207 struct hfi1_ctxtdata
*hfi1_create_ctxtdata(struct hfi1_pportdata
*ppd
, u32 ctxt
,
210 struct hfi1_devdata
*dd
= ppd
->dd
;
211 struct hfi1_ctxtdata
*rcd
;
212 unsigned kctxt_ngroups
= 0;
215 if (dd
->rcv_entries
.nctxt_extra
>
216 dd
->num_rcv_contexts
- dd
->first_user_ctxt
)
217 kctxt_ngroups
= (dd
->rcv_entries
.nctxt_extra
-
218 (dd
->num_rcv_contexts
- dd
->first_user_ctxt
));
219 rcd
= kzalloc(sizeof(*rcd
), GFP_KERNEL
);
221 u32 rcvtids
, max_entries
;
223 hfi1_cdbg(PROC
, "setting up context %u\n", ctxt
);
225 INIT_LIST_HEAD(&rcd
->qp_wait_list
);
232 rcd
->rcv_array_groups
= dd
->rcv_entries
.ngroups
;
234 mutex_init(&rcd
->exp_lock
);
237 * Calculate the context's RcvArray entry starting point.
238 * We do this here because we have to take into account all
239 * the RcvArray entries that previous context would have
240 * taken and we have to account for any extra groups
241 * assigned to the kernel or user contexts.
243 if (ctxt
< dd
->first_user_ctxt
) {
244 if (ctxt
< kctxt_ngroups
) {
245 base
= ctxt
* (dd
->rcv_entries
.ngroups
+ 1);
246 rcd
->rcv_array_groups
++;
248 base
= kctxt_ngroups
+
249 (ctxt
* dd
->rcv_entries
.ngroups
);
251 u16 ct
= ctxt
- dd
->first_user_ctxt
;
253 base
= ((dd
->n_krcv_queues
* dd
->rcv_entries
.ngroups
) +
255 if (ct
< dd
->rcv_entries
.nctxt_extra
) {
256 base
+= ct
* (dd
->rcv_entries
.ngroups
+ 1);
257 rcd
->rcv_array_groups
++;
259 base
+= dd
->rcv_entries
.nctxt_extra
+
260 (ct
* dd
->rcv_entries
.ngroups
);
262 rcd
->eager_base
= base
* dd
->rcv_entries
.group_size
;
264 /* Validate and initialize Rcv Hdr Q variables */
265 if (rcvhdrcnt
% HDRQ_INCREMENT
) {
267 "ctxt%u: header queue count %d must be divisible by %lu\n",
268 rcd
->ctxt
, rcvhdrcnt
, HDRQ_INCREMENT
);
271 rcd
->rcvhdrq_cnt
= rcvhdrcnt
;
272 rcd
->rcvhdrqentsize
= hfi1_hdrq_entsize
;
274 * Simple Eager buffer allocation: we have already pre-allocated
275 * the number of RcvArray entry groups. Each ctxtdata structure
276 * holds the number of groups for that context.
278 * To follow CSR requirements and maintain cacheline alignment,
279 * make sure all sizes and bases are multiples of group_size.
281 * The expected entry count is what is left after assigning
284 max_entries
= rcd
->rcv_array_groups
*
285 dd
->rcv_entries
.group_size
;
286 rcvtids
= ((max_entries
* hfi1_rcvarr_split
) / 100);
287 rcd
->egrbufs
.count
= round_down(rcvtids
,
288 dd
->rcv_entries
.group_size
);
289 if (rcd
->egrbufs
.count
> MAX_EAGER_ENTRIES
) {
290 dd_dev_err(dd
, "ctxt%u: requested too many RcvArray entries.\n",
292 rcd
->egrbufs
.count
= MAX_EAGER_ENTRIES
;
295 "ctxt%u: max Eager buffer RcvArray entries: %u\n",
296 rcd
->ctxt
, rcd
->egrbufs
.count
);
299 * Allocate array that will hold the eager buffer accounting
301 * This will allocate the maximum possible buffer count based
302 * on the value of the RcvArray split parameter.
303 * The resulting value will be rounded down to the closest
304 * multiple of dd->rcv_entries.group_size.
306 rcd
->egrbufs
.buffers
= kcalloc(rcd
->egrbufs
.count
,
307 sizeof(*rcd
->egrbufs
.buffers
),
309 if (!rcd
->egrbufs
.buffers
)
311 rcd
->egrbufs
.rcvtids
= kcalloc(rcd
->egrbufs
.count
,
312 sizeof(*rcd
->egrbufs
.rcvtids
),
314 if (!rcd
->egrbufs
.rcvtids
)
316 rcd
->egrbufs
.size
= eager_buffer_size
;
318 * The size of the buffers programmed into the RcvArray
319 * entries needs to be big enough to handle the highest
322 if (rcd
->egrbufs
.size
< hfi1_max_mtu
) {
323 rcd
->egrbufs
.size
= __roundup_pow_of_two(hfi1_max_mtu
);
325 "ctxt%u: eager bufs size too small. Adjusting to %zu\n",
326 rcd
->ctxt
, rcd
->egrbufs
.size
);
328 rcd
->egrbufs
.rcvtid_size
= HFI1_MAX_EAGER_BUFFER_SIZE
;
330 if (ctxt
< dd
->first_user_ctxt
) { /* N/A for PSM contexts */
331 rcd
->opstats
= kzalloc(sizeof(*rcd
->opstats
),
339 kfree(rcd
->egrbufs
.rcvtids
);
340 kfree(rcd
->egrbufs
.buffers
);
346 * Convert a receive header entry size that to the encoding used in the CSR.
348 * Return a zero if the given size is invalid.
350 static inline u64
encode_rcv_header_entry_size(u16 size
)
352 /* there are only 3 valid receive header entry sizes */
359 return 0; /* invalid */
363 * Select the largest ccti value over all SLs to determine the intra-
364 * packet gap for the link.
366 * called with cca_timer_lock held (to protect access to cca_timer
367 * array), and rcu_read_lock() (to protect access to cc_state).
369 void set_link_ipg(struct hfi1_pportdata
*ppd
)
371 struct hfi1_devdata
*dd
= ppd
->dd
;
372 struct cc_state
*cc_state
;
374 u16 cce
, ccti_limit
, max_ccti
= 0;
377 u32 current_egress_rate
; /* Mbits /sec */
380 * max_pkt_time is the maximum packet egress time in units
381 * of the fabric clock period 1/(805 MHz).
384 cc_state
= get_cc_state(ppd
);
388 * This should _never_ happen - rcu_read_lock() is held,
389 * and set_link_ipg() should not be called if cc_state
394 for (i
= 0; i
< OPA_MAX_SLS
; i
++) {
395 u16 ccti
= ppd
->cca_timer
[i
].ccti
;
401 ccti_limit
= cc_state
->cct
.ccti_limit
;
402 if (max_ccti
> ccti_limit
)
403 max_ccti
= ccti_limit
;
405 cce
= cc_state
->cct
.entries
[max_ccti
].entry
;
406 shift
= (cce
& 0xc000) >> 14;
407 mult
= (cce
& 0x3fff);
409 current_egress_rate
= active_egress_rate(ppd
);
411 max_pkt_time
= egress_cycles(ppd
->ibmaxlen
, current_egress_rate
);
413 src
= (max_pkt_time
>> shift
) * mult
;
415 src
&= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK
;
416 src
<<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT
;
418 write_csr(dd
, SEND_STATIC_RATE_CONTROL
, src
);
421 static enum hrtimer_restart
cca_timer_fn(struct hrtimer
*t
)
423 struct cca_timer
*cca_timer
;
424 struct hfi1_pportdata
*ppd
;
426 u16 ccti_timer
, ccti_min
;
427 struct cc_state
*cc_state
;
429 enum hrtimer_restart ret
= HRTIMER_NORESTART
;
431 cca_timer
= container_of(t
, struct cca_timer
, hrtimer
);
432 ppd
= cca_timer
->ppd
;
437 cc_state
= get_cc_state(ppd
);
441 return HRTIMER_NORESTART
;
445 * 1) decrement ccti for SL
446 * 2) calculate IPG for link (set_link_ipg())
447 * 3) restart timer, unless ccti is at min value
450 ccti_min
= cc_state
->cong_setting
.entries
[sl
].ccti_min
;
451 ccti_timer
= cc_state
->cong_setting
.entries
[sl
].ccti_timer
;
453 spin_lock_irqsave(&ppd
->cca_timer_lock
, flags
);
455 if (cca_timer
->ccti
> ccti_min
) {
460 if (cca_timer
->ccti
> ccti_min
) {
461 unsigned long nsec
= 1024 * ccti_timer
;
462 /* ccti_timer is in units of 1.024 usec */
463 hrtimer_forward_now(t
, ns_to_ktime(nsec
));
464 ret
= HRTIMER_RESTART
;
467 spin_unlock_irqrestore(&ppd
->cca_timer_lock
, flags
);
473 * Common code for initializing the physical port structure.
475 void hfi1_init_pportdata(struct pci_dev
*pdev
, struct hfi1_pportdata
*ppd
,
476 struct hfi1_devdata
*dd
, u8 hw_pidx
, u8 port
)
479 uint default_pkey_idx
;
480 struct cc_state
*cc_state
;
483 ppd
->hw_pidx
= hw_pidx
;
484 ppd
->port
= port
; /* IB port number, not index */
486 default_pkey_idx
= 1;
488 ppd
->pkeys
[default_pkey_idx
] = DEFAULT_P_KEY
;
490 hfi1_early_err(&pdev
->dev
,
491 "Faking data partition 0x8001 in idx %u\n",
493 ppd
->pkeys
[!default_pkey_idx
] = 0x8001;
496 INIT_WORK(&ppd
->link_vc_work
, handle_verify_cap
);
497 INIT_WORK(&ppd
->link_up_work
, handle_link_up
);
498 INIT_WORK(&ppd
->link_down_work
, handle_link_down
);
499 INIT_WORK(&ppd
->freeze_work
, handle_freeze
);
500 INIT_WORK(&ppd
->link_downgrade_work
, handle_link_downgrade
);
501 INIT_WORK(&ppd
->sma_message_work
, handle_sma_message
);
502 INIT_WORK(&ppd
->link_bounce_work
, handle_link_bounce
);
503 INIT_DELAYED_WORK(&ppd
->start_link_work
, handle_start_link
);
504 INIT_WORK(&ppd
->linkstate_active_work
, receive_interrupt_work
);
505 INIT_WORK(&ppd
->qsfp_info
.qsfp_work
, qsfp_event
);
507 mutex_init(&ppd
->hls_lock
);
508 spin_lock_init(&ppd
->sdma_alllock
);
509 spin_lock_init(&ppd
->qsfp_info
.qsfp_lock
);
511 ppd
->qsfp_info
.ppd
= ppd
;
512 ppd
->sm_trap_qp
= 0x0;
517 spin_lock_init(&ppd
->cca_timer_lock
);
519 for (i
= 0; i
< OPA_MAX_SLS
; i
++) {
520 hrtimer_init(&ppd
->cca_timer
[i
].hrtimer
, CLOCK_MONOTONIC
,
522 ppd
->cca_timer
[i
].ppd
= ppd
;
523 ppd
->cca_timer
[i
].sl
= i
;
524 ppd
->cca_timer
[i
].ccti
= 0;
525 ppd
->cca_timer
[i
].hrtimer
.function
= cca_timer_fn
;
528 ppd
->cc_max_table_entries
= IB_CC_TABLE_CAP_DEFAULT
;
530 spin_lock_init(&ppd
->cc_state_lock
);
531 spin_lock_init(&ppd
->cc_log_lock
);
532 cc_state
= kzalloc(sizeof(*cc_state
), GFP_KERNEL
);
533 RCU_INIT_POINTER(ppd
->cc_state
, cc_state
);
540 hfi1_early_err(&pdev
->dev
,
541 "Congestion Control Agent disabled for port %d\n", port
);
545 * Do initialization for device that is only needed on
546 * first detect, not on resets.
548 static int loadtime_init(struct hfi1_devdata
*dd
)
554 * init_after_reset - re-initialize after a reset
555 * @dd: the hfi1_ib device
557 * sanity check at least some of the values after reset, and
558 * ensure no receive or transmit (explicitly, in case reset
561 static int init_after_reset(struct hfi1_devdata
*dd
)
566 * Ensure chip does no sends or receives, tail updates, or
567 * pioavail updates while we re-initialize. This is mostly
568 * for the driver data structures, not chip registers.
570 for (i
= 0; i
< dd
->num_rcv_contexts
; i
++)
571 hfi1_rcvctrl(dd
, HFI1_RCVCTRL_CTXT_DIS
|
572 HFI1_RCVCTRL_INTRAVAIL_DIS
|
573 HFI1_RCVCTRL_TAILUPD_DIS
, i
);
574 pio_send_control(dd
, PSC_GLOBAL_DISABLE
);
575 for (i
= 0; i
< dd
->num_send_contexts
; i
++)
576 sc_disable(dd
->send_contexts
[i
].sc
);
581 static void enable_chip(struct hfi1_devdata
*dd
)
586 /* enable PIO send */
587 pio_send_control(dd
, PSC_GLOBAL_ENABLE
);
590 * Enable kernel ctxts' receive and receive interrupt.
591 * Other ctxts done as user opens and initializes them.
593 for (i
= 0; i
< dd
->first_user_ctxt
; ++i
) {
594 rcvmask
= HFI1_RCVCTRL_CTXT_ENB
| HFI1_RCVCTRL_INTRAVAIL_ENB
;
595 rcvmask
|= HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, DMA_RTAIL
) ?
596 HFI1_RCVCTRL_TAILUPD_ENB
: HFI1_RCVCTRL_TAILUPD_DIS
;
597 if (!HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, MULTI_PKT_EGR
))
598 rcvmask
|= HFI1_RCVCTRL_ONE_PKT_EGR_ENB
;
599 if (HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, NODROP_RHQ_FULL
))
600 rcvmask
|= HFI1_RCVCTRL_NO_RHQ_DROP_ENB
;
601 if (HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, NODROP_EGR_FULL
))
602 rcvmask
|= HFI1_RCVCTRL_NO_EGR_DROP_ENB
;
603 hfi1_rcvctrl(dd
, rcvmask
, i
);
604 sc_enable(dd
->rcd
[i
]->sc
);
609 * create_workqueues - create per port workqueues
610 * @dd: the hfi1_ib device
612 static int create_workqueues(struct hfi1_devdata
*dd
)
615 struct hfi1_pportdata
*ppd
;
617 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
618 ppd
= dd
->pport
+ pidx
;
623 WQ_SYSFS
| WQ_HIGHPRI
| WQ_CPU_INTENSIVE
,
632 pr_err("alloc_workqueue failed for port %d\n", pidx
+ 1);
633 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
634 ppd
= dd
->pport
+ pidx
;
636 destroy_workqueue(ppd
->hfi1_wq
);
644 * hfi1_init - do the actual initialization sequence on the chip
645 * @dd: the hfi1_ib device
646 * @reinit: re-initializing, so don't allocate new memory
648 * Do the actual initialization sequence on the chip. This is done
649 * both from the init routine called from the PCI infrastructure, and
650 * when we reset the chip, or detect that it was reset internally,
651 * or it's administratively re-enabled.
653 * Memory allocation here and in called routines is only done in
654 * the first case (reinit == 0). We have to be careful, because even
655 * without memory allocation, we need to re-write all the chip registers
656 * TIDs, etc. after the reset or enable has completed.
658 int hfi1_init(struct hfi1_devdata
*dd
, int reinit
)
660 int ret
= 0, pidx
, lastfail
= 0;
662 struct hfi1_ctxtdata
*rcd
;
663 struct hfi1_pportdata
*ppd
;
665 /* Set up recv low level handlers */
666 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_EXPECTED
] =
667 kdeth_process_expected
;
668 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_EAGER
] =
670 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_IB
] = process_receive_ib
;
671 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_ERROR
] =
672 process_receive_error
;
673 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_BYPASS
] =
674 process_receive_bypass
;
675 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_INVALID5
] =
676 process_receive_invalid
;
677 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_INVALID6
] =
678 process_receive_invalid
;
679 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_INVALID7
] =
680 process_receive_invalid
;
681 dd
->rhf_rcv_function_map
= dd
->normal_rhf_rcv_functions
;
683 /* Set up send low level handlers */
684 dd
->process_pio_send
= hfi1_verbs_send_pio
;
685 dd
->process_dma_send
= hfi1_verbs_send_dma
;
686 dd
->pio_inline_send
= pio_copy
;
689 atomic_set(&dd
->drop_packet
, DROP_PACKET_ON
);
692 atomic_set(&dd
->drop_packet
, DROP_PACKET_OFF
);
696 /* make sure the link is not "up" */
697 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
698 ppd
= dd
->pport
+ pidx
;
703 ret
= init_after_reset(dd
);
705 ret
= loadtime_init(dd
);
709 /* allocate dummy tail memory for all receive contexts */
710 dd
->rcvhdrtail_dummy_kvaddr
= dma_zalloc_coherent(
711 &dd
->pcidev
->dev
, sizeof(u64
),
712 &dd
->rcvhdrtail_dummy_physaddr
,
715 if (!dd
->rcvhdrtail_dummy_kvaddr
) {
716 dd_dev_err(dd
, "cannot allocate dummy tail memory\n");
721 /* dd->rcd can be NULL if early initialization failed */
722 for (i
= 0; dd
->rcd
&& i
< dd
->first_user_ctxt
; ++i
) {
724 * Set up the (kernel) rcvhdr queue and egr TIDs. If doing
725 * re-init, the simplest way to handle this is to free
726 * existing, and re-allocate.
727 * Need to re-create rest of ctxt 0 ctxtdata as well.
733 rcd
->do_interrupt
= &handle_receive_interrupt
;
735 lastfail
= hfi1_create_rcvhdrq(dd
, rcd
);
737 lastfail
= hfi1_setup_eagerbufs(rcd
);
740 "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
745 /* Allocate enough memory for user event notification. */
746 len
= PAGE_ALIGN(dd
->chip_rcv_contexts
* HFI1_MAX_SHARED_CTXTS
*
747 sizeof(*dd
->events
));
748 dd
->events
= vmalloc_user(len
);
750 dd_dev_err(dd
, "Failed to allocate user events page\n");
752 * Allocate a page for device and port status.
753 * Page will be shared amongst all user processes.
755 dd
->status
= vmalloc_user(PAGE_SIZE
);
757 dd_dev_err(dd
, "Failed to allocate dev status page\n");
759 dd
->freezelen
= PAGE_SIZE
- (sizeof(*dd
->status
) -
760 sizeof(dd
->status
->freezemsg
));
761 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
762 ppd
= dd
->pport
+ pidx
;
764 /* Currently, we only have one port */
765 ppd
->statusp
= &dd
->status
->port
;
770 /* enable chip even if we have an error, so we can debug cause */
775 * Set status even if port serdes is not initialized
776 * so that diags will work.
779 dd
->status
->dev
|= HFI1_STATUS_CHIP_PRESENT
|
782 /* enable all interrupts from the chip */
783 set_intr_state(dd
, 1);
785 /* chip is OK for user apps; mark it as initialized */
786 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
787 ppd
= dd
->pport
+ pidx
;
790 * start the serdes - must be after interrupts are
791 * enabled so we are notified when the link goes up
793 lastfail
= bringup_serdes(ppd
);
796 "Failed to bring up port %u\n",
800 * Set status even if port serdes is not initialized
801 * so that diags will work.
804 *ppd
->statusp
|= HFI1_STATUS_CHIP_PRESENT
|
806 if (!ppd
->link_speed_enabled
)
811 /* if ret is non-zero, we probably should do some cleanup here... */
815 static inline struct hfi1_devdata
*__hfi1_lookup(int unit
)
817 return idr_find(&hfi1_unit_table
, unit
);
820 struct hfi1_devdata
*hfi1_lookup(int unit
)
822 struct hfi1_devdata
*dd
;
825 spin_lock_irqsave(&hfi1_devs_lock
, flags
);
826 dd
= __hfi1_lookup(unit
);
827 spin_unlock_irqrestore(&hfi1_devs_lock
, flags
);
833 * Stop the timers during unit shutdown, or after an error late
836 static void stop_timers(struct hfi1_devdata
*dd
)
838 struct hfi1_pportdata
*ppd
;
841 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
842 ppd
= dd
->pport
+ pidx
;
843 if (ppd
->led_override_timer
.data
) {
844 del_timer_sync(&ppd
->led_override_timer
);
845 atomic_set(&ppd
->led_override_timer_active
, 0);
851 * shutdown_device - shut down a device
852 * @dd: the hfi1_ib device
854 * This is called to make the device quiet when we are about to
855 * unload the driver, and also when the device is administratively
856 * disabled. It does not free any data structures.
857 * Everything it does has to be setup again by hfi1_init(dd, 1)
859 static void shutdown_device(struct hfi1_devdata
*dd
)
861 struct hfi1_pportdata
*ppd
;
865 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
866 ppd
= dd
->pport
+ pidx
;
870 *ppd
->statusp
&= ~(HFI1_STATUS_IB_CONF
|
871 HFI1_STATUS_IB_READY
);
873 dd
->flags
&= ~HFI1_INITTED
;
875 /* mask interrupts, but not errors */
876 set_intr_state(dd
, 0);
878 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
879 ppd
= dd
->pport
+ pidx
;
880 for (i
= 0; i
< dd
->num_rcv_contexts
; i
++)
881 hfi1_rcvctrl(dd
, HFI1_RCVCTRL_TAILUPD_DIS
|
882 HFI1_RCVCTRL_CTXT_DIS
|
883 HFI1_RCVCTRL_INTRAVAIL_DIS
|
884 HFI1_RCVCTRL_PKEY_DIS
|
885 HFI1_RCVCTRL_ONE_PKT_EGR_DIS
, i
);
887 * Gracefully stop all sends allowing any in progress to
890 for (i
= 0; i
< dd
->num_send_contexts
; i
++)
891 sc_flush(dd
->send_contexts
[i
].sc
);
895 * Enough for anything that's going to trickle out to have actually
900 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
901 ppd
= dd
->pport
+ pidx
;
903 /* disable all contexts */
904 for (i
= 0; i
< dd
->num_send_contexts
; i
++)
905 sc_disable(dd
->send_contexts
[i
].sc
);
906 /* disable the send device */
907 pio_send_control(dd
, PSC_GLOBAL_DISABLE
);
909 shutdown_led_override(ppd
);
912 * Clear SerdesEnable.
913 * We can't count on interrupts since we are stopping.
915 hfi1_quiet_serdes(ppd
);
918 destroy_workqueue(ppd
->hfi1_wq
);
926 * hfi1_free_ctxtdata - free a context's allocated data
927 * @dd: the hfi1_ib device
928 * @rcd: the ctxtdata structure
930 * free up any allocated data for a context
931 * This should not touch anything that would affect a simultaneous
932 * re-allocation of context data, because it is called after hfi1_mutex
933 * is released (and can be called from reinit as well).
934 * It should never change any chip state, or global driver state.
936 void hfi1_free_ctxtdata(struct hfi1_devdata
*dd
, struct hfi1_ctxtdata
*rcd
)
944 dma_free_coherent(&dd
->pcidev
->dev
, rcd
->rcvhdrq_size
,
945 rcd
->rcvhdrq
, rcd
->rcvhdrq_phys
);
947 if (rcd
->rcvhdrtail_kvaddr
) {
948 dma_free_coherent(&dd
->pcidev
->dev
, PAGE_SIZE
,
949 (void *)rcd
->rcvhdrtail_kvaddr
,
950 rcd
->rcvhdrqtailaddr_phys
);
951 rcd
->rcvhdrtail_kvaddr
= NULL
;
955 /* all the RcvArray entries should have been cleared by now */
956 kfree(rcd
->egrbufs
.rcvtids
);
958 for (e
= 0; e
< rcd
->egrbufs
.alloced
; e
++) {
959 if (rcd
->egrbufs
.buffers
[e
].phys
)
960 dma_free_coherent(&dd
->pcidev
->dev
,
961 rcd
->egrbufs
.buffers
[e
].len
,
962 rcd
->egrbufs
.buffers
[e
].addr
,
963 rcd
->egrbufs
.buffers
[e
].phys
);
965 kfree(rcd
->egrbufs
.buffers
);
968 vfree(rcd
->user_event_mask
);
969 vfree(rcd
->subctxt_uregbase
);
970 vfree(rcd
->subctxt_rcvegrbuf
);
971 vfree(rcd
->subctxt_rcvhdr_base
);
977 * Release our hold on the shared asic data. If we are the last one,
978 * return the structure to be finalized outside the lock. Must be
979 * holding hfi1_devs_lock.
981 static struct hfi1_asic_data
*release_asic_data(struct hfi1_devdata
*dd
)
983 struct hfi1_asic_data
*ad
;
988 dd
->asic_data
->dds
[dd
->hfi1_id
] = NULL
;
989 other
= dd
->hfi1_id
? 0 : 1;
991 dd
->asic_data
= NULL
;
992 /* return NULL if the other dd still has a link */
993 return ad
->dds
[other
] ? NULL
: ad
;
996 static void finalize_asic_data(struct hfi1_devdata
*dd
,
997 struct hfi1_asic_data
*ad
)
999 clean_up_i2c(dd
, ad
);
1003 static void __hfi1_free_devdata(struct kobject
*kobj
)
1005 struct hfi1_devdata
*dd
=
1006 container_of(kobj
, struct hfi1_devdata
, kobj
);
1007 struct hfi1_asic_data
*ad
;
1008 unsigned long flags
;
1010 spin_lock_irqsave(&hfi1_devs_lock
, flags
);
1011 idr_remove(&hfi1_unit_table
, dd
->unit
);
1012 list_del(&dd
->list
);
1013 ad
= release_asic_data(dd
);
1014 spin_unlock_irqrestore(&hfi1_devs_lock
, flags
);
1016 finalize_asic_data(dd
, ad
);
1017 free_platform_config(dd
);
1018 rcu_barrier(); /* wait for rcu callbacks to complete */
1019 free_percpu(dd
->int_counter
);
1020 free_percpu(dd
->rcv_limit
);
1021 free_percpu(dd
->send_schedule
);
1022 rvt_dealloc_device(&dd
->verbs_dev
.rdi
);
1025 static struct kobj_type hfi1_devdata_type
= {
1026 .release
= __hfi1_free_devdata
,
1029 void hfi1_free_devdata(struct hfi1_devdata
*dd
)
1031 kobject_put(&dd
->kobj
);
1035 * Allocate our primary per-unit data structure. Must be done via verbs
1036 * allocator, because the verbs cleanup process both does cleanup and
1037 * free of the data structure.
1038 * "extra" is for chip-specific data.
1040 * Use the idr mechanism to get a unit number for this unit.
1042 struct hfi1_devdata
*hfi1_alloc_devdata(struct pci_dev
*pdev
, size_t extra
)
1044 unsigned long flags
;
1045 struct hfi1_devdata
*dd
;
1048 /* extra is * number of ports */
1049 nports
= extra
/ sizeof(struct hfi1_pportdata
);
1051 dd
= (struct hfi1_devdata
*)rvt_alloc_device(sizeof(*dd
) + extra
,
1054 return ERR_PTR(-ENOMEM
);
1055 dd
->num_pports
= nports
;
1056 dd
->pport
= (struct hfi1_pportdata
*)(dd
+ 1);
1058 INIT_LIST_HEAD(&dd
->list
);
1059 idr_preload(GFP_KERNEL
);
1060 spin_lock_irqsave(&hfi1_devs_lock
, flags
);
1062 ret
= idr_alloc(&hfi1_unit_table
, dd
, 0, 0, GFP_NOWAIT
);
1065 list_add(&dd
->list
, &hfi1_dev_list
);
1068 spin_unlock_irqrestore(&hfi1_devs_lock
, flags
);
1072 hfi1_early_err(&pdev
->dev
,
1073 "Could not allocate unit ID: error %d\n", -ret
);
1077 * Initialize all locks for the device. This needs to be as early as
1078 * possible so locks are usable.
1080 spin_lock_init(&dd
->sc_lock
);
1081 spin_lock_init(&dd
->sendctrl_lock
);
1082 spin_lock_init(&dd
->rcvctrl_lock
);
1083 spin_lock_init(&dd
->uctxt_lock
);
1084 spin_lock_init(&dd
->hfi1_diag_trans_lock
);
1085 spin_lock_init(&dd
->sc_init_lock
);
1086 spin_lock_init(&dd
->dc8051_lock
);
1087 spin_lock_init(&dd
->dc8051_memlock
);
1088 seqlock_init(&dd
->sc2vl_lock
);
1089 spin_lock_init(&dd
->sde_map_lock
);
1090 spin_lock_init(&dd
->pio_map_lock
);
1091 init_waitqueue_head(&dd
->event_queue
);
1093 dd
->int_counter
= alloc_percpu(u64
);
1094 if (!dd
->int_counter
) {
1096 hfi1_early_err(&pdev
->dev
,
1097 "Could not allocate per-cpu int_counter\n");
1101 dd
->rcv_limit
= alloc_percpu(u64
);
1102 if (!dd
->rcv_limit
) {
1104 hfi1_early_err(&pdev
->dev
,
1105 "Could not allocate per-cpu rcv_limit\n");
1109 dd
->send_schedule
= alloc_percpu(u64
);
1110 if (!dd
->send_schedule
) {
1112 hfi1_early_err(&pdev
->dev
,
1113 "Could not allocate per-cpu int_counter\n");
1117 if (!hfi1_cpulist_count
) {
1118 u32 count
= num_online_cpus();
1120 hfi1_cpulist
= kcalloc(BITS_TO_LONGS(count
), sizeof(long),
1123 hfi1_cpulist_count
= count
;
1127 "Could not alloc cpulist info, cpu affinity might be wrong\n");
1129 kobject_init(&dd
->kobj
, &hfi1_devdata_type
);
1133 if (!list_empty(&dd
->list
))
1134 list_del_init(&dd
->list
);
1135 rvt_dealloc_device(&dd
->verbs_dev
.rdi
);
1136 return ERR_PTR(ret
);
1140 * Called from freeze mode handlers, and from PCI error
1141 * reporting code. Should be paranoid about state of
1142 * system and data structures.
1144 void hfi1_disable_after_error(struct hfi1_devdata
*dd
)
1146 if (dd
->flags
& HFI1_INITTED
) {
1149 dd
->flags
&= ~HFI1_INITTED
;
1151 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
1152 struct hfi1_pportdata
*ppd
;
1154 ppd
= dd
->pport
+ pidx
;
1155 if (dd
->flags
& HFI1_PRESENT
)
1156 set_link_state(ppd
, HLS_DN_DISABLE
);
1159 *ppd
->statusp
&= ~HFI1_STATUS_IB_READY
;
1164 * Mark as having had an error for driver, and also
1165 * for /sys and status word mapped to user programs.
1166 * This marks unit as not usable, until reset.
1169 dd
->status
->dev
|= HFI1_STATUS_HWERROR
;
1172 static void remove_one(struct pci_dev
*);
1173 static int init_one(struct pci_dev
*, const struct pci_device_id
*);
1175 #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: "
1176 #define PFX DRIVER_NAME ": "
1178 const struct pci_device_id hfi1_pci_tbl
[] = {
1179 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL0
) },
1180 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL1
) },
1184 MODULE_DEVICE_TABLE(pci
, hfi1_pci_tbl
);
1186 static struct pci_driver hfi1_pci_driver
= {
1187 .name
= DRIVER_NAME
,
1189 .remove
= remove_one
,
1190 .id_table
= hfi1_pci_tbl
,
1191 .err_handler
= &hfi1_pci_err_handler
,
1194 static void __init
compute_krcvqs(void)
1198 for (i
= 0; i
< krcvqsset
; i
++)
1199 n_krcvqs
+= krcvqs
[i
];
1203 * Do all the generic driver unit- and chip-independent memory
1204 * allocation and initialization.
1206 static int __init
hfi1_mod_init(void)
1214 ret
= node_affinity_init();
1218 /* validate max MTU before any devices start */
1219 if (!valid_opa_max_mtu(hfi1_max_mtu
)) {
1220 pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n",
1221 hfi1_max_mtu
, HFI1_DEFAULT_MAX_MTU
);
1222 hfi1_max_mtu
= HFI1_DEFAULT_MAX_MTU
;
1224 /* valid CUs run from 1-128 in powers of 2 */
1225 if (hfi1_cu
> 128 || !is_power_of_2(hfi1_cu
))
1227 /* valid credit return threshold is 0-100, variable is unsigned */
1228 if (user_credit_return_threshold
> 100)
1229 user_credit_return_threshold
= 100;
1233 * sanitize receive interrupt count, time must wait until after
1234 * the hardware type is known
1236 if (rcv_intr_count
> RCV_HDR_HEAD_COUNTER_MASK
)
1237 rcv_intr_count
= RCV_HDR_HEAD_COUNTER_MASK
;
1238 /* reject invalid combinations */
1239 if (rcv_intr_count
== 0 && rcv_intr_timeout
== 0) {
1240 pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n");
1243 if (rcv_intr_count
> 1 && rcv_intr_timeout
== 0) {
1245 * Avoid indefinite packet delivery by requiring a timeout
1248 pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n");
1249 rcv_intr_timeout
= 1;
1251 if (rcv_intr_dynamic
&& !(rcv_intr_count
> 1 && rcv_intr_timeout
> 0)) {
1253 * The dynamic algorithm expects a non-zero timeout
1256 pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n");
1257 rcv_intr_dynamic
= 0;
1260 /* sanitize link CRC options */
1261 link_crc_mask
&= SUPPORTED_CRCS
;
1264 * These must be called before the driver is registered with
1265 * the PCI subsystem.
1267 idr_init(&hfi1_unit_table
);
1270 ret
= hfi1_wss_init();
1273 ret
= pci_register_driver(&hfi1_pci_driver
);
1275 pr_err("Unable to register driver: error %d\n", -ret
);
1278 goto bail
; /* all OK */
1284 idr_destroy(&hfi1_unit_table
);
1290 module_init(hfi1_mod_init
);
1293 * Do the non-unit driver cleanup, memory free, etc. at unload.
1295 static void __exit
hfi1_mod_cleanup(void)
1297 pci_unregister_driver(&hfi1_pci_driver
);
1298 node_affinity_destroy();
1301 hfi1_cpulist_count
= 0;
1302 kfree(hfi1_cpulist
);
1304 idr_destroy(&hfi1_unit_table
);
1305 dispose_firmware(); /* asymmetric with obtain_firmware() */
1309 module_exit(hfi1_mod_cleanup
);
1311 /* this can only be called after a successful initialization */
1312 static void cleanup_device_data(struct hfi1_devdata
*dd
)
1316 struct hfi1_ctxtdata
**tmp
;
1317 unsigned long flags
;
1319 /* users can't do anything more with chip */
1320 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
1321 struct hfi1_pportdata
*ppd
= &dd
->pport
[pidx
];
1322 struct cc_state
*cc_state
;
1326 *ppd
->statusp
&= ~HFI1_STATUS_CHIP_PRESENT
;
1328 for (i
= 0; i
< OPA_MAX_SLS
; i
++)
1329 hrtimer_cancel(&ppd
->cca_timer
[i
].hrtimer
);
1331 spin_lock(&ppd
->cc_state_lock
);
1332 cc_state
= get_cc_state_protected(ppd
);
1333 RCU_INIT_POINTER(ppd
->cc_state
, NULL
);
1334 spin_unlock(&ppd
->cc_state_lock
);
1337 kfree_rcu(cc_state
, rcu
);
1340 free_credit_return(dd
);
1343 * Free any resources still in use (usually just kernel contexts)
1344 * at unload; we do for ctxtcnt, because that's what we allocate.
1345 * We acquire lock to be really paranoid that rcd isn't being
1346 * accessed from some interrupt-related code (that should not happen,
1347 * but best to be sure).
1349 spin_lock_irqsave(&dd
->uctxt_lock
, flags
);
1352 spin_unlock_irqrestore(&dd
->uctxt_lock
, flags
);
1354 if (dd
->rcvhdrtail_dummy_kvaddr
) {
1355 dma_free_coherent(&dd
->pcidev
->dev
, sizeof(u64
),
1356 (void *)dd
->rcvhdrtail_dummy_kvaddr
,
1357 dd
->rcvhdrtail_dummy_physaddr
);
1358 dd
->rcvhdrtail_dummy_kvaddr
= NULL
;
1361 for (ctxt
= 0; tmp
&& ctxt
< dd
->num_rcv_contexts
; ctxt
++) {
1362 struct hfi1_ctxtdata
*rcd
= tmp
[ctxt
];
1364 tmp
[ctxt
] = NULL
; /* debugging paranoia */
1366 hfi1_clear_tids(rcd
);
1367 hfi1_free_ctxtdata(dd
, rcd
);
1372 /* must follow rcv context free - need to remove rcv's hooks */
1373 for (ctxt
= 0; ctxt
< dd
->num_send_contexts
; ctxt
++)
1374 sc_free(dd
->send_contexts
[ctxt
].sc
);
1375 dd
->num_send_contexts
= 0;
1376 kfree(dd
->send_contexts
);
1377 dd
->send_contexts
= NULL
;
1378 kfree(dd
->hw_to_sw
);
1379 dd
->hw_to_sw
= NULL
;
1380 kfree(dd
->boardname
);
1386 * Clean up on unit shutdown, or error during unit load after
1387 * successful initialization.
1389 static void postinit_cleanup(struct hfi1_devdata
*dd
)
1391 hfi1_start_cleanup(dd
);
1393 hfi1_pcie_ddcleanup(dd
);
1394 hfi1_pcie_cleanup(dd
->pcidev
);
1396 cleanup_device_data(dd
);
1398 hfi1_free_devdata(dd
);
1401 static int init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1403 int ret
= 0, j
, pidx
, initfail
;
1404 struct hfi1_devdata
*dd
= ERR_PTR(-EINVAL
);
1405 struct hfi1_pportdata
*ppd
;
1407 /* First, lock the non-writable module parameters */
1410 /* Validate some global module parameters */
1411 if (rcvhdrcnt
<= HFI1_MIN_HDRQ_EGRBUF_CNT
) {
1412 hfi1_early_err(&pdev
->dev
, "Header queue count too small\n");
1416 if (rcvhdrcnt
> HFI1_MAX_HDRQ_EGRBUF_CNT
) {
1417 hfi1_early_err(&pdev
->dev
,
1418 "Receive header queue count cannot be greater than %u\n",
1419 HFI1_MAX_HDRQ_EGRBUF_CNT
);
1423 /* use the encoding function as a sanitization check */
1424 if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize
)) {
1425 hfi1_early_err(&pdev
->dev
, "Invalid HdrQ Entry size %u\n",
1431 /* The receive eager buffer size must be set before the receive
1432 * contexts are created.
1434 * Set the eager buffer size. Validate that it falls in a range
1435 * allowed by the hardware - all powers of 2 between the min and
1436 * max. The maximum valid MTU is within the eager buffer range
1437 * so we do not need to cap the max_mtu by an eager buffer size
1440 if (eager_buffer_size
) {
1441 if (!is_power_of_2(eager_buffer_size
))
1443 roundup_pow_of_two(eager_buffer_size
);
1445 clamp_val(eager_buffer_size
,
1446 MIN_EAGER_BUFFER
* 8,
1447 MAX_EAGER_BUFFER_TOTAL
);
1448 hfi1_early_info(&pdev
->dev
, "Eager buffer size %u\n",
1451 hfi1_early_err(&pdev
->dev
, "Invalid Eager buffer size of 0\n");
1456 /* restrict value of hfi1_rcvarr_split */
1457 hfi1_rcvarr_split
= clamp_val(hfi1_rcvarr_split
, 0, 100);
1459 ret
= hfi1_pcie_init(pdev
, ent
);
1464 * Do device-specific initialization, function table setup, dd
1467 switch (ent
->device
) {
1468 case PCI_DEVICE_ID_INTEL0
:
1469 case PCI_DEVICE_ID_INTEL1
:
1470 dd
= hfi1_init_dd(pdev
, ent
);
1473 hfi1_early_err(&pdev
->dev
,
1474 "Failing on unknown Intel deviceid 0x%x\n",
1482 goto clean_bail
; /* error already printed */
1484 ret
= create_workqueues(dd
);
1488 /* do the generic initialization */
1489 initfail
= hfi1_init(dd
, 0);
1491 ret
= hfi1_register_ib_device(dd
);
1494 * Now ready for use. this should be cleared whenever we
1495 * detect a reset, or initiate one. If earlier failure,
1496 * we still create devices, so diags, etc. can be used
1497 * to determine cause of problem.
1499 if (!initfail
&& !ret
) {
1500 dd
->flags
|= HFI1_INITTED
;
1501 /* create debufs files after init and ib register */
1502 hfi1_dbg_ibdev_init(&dd
->verbs_dev
);
1505 j
= hfi1_device_create(dd
);
1507 dd_dev_err(dd
, "Failed to create /dev devices: %d\n", -j
);
1509 if (initfail
|| ret
) {
1511 flush_workqueue(ib_wq
);
1512 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
1513 hfi1_quiet_serdes(dd
->pport
+ pidx
);
1514 ppd
= dd
->pport
+ pidx
;
1516 destroy_workqueue(ppd
->hfi1_wq
);
1517 ppd
->hfi1_wq
= NULL
;
1521 hfi1_device_remove(dd
);
1523 hfi1_unregister_ib_device(dd
);
1524 postinit_cleanup(dd
);
1527 goto bail
; /* everything already cleaned */
1535 hfi1_pcie_cleanup(pdev
);
1540 static void remove_one(struct pci_dev
*pdev
)
1542 struct hfi1_devdata
*dd
= pci_get_drvdata(pdev
);
1544 /* close debugfs files before ib unregister */
1545 hfi1_dbg_ibdev_exit(&dd
->verbs_dev
);
1546 /* unregister from IB core */
1547 hfi1_unregister_ib_device(dd
);
1550 * Disable the IB link, disable interrupts on the device,
1551 * clear dma engines, etc.
1553 shutdown_device(dd
);
1557 /* wait until all of our (qsfp) queue_work() calls complete */
1558 flush_workqueue(ib_wq
);
1560 hfi1_device_remove(dd
);
1562 postinit_cleanup(dd
);
1566 * hfi1_create_rcvhdrq - create a receive header queue
1567 * @dd: the hfi1_ib device
1568 * @rcd: the context data
1570 * This must be contiguous memory (from an i/o perspective), and must be
1571 * DMA'able (which means for some systems, it will go through an IOMMU,
1572 * or be forced into a low address range).
1574 int hfi1_create_rcvhdrq(struct hfi1_devdata
*dd
, struct hfi1_ctxtdata
*rcd
)
1579 if (!rcd
->rcvhdrq
) {
1580 dma_addr_t phys_hdrqtail
;
1584 * rcvhdrqentsize is in DWs, so we have to convert to bytes
1587 amt
= PAGE_ALIGN(rcd
->rcvhdrq_cnt
* rcd
->rcvhdrqentsize
*
1590 gfp_flags
= (rcd
->ctxt
>= dd
->first_user_ctxt
) ?
1591 GFP_USER
: GFP_KERNEL
;
1592 rcd
->rcvhdrq
= dma_zalloc_coherent(
1593 &dd
->pcidev
->dev
, amt
, &rcd
->rcvhdrq_phys
,
1594 gfp_flags
| __GFP_COMP
);
1596 if (!rcd
->rcvhdrq
) {
1598 "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1603 if (HFI1_CAP_KGET_MASK(rcd
->flags
, DMA_RTAIL
)) {
1604 rcd
->rcvhdrtail_kvaddr
= dma_zalloc_coherent(
1605 &dd
->pcidev
->dev
, PAGE_SIZE
, &phys_hdrqtail
,
1607 if (!rcd
->rcvhdrtail_kvaddr
)
1609 rcd
->rcvhdrqtailaddr_phys
= phys_hdrqtail
;
1612 rcd
->rcvhdrq_size
= amt
;
1615 * These values are per-context:
1620 reg
= ((u64
)(rcd
->rcvhdrq_cnt
>> HDRQ_SIZE_SHIFT
)
1621 & RCV_HDR_CNT_CNT_MASK
)
1622 << RCV_HDR_CNT_CNT_SHIFT
;
1623 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_HDR_CNT
, reg
);
1624 reg
= (encode_rcv_header_entry_size(rcd
->rcvhdrqentsize
)
1625 & RCV_HDR_ENT_SIZE_ENT_SIZE_MASK
)
1626 << RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT
;
1627 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_HDR_ENT_SIZE
, reg
);
1628 reg
= (dd
->rcvhdrsize
& RCV_HDR_SIZE_HDR_SIZE_MASK
)
1629 << RCV_HDR_SIZE_HDR_SIZE_SHIFT
;
1630 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_HDR_SIZE
, reg
);
1633 * Program dummy tail address for every receive context
1634 * before enabling any receive context
1636 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_HDR_TAIL_ADDR
,
1637 dd
->rcvhdrtail_dummy_physaddr
);
1643 "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1645 vfree(rcd
->user_event_mask
);
1646 rcd
->user_event_mask
= NULL
;
1647 dma_free_coherent(&dd
->pcidev
->dev
, amt
, rcd
->rcvhdrq
,
1649 rcd
->rcvhdrq
= NULL
;
1655 * allocate eager buffers, both kernel and user contexts.
1656 * @rcd: the context we are setting up.
1658 * Allocate the eager TID buffers and program them into hip.
1659 * They are no longer completely contiguous, we do multiple allocation
1660 * calls. Otherwise we get the OOM code involved, by asking for too
1661 * much per call, with disastrous results on some kernels.
1663 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata
*rcd
)
1665 struct hfi1_devdata
*dd
= rcd
->dd
;
1666 u32 max_entries
, egrtop
, alloced_bytes
= 0, idx
= 0;
1670 u16 round_mtu
= roundup_pow_of_two(hfi1_max_mtu
);
1673 * GFP_USER, but without GFP_FS, so buffer cache can be
1674 * coalesced (we hope); otherwise, even at order 4,
1675 * heavy filesystem activity makes these fail, and we can
1676 * use compound pages.
1678 gfp_flags
= __GFP_RECLAIM
| __GFP_IO
| __GFP_COMP
;
1681 * The minimum size of the eager buffers is a groups of MTU-sized
1683 * The global eager_buffer_size parameter is checked against the
1684 * theoretical lower limit of the value. Here, we check against the
1687 if (rcd
->egrbufs
.size
< (round_mtu
* dd
->rcv_entries
.group_size
))
1688 rcd
->egrbufs
.size
= round_mtu
* dd
->rcv_entries
.group_size
;
1690 * If using one-pkt-per-egr-buffer, lower the eager buffer
1691 * size to the max MTU (page-aligned).
1693 if (!HFI1_CAP_KGET_MASK(rcd
->flags
, MULTI_PKT_EGR
))
1694 rcd
->egrbufs
.rcvtid_size
= round_mtu
;
1697 * Eager buffers sizes of 1MB or less require smaller TID sizes
1698 * to satisfy the "multiple of 8 RcvArray entries" requirement.
1700 if (rcd
->egrbufs
.size
<= (1 << 20))
1701 rcd
->egrbufs
.rcvtid_size
= max((unsigned long)round_mtu
,
1702 rounddown_pow_of_two(rcd
->egrbufs
.size
/ 8));
1704 while (alloced_bytes
< rcd
->egrbufs
.size
&&
1705 rcd
->egrbufs
.alloced
< rcd
->egrbufs
.count
) {
1706 rcd
->egrbufs
.buffers
[idx
].addr
=
1707 dma_zalloc_coherent(&dd
->pcidev
->dev
,
1708 rcd
->egrbufs
.rcvtid_size
,
1709 &rcd
->egrbufs
.buffers
[idx
].phys
,
1711 if (rcd
->egrbufs
.buffers
[idx
].addr
) {
1712 rcd
->egrbufs
.buffers
[idx
].len
=
1713 rcd
->egrbufs
.rcvtid_size
;
1714 rcd
->egrbufs
.rcvtids
[rcd
->egrbufs
.alloced
].addr
=
1715 rcd
->egrbufs
.buffers
[idx
].addr
;
1716 rcd
->egrbufs
.rcvtids
[rcd
->egrbufs
.alloced
].phys
=
1717 rcd
->egrbufs
.buffers
[idx
].phys
;
1718 rcd
->egrbufs
.alloced
++;
1719 alloced_bytes
+= rcd
->egrbufs
.rcvtid_size
;
1726 * Fail the eager buffer allocation if:
1727 * - we are already using the lowest acceptable size
1728 * - we are using one-pkt-per-egr-buffer (this implies
1729 * that we are accepting only one size)
1731 if (rcd
->egrbufs
.rcvtid_size
== round_mtu
||
1732 !HFI1_CAP_KGET_MASK(rcd
->flags
, MULTI_PKT_EGR
)) {
1733 dd_dev_err(dd
, "ctxt%u: Failed to allocate eager buffers\n",
1735 goto bail_rcvegrbuf_phys
;
1738 new_size
= rcd
->egrbufs
.rcvtid_size
/ 2;
1741 * If the first attempt to allocate memory failed, don't
1742 * fail everything but continue with the next lower
1746 rcd
->egrbufs
.rcvtid_size
= new_size
;
1751 * Re-partition already allocated buffers to a smaller
1754 rcd
->egrbufs
.alloced
= 0;
1755 for (i
= 0, j
= 0, offset
= 0; j
< idx
; i
++) {
1756 if (i
>= rcd
->egrbufs
.count
)
1758 rcd
->egrbufs
.rcvtids
[i
].phys
=
1759 rcd
->egrbufs
.buffers
[j
].phys
+ offset
;
1760 rcd
->egrbufs
.rcvtids
[i
].addr
=
1761 rcd
->egrbufs
.buffers
[j
].addr
+ offset
;
1762 rcd
->egrbufs
.alloced
++;
1763 if ((rcd
->egrbufs
.buffers
[j
].phys
+ offset
+
1765 (rcd
->egrbufs
.buffers
[j
].phys
+
1766 rcd
->egrbufs
.buffers
[j
].len
)) {
1773 rcd
->egrbufs
.rcvtid_size
= new_size
;
1776 rcd
->egrbufs
.numbufs
= idx
;
1777 rcd
->egrbufs
.size
= alloced_bytes
;
1780 "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %zuKB\n",
1781 rcd
->ctxt
, rcd
->egrbufs
.alloced
,
1782 rcd
->egrbufs
.rcvtid_size
/ 1024, rcd
->egrbufs
.size
/ 1024);
1785 * Set the contexts rcv array head update threshold to the closest
1786 * power of 2 (so we can use a mask instead of modulo) below half
1787 * the allocated entries.
1789 rcd
->egrbufs
.threshold
=
1790 rounddown_pow_of_two(rcd
->egrbufs
.alloced
/ 2);
1792 * Compute the expected RcvArray entry base. This is done after
1793 * allocating the eager buffers in order to maximize the
1794 * expected RcvArray entries for the context.
1796 max_entries
= rcd
->rcv_array_groups
* dd
->rcv_entries
.group_size
;
1797 egrtop
= roundup(rcd
->egrbufs
.alloced
, dd
->rcv_entries
.group_size
);
1798 rcd
->expected_count
= max_entries
- egrtop
;
1799 if (rcd
->expected_count
> MAX_TID_PAIR_ENTRIES
* 2)
1800 rcd
->expected_count
= MAX_TID_PAIR_ENTRIES
* 2;
1802 rcd
->expected_base
= rcd
->eager_base
+ egrtop
;
1803 hfi1_cdbg(PROC
, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n",
1804 rcd
->ctxt
, rcd
->egrbufs
.alloced
, rcd
->expected_count
,
1805 rcd
->eager_base
, rcd
->expected_base
);
1807 if (!hfi1_rcvbuf_validate(rcd
->egrbufs
.rcvtid_size
, PT_EAGER
, &order
)) {
1809 "ctxt%u: current Eager buffer size is invalid %u\n",
1810 rcd
->ctxt
, rcd
->egrbufs
.rcvtid_size
);
1815 for (idx
= 0; idx
< rcd
->egrbufs
.alloced
; idx
++) {
1816 hfi1_put_tid(dd
, rcd
->eager_base
+ idx
, PT_EAGER
,
1817 rcd
->egrbufs
.rcvtids
[idx
].phys
, order
);
1822 bail_rcvegrbuf_phys
:
1823 for (idx
= 0; idx
< rcd
->egrbufs
.alloced
&&
1824 rcd
->egrbufs
.buffers
[idx
].addr
;
1826 dma_free_coherent(&dd
->pcidev
->dev
,
1827 rcd
->egrbufs
.buffers
[idx
].len
,
1828 rcd
->egrbufs
.buffers
[idx
].addr
,
1829 rcd
->egrbufs
.buffers
[idx
].phys
);
1830 rcd
->egrbufs
.buffers
[idx
].addr
= NULL
;
1831 rcd
->egrbufs
.buffers
[idx
].phys
= 0;
1832 rcd
->egrbufs
.buffers
[idx
].len
= 0;