drivers/infiniband/hw/i40iw/i40iw_hw.c

   1 /*******************************************************************************
   2 *
   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenFabrics.org BSD license below:
  10 *
  11 *   Redistribution and use in source and binary forms, with or
  12 *   without modification, are permitted provided that the following
  13 *   conditions are met:
  14 *
  15 *    - Redistributions of source code must retain the above
  16 *       copyright notice, this list of conditions and the following
  17 *       disclaimer.
  18 *
  19 *    - Redistributions in binary form must reproduce the above
  20 *       copyright notice, this list of conditions and the following
  21 *       disclaimer in the documentation and/or other materials
  22 *       provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 *
  33 *******************************************************************************/
  34
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/etherdevice.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/if_vlan.h>
  42
  43 #include "i40iw.h"
  44
  45 /**
  46  * i40iw_initialize_hw_resources - initialize hw resource during open
  47  * @iwdev: iwarp device
  48  */
  49 u32 i40iw_initialize_hw_resources(struct i40iw_device *iwdev)
  50 {
  51         unsigned long num_pds;
  52         u32 resources_size;
  53         u32 max_mr;
  54         u32 max_qp;
  55         u32 max_cq;
  56         u32 arp_table_size;
  57         u32 mrdrvbits;
  58         void *resource_ptr;
  59
  60         max_qp = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt;
  61         max_cq = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt;
  62         max_mr = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt;
  63         arp_table_size = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_ARP].cnt;
  64         iwdev->max_cqe = 0xFFFFF;
  65         num_pds = max_qp * 4;
  66         resources_size = sizeof(struct i40iw_arp_entry) * arp_table_size;
  67         resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_qp);
  68         resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_mr);
  69         resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_cq);
  70         resources_size += sizeof(unsigned long) * BITS_TO_LONGS(num_pds);
  71         resources_size += sizeof(unsigned long) * BITS_TO_LONGS(arp_table_size);
  72         resources_size += sizeof(struct i40iw_qp **) * max_qp;
  73         iwdev->mem_resources = kzalloc(resources_size, GFP_KERNEL);
  74
  75         if (!iwdev->mem_resources)
  76                 return -ENOMEM;
  77
  78         iwdev->max_qp = max_qp;
  79         iwdev->max_mr = max_mr;
  80         iwdev->max_cq = max_cq;
  81         iwdev->max_pd = num_pds;
  82         iwdev->arp_table_size = arp_table_size;
  83         iwdev->arp_table = (struct i40iw_arp_entry *)iwdev->mem_resources;
  84         resource_ptr = iwdev->mem_resources + (sizeof(struct i40iw_arp_entry) * arp_table_size);
  85
  86         iwdev->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY |
  87             IB_DEVICE_MEM_WINDOW | IB_DEVICE_MEM_MGT_EXTENSIONS;
  88
  89         iwdev->allocated_qps = resource_ptr;
  90         iwdev->allocated_cqs = &iwdev->allocated_qps[BITS_TO_LONGS(max_qp)];
  91         iwdev->allocated_mrs = &iwdev->allocated_cqs[BITS_TO_LONGS(max_cq)];
  92         iwdev->allocated_pds = &iwdev->allocated_mrs[BITS_TO_LONGS(max_mr)];
  93         iwdev->allocated_arps = &iwdev->allocated_pds[BITS_TO_LONGS(num_pds)];
  94         iwdev->qp_table = (struct i40iw_qp **)(&iwdev->allocated_arps[BITS_TO_LONGS(arp_table_size)]);
  95         set_bit(0, iwdev->allocated_mrs);
  96         set_bit(0, iwdev->allocated_qps);
  97         set_bit(0, iwdev->allocated_cqs);
  98         set_bit(0, iwdev->allocated_pds);
  99         set_bit(0, iwdev->allocated_arps);
 100
 101         /* Following for ILQ/IEQ */
 102         set_bit(1, iwdev->allocated_qps);
 103         set_bit(1, iwdev->allocated_cqs);
 104         set_bit(1, iwdev->allocated_pds);
 105         set_bit(2, iwdev->allocated_cqs);
 106         set_bit(2, iwdev->allocated_pds);
 107
 108         spin_lock_init(&iwdev->resource_lock);
 109         spin_lock_init(&iwdev->qptable_lock);
 110         mrdrvbits = 24 - get_count_order(iwdev->max_mr);
 111         iwdev->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits));
 112         return 0;
 113 }
 114
 115 /**
 116  * i40iw_cqp_ce_handler - handle cqp completions
 117  * @iwdev: iwarp device
 118  * @arm: flag to arm after completions
 119  * @cq: cq for cqp completions
 120  */
 121 static void i40iw_cqp_ce_handler(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq, bool arm)
 122 {
 123         struct i40iw_cqp_request *cqp_request;
 124         struct i40iw_sc_dev *dev = &iwdev->sc_dev;
 125         u32 cqe_count = 0;
 126         struct i40iw_ccq_cqe_info info;
 127         int ret;
 128
 129         do {
 130                 memset(&info, 0, sizeof(info));
 131                 ret = dev->ccq_ops->ccq_get_cqe_info(cq, &info);
 132                 if (ret)
 133                         break;
 134                 cqp_request = (struct i40iw_cqp_request *)(unsigned long)info.scratch;
 135                 if (info.error)
 136                         i40iw_pr_err("opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n",
 137                                      info.op_code, info.maj_err_code, info.min_err_code);
 138                 if (cqp_request) {
 139                         cqp_request->compl_info.maj_err_code = info.maj_err_code;
 140                         cqp_request->compl_info.min_err_code = info.min_err_code;
 141                         cqp_request->compl_info.op_ret_val = info.op_ret_val;
 142                         cqp_request->compl_info.error = info.error;
 143
 144                         if (cqp_request->waiting) {
 145                                 cqp_request->request_done = true;
 146                                 wake_up(&cqp_request->waitq);
 147                                 i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
 148                         } else {
 149                                 if (cqp_request->callback_fcn)
 150                                         cqp_request->callback_fcn(cqp_request, 1);
 151                                 i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
 152                         }
 153                 }
 154
 155                 cqe_count++;
 156         } while (1);
 157
 158         if (arm && cqe_count) {
 159                 i40iw_process_bh(dev);
 160                 dev->ccq_ops->ccq_arm(cq);
 161         }
 162 }
 163
 164 /**
 165  * i40iw_iwarp_ce_handler - handle iwarp completions
 166  * @iwdev: iwarp device
 167  * @iwcp: iwarp cq receiving event
 168  */
 169 static void i40iw_iwarp_ce_handler(struct i40iw_device *iwdev,
 170                                    struct i40iw_sc_cq *iwcq)
 171 {
 172         struct i40iw_cq *i40iwcq = iwcq->back_cq;
 173
 174         if (i40iwcq->ibcq.comp_handler)
 175                 i40iwcq->ibcq.comp_handler(&i40iwcq->ibcq,
 176                                            i40iwcq->ibcq.cq_context);
 177 }
 178
 179 /**
 180  * i40iw_puda_ce_handler - handle puda completion events
 181  * @iwdev: iwarp device
 182  * @cq: puda completion q for event
 183  */
 184 static void i40iw_puda_ce_handler(struct i40iw_device *iwdev,
 185                                   struct i40iw_sc_cq *cq)
 186 {
 187         struct i40iw_sc_dev *dev = (struct i40iw_sc_dev *)&iwdev->sc_dev;
 188         enum i40iw_status_code status;
 189         u32 compl_error;
 190
 191         do {
 192                 status = i40iw_puda_poll_completion(dev, cq, &compl_error);
 193                 if (status == I40IW_ERR_QUEUE_EMPTY)
 194                         break;
 195                 if (status) {
 196                         i40iw_pr_err("puda  status = %d\n", status);
 197                         break;
 198                 }
 199                 if (compl_error) {
 200                         i40iw_pr_err("puda compl_err  =0x%x\n", compl_error);
 201                         break;
 202                 }
 203         } while (1);
 204
 205         dev->ccq_ops->ccq_arm(cq);
 206 }
 207
 208 /**
 209  * i40iw_process_ceq - handle ceq for completions
 210  * @iwdev: iwarp device
 211  * @ceq: ceq having cq for completion
 212  */
 213 void i40iw_process_ceq(struct i40iw_device *iwdev, struct i40iw_ceq *ceq)
 214 {
 215         struct i40iw_sc_dev *dev = &iwdev->sc_dev;
 216         struct i40iw_sc_ceq *sc_ceq;
 217         struct i40iw_sc_cq *cq;
 218         bool arm = true;
 219
 220         sc_ceq = &ceq->sc_ceq;
 221         do {
 222                 cq = dev->ceq_ops->process_ceq(dev, sc_ceq);
 223                 if (!cq)
 224                         break;
 225
 226                 if (cq->cq_type == I40IW_CQ_TYPE_CQP)
 227                         i40iw_cqp_ce_handler(iwdev, cq, arm);
 228                 else if (cq->cq_type == I40IW_CQ_TYPE_IWARP)
 229                         i40iw_iwarp_ce_handler(iwdev, cq);
 230                 else if ((cq->cq_type == I40IW_CQ_TYPE_ILQ) ||
 231                          (cq->cq_type == I40IW_CQ_TYPE_IEQ))
 232                         i40iw_puda_ce_handler(iwdev, cq);
 233         } while (1);
 234 }
 235
 236 /**
 237  * i40iw_next_iw_state - modify qp state
 238  * @iwqp: iwarp qp to modify
 239  * @state: next state for qp
 240  * @del_hash: del hash
 241  * @term: term message
 242  * @termlen: length of term message
 243  */
 244 void i40iw_next_iw_state(struct i40iw_qp *iwqp,
 245                          u8 state,
 246                          u8 del_hash,
 247                          u8 term,
 248                          u8 termlen)
 249 {
 250         struct i40iw_modify_qp_info info;
 251
 252         memset(&info, 0, sizeof(info));
 253         info.next_iwarp_state = state;
 254         info.remove_hash_idx = del_hash;
 255         info.cq_num_valid = true;
 256         info.arp_cache_idx_valid = true;
 257         info.dont_send_term = true;
 258         info.dont_send_fin = true;
 259         info.termlen = termlen;
 260
 261         if (term & I40IWQP_TERM_SEND_TERM_ONLY)
 262                 info.dont_send_term = false;
 263         if (term & I40IWQP_TERM_SEND_FIN_ONLY)
 264                 info.dont_send_fin = false;
 265         if (iwqp->sc_qp.term_flags && (state == I40IW_QP_STATE_ERROR))
 266                 info.reset_tcp_conn = true;
 267         i40iw_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0);
 268 }
 269
 270 /**
 271  * i40iw_process_aeq - handle aeq events
 272  * @iwdev: iwarp device
 273  */
 274 void i40iw_process_aeq(struct i40iw_device *iwdev)
 275 {
 276         struct i40iw_sc_dev *dev = &iwdev->sc_dev;
 277         struct i40iw_aeq *aeq = &iwdev->aeq;
 278         struct i40iw_sc_aeq *sc_aeq = &aeq->sc_aeq;
 279         struct i40iw_aeqe_info aeinfo;
 280         struct i40iw_aeqe_info *info = &aeinfo;
 281         int ret;
 282         struct i40iw_qp *iwqp = NULL;
 283         struct i40iw_sc_cq *cq = NULL;
 284         struct i40iw_cq *iwcq = NULL;
 285         struct i40iw_sc_qp *qp = NULL;
 286         struct i40iw_qp_host_ctx_info *ctx_info = NULL;
 287         unsigned long flags;
 288
 289         u32 aeqcnt = 0;
 290
 291         if (!sc_aeq->size)
 292                 return;
 293
 294         do {
 295                 memset(info, 0, sizeof(*info));
 296                 ret = dev->aeq_ops->get_next_aeqe(sc_aeq, info);
 297                 if (ret)
 298                         break;
 299
 300                 aeqcnt++;
 301                 i40iw_debug(dev, I40IW_DEBUG_AEQ,
 302                             "%s ae_id = 0x%x bool qp=%d qp_id = %d\n",
 303                             __func__, info->ae_id, info->qp, info->qp_cq_id);
 304                 if (info->qp) {
 305                         spin_lock_irqsave(&iwdev->qptable_lock, flags);
 306                         iwqp = iwdev->qp_table[info->qp_cq_id];
 307                         if (!iwqp) {
 308                                 spin_unlock_irqrestore(&iwdev->qptable_lock, flags);
 309                                 i40iw_pr_err("qp_id %d is already freed\n", info->qp_cq_id);
 310                                 continue;
 311                         }
 312                         i40iw_add_ref(&iwqp->ibqp);
 313                         spin_unlock_irqrestore(&iwdev->qptable_lock, flags);
 314                         qp = &iwqp->sc_qp;
 315                         spin_lock_irqsave(&iwqp->lock, flags);
 316                         iwqp->hw_tcp_state = info->tcp_state;
 317                         iwqp->hw_iwarp_state = info->iwarp_state;
 318                         iwqp->last_aeq = info->ae_id;
 319                         spin_unlock_irqrestore(&iwqp->lock, flags);
 320                         ctx_info = &iwqp->ctx_info;
 321                         ctx_info->err_rq_idx_valid = true;
 322                 } else {
 323                         if (info->ae_id != I40IW_AE_CQ_OPERATION_ERROR)
 324                                 continue;
 325                 }
 326
 327                 switch (info->ae_id) {
 328                 case I40IW_AE_LLP_FIN_RECEIVED:
 329                         if (qp->term_flags)
 330                                 continue;
 331                         if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
 332                                 iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSE_WAIT;
 333                                 if ((iwqp->hw_tcp_state == I40IW_TCP_STATE_CLOSE_WAIT) &&
 334                                     (iwqp->ibqp_state == IB_QPS_RTS)) {
 335                                         i40iw_next_iw_state(iwqp,
 336                                                             I40IW_QP_STATE_CLOSING, 0, 0, 0);
 337                                         i40iw_cm_disconn(iwqp);
 338                                 }
 339                                 iwqp->cm_id->add_ref(iwqp->cm_id);
 340                                 i40iw_schedule_cm_timer(iwqp->cm_node,
 341                                                         (struct i40iw_puda_buf *)iwqp,
 342                                                         I40IW_TIMER_TYPE_CLOSE, 1, 0);
 343                         }
 344                         break;
 345                 case I40IW_AE_LLP_CLOSE_COMPLETE:
 346                         if (qp->term_flags)
 347                                 i40iw_terminate_done(qp, 0);
 348                         else
 349                                 i40iw_cm_disconn(iwqp);
 350                         break;
 351                 case I40IW_AE_RESET_SENT:
 352                         i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 1, 0, 0);
 353                         i40iw_cm_disconn(iwqp);
 354                         break;
 355                 case I40IW_AE_LLP_CONNECTION_RESET:
 356                         if (atomic_read(&iwqp->close_timer_started))
 357                                 continue;
 358                         i40iw_cm_disconn(iwqp);
 359                         break;
 360                 case I40IW_AE_TERMINATE_SENT:
 361                         i40iw_terminate_send_fin(qp);
 362                         break;
 363                 case I40IW_AE_LLP_TERMINATE_RECEIVED:
 364                         i40iw_terminate_received(qp, info);
 365                         break;
 366                 case I40IW_AE_CQ_OPERATION_ERROR:
 367                         i40iw_pr_err("Processing an iWARP related AE for CQ misc = 0x%04X\n",
 368                                      info->ae_id);
 369                         cq = (struct i40iw_sc_cq *)(unsigned long)info->compl_ctx;
 370                         iwcq = (struct i40iw_cq *)cq->back_cq;
 371
 372                         if (iwcq->ibcq.event_handler) {
 373                                 struct ib_event ibevent;
 374
 375                                 ibevent.device = iwcq->ibcq.device;
 376                                 ibevent.event = IB_EVENT_CQ_ERR;
 377                                 ibevent.element.cq = &iwcq->ibcq;
 378                                 iwcq->ibcq.event_handler(&ibevent, iwcq->ibcq.cq_context);
 379                         }
 380                         break;
 381                 case I40IW_AE_PRIV_OPERATION_DENIED:
 382                 case I40IW_AE_STAG_ZERO_INVALID:
 383                 case I40IW_AE_IB_RREQ_AND_Q1_FULL:
 384                 case I40IW_AE_DDP_UBE_INVALID_DDP_VERSION:
 385                 case I40IW_AE_DDP_UBE_INVALID_MO:
 386                 case I40IW_AE_DDP_UBE_INVALID_QN:
 387                 case I40IW_AE_DDP_NO_L_BIT:
 388                 case I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
 389                 case I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
 390                 case I40IW_AE_ROE_INVALID_RDMA_READ_REQUEST:
 391                 case I40IW_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
 392                 case I40IW_AE_INVALID_ARP_ENTRY:
 393                 case I40IW_AE_INVALID_TCP_OPTION_RCVD:
 394                 case I40IW_AE_STALE_ARP_ENTRY:
 395                 case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR:
 396                 case I40IW_AE_LLP_SEGMENT_TOO_SMALL:
 397                 case I40IW_AE_LLP_SYN_RECEIVED:
 398                 case I40IW_AE_LLP_TOO_MANY_RETRIES:
 399                 case I40IW_AE_LLP_DOUBT_REACHABILITY:
 400                 case I40IW_AE_LCE_QP_CATASTROPHIC:
 401                 case I40IW_AE_LCE_FUNCTION_CATASTROPHIC:
 402                 case I40IW_AE_LCE_CQ_CATASTROPHIC:
 403                 case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG:
 404                 case I40IW_AE_UDA_XMIT_IPADDR_MISMATCH:
 405                 case I40IW_AE_QP_SUSPEND_COMPLETE:
 406                         ctx_info->err_rq_idx_valid = false;
 407                 default:
 408                                 if (!info->sq && ctx_info->err_rq_idx_valid) {
 409                                         ctx_info->err_rq_idx = info->wqe_idx;
 410                                         ctx_info->tcp_info_valid = false;
 411                                         ctx_info->iwarp_info_valid = false;
 412                                         ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
 413                                                                              iwqp->host_ctx.va,
 414                                                                              ctx_info);
 415                                 }
 416                                 i40iw_terminate_connection(qp, info);
 417                                 break;
 418                 }
 419                 if (info->qp)
 420                         i40iw_rem_ref(&iwqp->ibqp);
 421         } while (1);
 422
 423         if (aeqcnt)
 424                 dev->aeq_ops->repost_aeq_entries(dev, aeqcnt);
 425 }
 426
 427 /**
 428  * i40iw_manage_apbvt - add or delete tcp port
 429  * @iwdev: iwarp device
 430  * @accel_local_port: port for apbvt
 431  * @add_port: add or delete port
 432  */
 433 int i40iw_manage_apbvt(struct i40iw_device *iwdev, u16 accel_local_port, bool add_port)
 434 {
 435         struct i40iw_apbvt_info *info;
 436         enum i40iw_status_code status;
 437         struct i40iw_cqp_request *cqp_request;
 438         struct cqp_commands_info *cqp_info;
 439
 440         cqp_request = i40iw_get_cqp_request(&iwdev->cqp, add_port);
 441         if (!cqp_request)
 442                 return -ENOMEM;
 443
 444         cqp_info = &cqp_request->info;
 445         info = &cqp_info->in.u.manage_apbvt_entry.info;
 446
 447         memset(info, 0, sizeof(*info));
 448         info->add = add_port;
 449         info->port = cpu_to_le16(accel_local_port);
 450
 451         cqp_info->cqp_cmd = OP_MANAGE_APBVT_ENTRY;
 452         cqp_info->post_sq = 1;
 453         cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->cqp.sc_cqp;
 454         cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request;
 455         status = i40iw_handle_cqp_op(iwdev, cqp_request);
 456         if (status)
 457                 i40iw_pr_err("CQP-OP Manage APBVT entry fail");
 458         return status;
 459 }
 460
 461 /**
 462  * i40iw_manage_arp_cache - manage hw arp cache
 463  * @iwdev: iwarp device
 464  * @mac_addr: mac address ptr
 465  * @ip_addr: ip addr for arp cache
 466  * @action: add, delete or modify
 467  */
 468 void i40iw_manage_arp_cache(struct i40iw_device *iwdev,
 469                             unsigned char *mac_addr,
 470                             __be32 *ip_addr,
 471                             bool ipv4,
 472                             u32 action)
 473 {
 474         struct i40iw_add_arp_cache_entry_info *info;
 475         struct i40iw_cqp_request *cqp_request;
 476         struct cqp_commands_info *cqp_info;
 477         int arp_index;
 478
 479         arp_index = i40iw_arp_table(iwdev, ip_addr, ipv4, mac_addr, action);
 480         if (arp_index == -1)
 481                 return;
 482         cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
 483         if (!cqp_request)
 484                 return;
 485
 486         cqp_info = &cqp_request->info;
 487         if (action == I40IW_ARP_ADD) {
 488                 cqp_info->cqp_cmd = OP_ADD_ARP_CACHE_ENTRY;
 489                 info = &cqp_info->in.u.add_arp_cache_entry.info;
 490                 memset(info, 0, sizeof(*info));
 491                 info->arp_index = cpu_to_le32(arp_index);
 492                 info->permanent = true;
 493                 ether_addr_copy(info->mac_addr, mac_addr);
 494                 cqp_info->in.u.add_arp_cache_entry.scratch = (uintptr_t)cqp_request;
 495                 cqp_info->in.u.add_arp_cache_entry.cqp = &iwdev->cqp.sc_cqp;
 496         } else {
 497                 cqp_info->cqp_cmd = OP_DELETE_ARP_CACHE_ENTRY;
 498                 cqp_info->in.u.del_arp_cache_entry.scratch = (uintptr_t)cqp_request;
 499                 cqp_info->in.u.del_arp_cache_entry.cqp = &iwdev->cqp.sc_cqp;
 500                 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index;
 501         }
 502
 503         cqp_info->in.u.add_arp_cache_entry.cqp = &iwdev->cqp.sc_cqp;
 504         cqp_info->in.u.add_arp_cache_entry.scratch = (uintptr_t)cqp_request;
 505         cqp_info->post_sq = 1;
 506         if (i40iw_handle_cqp_op(iwdev, cqp_request))
 507                 i40iw_pr_err("CQP-OP Add/Del Arp Cache entry fail");
 508 }
 509
 510 /**
 511  * i40iw_send_syn_cqp_callback - do syn/ack after qhash
 512  * @cqp_request: qhash cqp completion
 513  * @send_ack: flag send ack
 514  */
 515 static void i40iw_send_syn_cqp_callback(struct i40iw_cqp_request *cqp_request, u32 send_ack)
 516 {
 517         i40iw_send_syn(cqp_request->param, send_ack);
 518 }
 519
 520 /**
 521  * i40iw_manage_qhash - add or modify qhash
 522  * @iwdev: iwarp device
 523  * @cminfo: cm info for qhash
 524  * @etype: type (syn or quad)
 525  * @mtype: type of qhash
 526  * @cmnode: cmnode associated with connection
 527  * @wait: wait for completion
 528  * @user_pri:user pri of the connection
 529  */
 530 enum i40iw_status_code i40iw_manage_qhash(struct i40iw_device *iwdev,
 531                                           struct i40iw_cm_info *cminfo,
 532                                           enum i40iw_quad_entry_type etype,
 533                                           enum i40iw_quad_hash_manage_type mtype,
 534                                           void *cmnode,
 535                                           bool wait)
 536 {
 537         struct i40iw_qhash_table_info *info;
 538         struct i40iw_sc_dev *dev = &iwdev->sc_dev;
 539         enum i40iw_status_code status;
 540         struct i40iw_cqp *iwcqp = &iwdev->cqp;
 541         struct i40iw_cqp_request *cqp_request;
 542         struct cqp_commands_info *cqp_info;
 543
 544         cqp_request = i40iw_get_cqp_request(iwcqp, wait);
 545         if (!cqp_request)
 546                 return I40IW_ERR_NO_MEMORY;
 547         cqp_info = &cqp_request->info;
 548         info = &cqp_info->in.u.manage_qhash_table_entry.info;
 549         memset(info, 0, sizeof(*info));
 550
 551         info->manage = mtype;
 552         info->entry_type = etype;
 553         if (cminfo->vlan_id != 0xFFFF) {
 554                 info->vlan_valid = true;
 555                 info->vlan_id = cpu_to_le16(cminfo->vlan_id);
 556         } else {
 557                 info->vlan_valid = false;
 558         }
 559
 560         info->ipv4_valid = cminfo->ipv4;
 561         ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr);
 562         info->qp_num = cpu_to_le32(dev->ilq->qp_id);
 563         info->dest_port = cpu_to_le16(cminfo->loc_port);
 564         info->dest_ip[0] = cpu_to_le32(cminfo->loc_addr[0]);
 565         info->dest_ip[1] = cpu_to_le32(cminfo->loc_addr[1]);
 566         info->dest_ip[2] = cpu_to_le32(cminfo->loc_addr[2]);
 567         info->dest_ip[3] = cpu_to_le32(cminfo->loc_addr[3]);
 568         if (etype == I40IW_QHASH_TYPE_TCP_ESTABLISHED) {
 569                 info->src_port = cpu_to_le16(cminfo->rem_port);
 570                 info->src_ip[0] = cpu_to_le32(cminfo->rem_addr[0]);
 571                 info->src_ip[1] = cpu_to_le32(cminfo->rem_addr[1]);
 572                 info->src_ip[2] = cpu_to_le32(cminfo->rem_addr[2]);
 573                 info->src_ip[3] = cpu_to_le32(cminfo->rem_addr[3]);
 574         }
 575         if (cmnode) {
 576                 cqp_request->callback_fcn = i40iw_send_syn_cqp_callback;
 577                 cqp_request->param = (void *)cmnode;
 578         }
 579
 580         if (info->ipv4_valid)
 581                 i40iw_debug(dev, I40IW_DEBUG_CM,
 582                             "%s:%s IP=%pI4, port=%d, mac=%pM, vlan_id=%d\n",
 583                             __func__, (!mtype) ? "DELETE" : "ADD",
 584                             info->dest_ip,
 585                             info->dest_port, info->mac_addr, cminfo->vlan_id);
 586         else
 587                 i40iw_debug(dev, I40IW_DEBUG_CM,
 588                             "%s:%s IP=%pI6, port=%d, mac=%pM, vlan_id=%d\n",
 589                             __func__, (!mtype) ? "DELETE" : "ADD",
 590                             info->dest_ip,
 591                             info->dest_port, info->mac_addr, cminfo->vlan_id);
 592         cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->cqp.sc_cqp;
 593         cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request;
 594         cqp_info->cqp_cmd = OP_MANAGE_QHASH_TABLE_ENTRY;
 595         cqp_info->post_sq = 1;
 596         status = i40iw_handle_cqp_op(iwdev, cqp_request);
 597         if (status)
 598                 i40iw_pr_err("CQP-OP Manage Qhash Entry fail");
 599         return status;
 600 }
 601
 602 /**
 603  * i40iw_hw_flush_wqes - flush qp's wqe
 604  * @iwdev: iwarp device
 605  * @qp: hardware control qp
 606  * @info: info for flush
 607  * @wait: flag wait for completion
 608  */
 609 enum i40iw_status_code i40iw_hw_flush_wqes(struct i40iw_device *iwdev,
 610                                            struct i40iw_sc_qp *qp,
 611                                            struct i40iw_qp_flush_info *info,
 612                                            bool wait)
 613 {
 614         enum i40iw_status_code status;
 615         struct i40iw_qp_flush_info *hw_info;
 616         struct i40iw_cqp_request *cqp_request;
 617         struct cqp_commands_info *cqp_info;
 618
 619         cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
 620         if (!cqp_request)
 621                 return I40IW_ERR_NO_MEMORY;
 622
 623         cqp_info = &cqp_request->info;
 624         hw_info = &cqp_request->info.in.u.qp_flush_wqes.info;
 625         memcpy(hw_info, info, sizeof(*hw_info));
 626
 627         cqp_info->cqp_cmd = OP_QP_FLUSH_WQES;
 628         cqp_info->post_sq = 1;
 629         cqp_info->in.u.qp_flush_wqes.qp = qp;
 630         cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request;
 631         status = i40iw_handle_cqp_op(iwdev, cqp_request);
 632         if (status)
 633                 i40iw_pr_err("CQP-OP Flush WQE's fail");
 634         return status;
 635 }
 636
 637 /**
 638  * i40iw_hw_manage_vf_pble_bp - manage vf pbles
 639  * @iwdev: iwarp device
 640  * @info: info for managing pble
 641  * @wait: flag wait for completion
 642  */
 643 enum i40iw_status_code i40iw_hw_manage_vf_pble_bp(struct i40iw_device *iwdev,
 644                                                   struct i40iw_manage_vf_pble_info *info,
 645                                                   bool wait)
 646 {
 647         enum i40iw_status_code status;
 648         struct i40iw_manage_vf_pble_info *hw_info;
 649         struct i40iw_cqp_request *cqp_request;
 650         struct cqp_commands_info *cqp_info;
 651
 652         if ((iwdev->init_state < CCQ_CREATED) && wait)
 653                 wait = false;
 654
 655         cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
 656         if (!cqp_request)
 657                 return I40IW_ERR_NO_MEMORY;
 658
 659         cqp_info = &cqp_request->info;
 660         hw_info = &cqp_request->info.in.u.manage_vf_pble_bp.info;
 661         memcpy(hw_info, info, sizeof(*hw_info));
 662
 663         cqp_info->cqp_cmd = OP_MANAGE_VF_PBLE_BP;
 664         cqp_info->post_sq = 1;
 665         cqp_info->in.u.manage_vf_pble_bp.cqp = &iwdev->cqp.sc_cqp;
 666         cqp_info->in.u.manage_vf_pble_bp.scratch = (uintptr_t)cqp_request;
 667         status = i40iw_handle_cqp_op(iwdev, cqp_request);
 668         if (status)
 669                 i40iw_pr_err("CQP-OP Manage VF pble_bp fail");
 670         return status;
 671 }
 672
 673 /**
 674  * i40iw_get_ib_wc - return change flush code to IB's
 675  * @opcode: iwarp flush code
 676  */
 677 static enum ib_wc_status i40iw_get_ib_wc(enum i40iw_flush_opcode opcode)
 678 {
 679         switch (opcode) {
 680         case FLUSH_PROT_ERR:
 681                 return IB_WC_LOC_PROT_ERR;
 682         case FLUSH_REM_ACCESS_ERR:
 683                 return IB_WC_REM_ACCESS_ERR;
 684         case FLUSH_LOC_QP_OP_ERR:
 685                 return IB_WC_LOC_QP_OP_ERR;
 686         case FLUSH_REM_OP_ERR:
 687                 return IB_WC_REM_OP_ERR;
 688         case FLUSH_LOC_LEN_ERR:
 689                 return IB_WC_LOC_LEN_ERR;
 690         case FLUSH_GENERAL_ERR:
 691                 return IB_WC_GENERAL_ERR;
 692         case FLUSH_FATAL_ERR:
 693         default:
 694                 return IB_WC_FATAL_ERR;
 695         }
 696 }
 697
 698 /**
 699  * i40iw_set_flush_info - set flush info
 700  * @pinfo: set flush info
 701  * @min: minor err
 702  * @maj: major err
 703  * @opcode: flush error code
 704  */
 705 static void i40iw_set_flush_info(struct i40iw_qp_flush_info *pinfo,
 706                                  u16 *min,
 707                                  u16 *maj,
 708                                  enum i40iw_flush_opcode opcode)
 709 {
 710         *min = (u16)i40iw_get_ib_wc(opcode);
 711         *maj = CQE_MAJOR_DRV;
 712         pinfo->userflushcode = true;
 713 }
 714
 715 /**
 716  * i40iw_flush_wqes - flush wqe for qp
 717  * @iwdev: iwarp device
 718  * @iwqp: qp to flush wqes
 719  */
 720 void i40iw_flush_wqes(struct i40iw_device *iwdev, struct i40iw_qp *iwqp)
 721 {
 722         struct i40iw_qp_flush_info info;
 723         struct i40iw_qp_flush_info *pinfo = &info;
 724
 725         struct i40iw_sc_qp *qp = &iwqp->sc_qp;
 726
 727         memset(pinfo, 0, sizeof(*pinfo));
 728         info.sq = true;
 729         info.rq = true;
 730         if (qp->term_flags) {
 731                 i40iw_set_flush_info(pinfo, &pinfo->sq_minor_code,
 732                                      &pinfo->sq_major_code, qp->flush_code);
 733                 i40iw_set_flush_info(pinfo, &pinfo->rq_minor_code,
 734                                      &pinfo->rq_major_code, qp->flush_code);
 735         }
 736         (void)i40iw_hw_flush_wqes(iwdev, &iwqp->sc_qp, &info, true);
 737 }