drivers/infiniband/hw/i40iw/i40iw_hw.c

   1 /*******************************************************************************
   2 *
   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenFabrics.org BSD license below:
  10 *
  11 *   Redistribution and use in source and binary forms, with or
  12 *   without modification, are permitted provided that the following
  13 *   conditions are met:
  14 *
  15 *    - Redistributions of source code must retain the above
  16 *       copyright notice, this list of conditions and the following
  17 *       disclaimer.
  18 *
  19 *    - Redistributions in binary form must reproduce the above
  20 *       copyright notice, this list of conditions and the following
  21 *       disclaimer in the documentation and/or other materials
  22 *       provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 *
  33 *******************************************************************************/
  34
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/netdevice.h>
  38 #include <linux/etherdevice.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/if_vlan.h>
  42
  43 #include "i40iw.h"
  44
  45 /**
  46  * i40iw_initialize_hw_resources - initialize hw resource during open
  47  * @iwdev: iwarp device
  48  */
  49 u32 i40iw_initialize_hw_resources(struct i40iw_device *iwdev)
  50 {
  51         unsigned long num_pds;
  52         u32 resources_size;
  53         u32 max_mr;
  54         u32 max_qp;
  55         u32 max_cq;
  56         u32 arp_table_size;
  57         u32 mrdrvbits;
  58         void *resource_ptr;
  59
  60         max_qp = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt;
  61         max_cq = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt;
  62         max_mr = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_MR].cnt;
  63         arp_table_size = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_ARP].cnt;
  64         iwdev->max_cqe = 0xFFFFF;
  65         num_pds = max_qp * 4;
  66         resources_size = sizeof(struct i40iw_arp_entry) * arp_table_size;
  67         resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_qp);
  68         resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_mr);
  69         resources_size += sizeof(unsigned long) * BITS_TO_LONGS(max_cq);
  70         resources_size += sizeof(unsigned long) * BITS_TO_LONGS(num_pds);
  71         resources_size += sizeof(unsigned long) * BITS_TO_LONGS(arp_table_size);
  72         resources_size += sizeof(struct i40iw_qp **) * max_qp;
  73         iwdev->mem_resources = kzalloc(resources_size, GFP_KERNEL);
  74
  75         if (!iwdev->mem_resources)
  76                 return -ENOMEM;
  77
  78         iwdev->max_qp = max_qp;
  79         iwdev->max_mr = max_mr;
  80         iwdev->max_cq = max_cq;
  81         iwdev->max_pd = num_pds;
  82         iwdev->arp_table_size = arp_table_size;
  83         iwdev->arp_table = (struct i40iw_arp_entry *)iwdev->mem_resources;
  84         resource_ptr = iwdev->mem_resources + (sizeof(struct i40iw_arp_entry) * arp_table_size);
  85
  86         iwdev->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY |
  87             IB_DEVICE_MEM_WINDOW | IB_DEVICE_MEM_MGT_EXTENSIONS;
  88
  89         iwdev->allocated_qps = resource_ptr;
  90         iwdev->allocated_cqs = &iwdev->allocated_qps[BITS_TO_LONGS(max_qp)];
  91         iwdev->allocated_mrs = &iwdev->allocated_cqs[BITS_TO_LONGS(max_cq)];
  92         iwdev->allocated_pds = &iwdev->allocated_mrs[BITS_TO_LONGS(max_mr)];
  93         iwdev->allocated_arps = &iwdev->allocated_pds[BITS_TO_LONGS(num_pds)];
  94         iwdev->qp_table = (struct i40iw_qp **)(&iwdev->allocated_arps[BITS_TO_LONGS(arp_table_size)]);
  95         set_bit(0, iwdev->allocated_mrs);
  96         set_bit(0, iwdev->allocated_qps);
  97         set_bit(0, iwdev->allocated_cqs);
  98         set_bit(0, iwdev->allocated_pds);
  99         set_bit(0, iwdev->allocated_arps);
 100
 101         /* Following for ILQ/IEQ */
 102         set_bit(1, iwdev->allocated_qps);
 103         set_bit(1, iwdev->allocated_cqs);
 104         set_bit(1, iwdev->allocated_pds);
 105         set_bit(2, iwdev->allocated_cqs);
 106         set_bit(2, iwdev->allocated_pds);
 107
 108         spin_lock_init(&iwdev->resource_lock);
 109         mrdrvbits = 24 - get_count_order(iwdev->max_mr);
 110         iwdev->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits));
 111         return 0;
 112 }
 113
 114 /**
 115  * i40iw_cqp_ce_handler - handle cqp completions
 116  * @iwdev: iwarp device
 117  * @arm: flag to arm after completions
 118  * @cq: cq for cqp completions
 119  */
 120 static void i40iw_cqp_ce_handler(struct i40iw_device *iwdev, struct i40iw_sc_cq *cq, bool arm)
 121 {
 122         struct i40iw_cqp_request *cqp_request;
 123         struct i40iw_sc_dev *dev = &iwdev->sc_dev;
 124         u32 cqe_count = 0;
 125         struct i40iw_ccq_cqe_info info;
 126         int ret;
 127
 128         do {
 129                 memset(&info, 0, sizeof(info));
 130                 ret = dev->ccq_ops->ccq_get_cqe_info(cq, &info);
 131                 if (ret)
 132                         break;
 133                 cqp_request = (struct i40iw_cqp_request *)(unsigned long)info.scratch;
 134                 if (info.error)
 135                         i40iw_pr_err("opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n",
 136                                      info.op_code, info.maj_err_code, info.min_err_code);
 137                 if (cqp_request) {
 138                         cqp_request->compl_info.maj_err_code = info.maj_err_code;
 139                         cqp_request->compl_info.min_err_code = info.min_err_code;
 140                         cqp_request->compl_info.op_ret_val = info.op_ret_val;
 141                         cqp_request->compl_info.error = info.error;
 142
 143                         if (cqp_request->waiting) {
 144                                 cqp_request->request_done = true;
 145                                 wake_up(&cqp_request->waitq);
 146                                 i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
 147                         } else {
 148                                 if (cqp_request->callback_fcn)
 149                                         cqp_request->callback_fcn(cqp_request, 1);
 150                                 i40iw_put_cqp_request(&iwdev->cqp, cqp_request);
 151                         }
 152                 }
 153
 154                 cqe_count++;
 155         } while (1);
 156
 157         if (arm && cqe_count) {
 158                 i40iw_process_bh(dev);
 159                 dev->ccq_ops->ccq_arm(cq);
 160         }
 161 }
 162
 163 /**
 164  * i40iw_iwarp_ce_handler - handle iwarp completions
 165  * @iwdev: iwarp device
 166  * @iwcp: iwarp cq receiving event
 167  */
 168 static void i40iw_iwarp_ce_handler(struct i40iw_device *iwdev,
 169                                    struct i40iw_sc_cq *iwcq)
 170 {
 171         struct i40iw_cq *i40iwcq = iwcq->back_cq;
 172
 173         if (i40iwcq->ibcq.comp_handler)
 174                 i40iwcq->ibcq.comp_handler(&i40iwcq->ibcq,
 175                                            i40iwcq->ibcq.cq_context);
 176 }
 177
 178 /**
 179  * i40iw_puda_ce_handler - handle puda completion events
 180  * @iwdev: iwarp device
 181  * @cq: puda completion q for event
 182  */
 183 static void i40iw_puda_ce_handler(struct i40iw_device *iwdev,
 184                                   struct i40iw_sc_cq *cq)
 185 {
 186         struct i40iw_sc_dev *dev = (struct i40iw_sc_dev *)&iwdev->sc_dev;
 187         enum i40iw_status_code status;
 188         u32 compl_error;
 189
 190         do {
 191                 status = i40iw_puda_poll_completion(dev, cq, &compl_error);
 192                 if (status == I40IW_ERR_QUEUE_EMPTY)
 193                         break;
 194                 if (status) {
 195                         i40iw_pr_err("puda  status = %d\n", status);
 196                         break;
 197                 }
 198                 if (compl_error) {
 199                         i40iw_pr_err("puda compl_err  =0x%x\n", compl_error);
 200                         break;
 201                 }
 202         } while (1);
 203
 204         dev->ccq_ops->ccq_arm(cq);
 205 }
 206
 207 /**
 208  * i40iw_process_ceq - handle ceq for completions
 209  * @iwdev: iwarp device
 210  * @ceq: ceq having cq for completion
 211  */
 212 void i40iw_process_ceq(struct i40iw_device *iwdev, struct i40iw_ceq *ceq)
 213 {
 214         struct i40iw_sc_dev *dev = &iwdev->sc_dev;
 215         struct i40iw_sc_ceq *sc_ceq;
 216         struct i40iw_sc_cq *cq;
 217         bool arm = true;
 218
 219         sc_ceq = &ceq->sc_ceq;
 220         do {
 221                 cq = dev->ceq_ops->process_ceq(dev, sc_ceq);
 222                 if (!cq)
 223                         break;
 224
 225                 if (cq->cq_type == I40IW_CQ_TYPE_CQP)
 226                         i40iw_cqp_ce_handler(iwdev, cq, arm);
 227                 else if (cq->cq_type == I40IW_CQ_TYPE_IWARP)
 228                         i40iw_iwarp_ce_handler(iwdev, cq);
 229                 else if ((cq->cq_type == I40IW_CQ_TYPE_ILQ) ||
 230                          (cq->cq_type == I40IW_CQ_TYPE_IEQ))
 231                         i40iw_puda_ce_handler(iwdev, cq);
 232         } while (1);
 233 }
 234
 235 /**
 236  * i40iw_next_iw_state - modify qp state
 237  * @iwqp: iwarp qp to modify
 238  * @state: next state for qp
 239  * @del_hash: del hash
 240  * @term: term message
 241  * @termlen: length of term message
 242  */
 243 void i40iw_next_iw_state(struct i40iw_qp *iwqp,
 244                          u8 state,
 245                          u8 del_hash,
 246                          u8 term,
 247                          u8 termlen)
 248 {
 249         struct i40iw_modify_qp_info info;
 250
 251         memset(&info, 0, sizeof(info));
 252         info.next_iwarp_state = state;
 253         info.remove_hash_idx = del_hash;
 254         info.cq_num_valid = true;
 255         info.arp_cache_idx_valid = true;
 256         info.dont_send_term = true;
 257         info.dont_send_fin = true;
 258         info.termlen = termlen;
 259
 260         if (term & I40IWQP_TERM_SEND_TERM_ONLY)
 261                 info.dont_send_term = false;
 262         if (term & I40IWQP_TERM_SEND_FIN_ONLY)
 263                 info.dont_send_fin = false;
 264         if (iwqp->sc_qp.term_flags && (state == I40IW_QP_STATE_ERROR))
 265                 info.reset_tcp_conn = true;
 266         i40iw_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0);
 267 }
 268
 269 /**
 270  * i40iw_process_aeq - handle aeq events
 271  * @iwdev: iwarp device
 272  */
 273 void i40iw_process_aeq(struct i40iw_device *iwdev)
 274 {
 275         struct i40iw_sc_dev *dev = &iwdev->sc_dev;
 276         struct i40iw_aeq *aeq = &iwdev->aeq;
 277         struct i40iw_sc_aeq *sc_aeq = &aeq->sc_aeq;
 278         struct i40iw_aeqe_info aeinfo;
 279         struct i40iw_aeqe_info *info = &aeinfo;
 280         int ret;
 281         struct i40iw_qp *iwqp = NULL;
 282         struct i40iw_sc_cq *cq = NULL;
 283         struct i40iw_cq *iwcq = NULL;
 284         struct i40iw_sc_qp *qp = NULL;
 285         struct i40iw_qp_host_ctx_info *ctx_info = NULL;
 286         unsigned long flags;
 287
 288         u32 aeqcnt = 0;
 289
 290         if (!sc_aeq->size)
 291                 return;
 292
 293         do {
 294                 memset(info, 0, sizeof(*info));
 295                 ret = dev->aeq_ops->get_next_aeqe(sc_aeq, info);
 296                 if (ret)
 297                         break;
 298
 299                 aeqcnt++;
 300                 i40iw_debug(dev, I40IW_DEBUG_AEQ,
 301                             "%s ae_id = 0x%x bool qp=%d qp_id = %d\n",
 302                             __func__, info->ae_id, info->qp, info->qp_cq_id);
 303                 if (info->qp) {
 304                         iwqp = iwdev->qp_table[info->qp_cq_id];
 305                         if (!iwqp) {
 306                                 i40iw_pr_err("qp_id %d is already freed\n", info->qp_cq_id);
 307                                 continue;
 308                         }
 309                         qp = &iwqp->sc_qp;
 310                         spin_lock_irqsave(&iwqp->lock, flags);
 311                         iwqp->hw_tcp_state = info->tcp_state;
 312                         iwqp->hw_iwarp_state = info->iwarp_state;
 313                         iwqp->last_aeq = info->ae_id;
 314                         spin_unlock_irqrestore(&iwqp->lock, flags);
 315                         ctx_info = &iwqp->ctx_info;
 316                         ctx_info->err_rq_idx_valid = true;
 317                 } else {
 318                         if (info->ae_id != I40IW_AE_CQ_OPERATION_ERROR)
 319                                 continue;
 320                 }
 321
 322                 switch (info->ae_id) {
 323                 case I40IW_AE_LLP_FIN_RECEIVED:
 324                         if (qp->term_flags)
 325                                 continue;
 326                         if (atomic_inc_return(&iwqp->close_timer_started) == 1) {
 327                                 iwqp->hw_tcp_state = I40IW_TCP_STATE_CLOSE_WAIT;
 328                                 if ((iwqp->hw_tcp_state == I40IW_TCP_STATE_CLOSE_WAIT) &&
 329                                     (iwqp->ibqp_state == IB_QPS_RTS)) {
 330                                         i40iw_next_iw_state(iwqp,
 331                                                             I40IW_QP_STATE_CLOSING, 0, 0, 0);
 332                                         i40iw_cm_disconn(iwqp);
 333                                 }
 334                                 iwqp->cm_id->add_ref(iwqp->cm_id);
 335                                 i40iw_schedule_cm_timer(iwqp->cm_node,
 336                                                         (struct i40iw_puda_buf *)iwqp,
 337                                                         I40IW_TIMER_TYPE_CLOSE, 1, 0);
 338                         }
 339                         break;
 340                 case I40IW_AE_LLP_CLOSE_COMPLETE:
 341                         if (qp->term_flags)
 342                                 i40iw_terminate_done(qp, 0);
 343                         else
 344                                 i40iw_cm_disconn(iwqp);
 345                         break;
 346                 case I40IW_AE_RESET_SENT:
 347                         i40iw_next_iw_state(iwqp, I40IW_QP_STATE_ERROR, 1, 0, 0);
 348                         i40iw_cm_disconn(iwqp);
 349                         break;
 350                 case I40IW_AE_LLP_CONNECTION_RESET:
 351                         if (atomic_read(&iwqp->close_timer_started))
 352                                 continue;
 353                         i40iw_cm_disconn(iwqp);
 354                         break;
 355                 case I40IW_AE_TERMINATE_SENT:
 356                         i40iw_terminate_send_fin(qp);
 357                         break;
 358                 case I40IW_AE_LLP_TERMINATE_RECEIVED:
 359                         i40iw_terminate_received(qp, info);
 360                         break;
 361                 case I40IW_AE_CQ_OPERATION_ERROR:
 362                         i40iw_pr_err("Processing an iWARP related AE for CQ misc = 0x%04X\n",
 363                                      info->ae_id);
 364                         cq = (struct i40iw_sc_cq *)(unsigned long)info->compl_ctx;
 365                         iwcq = (struct i40iw_cq *)cq->back_cq;
 366
 367                         if (iwcq->ibcq.event_handler) {
 368                                 struct ib_event ibevent;
 369
 370                                 ibevent.device = iwcq->ibcq.device;
 371                                 ibevent.event = IB_EVENT_CQ_ERR;
 372                                 ibevent.element.cq = &iwcq->ibcq;
 373                                 iwcq->ibcq.event_handler(&ibevent, iwcq->ibcq.cq_context);
 374                         }
 375                         break;
 376                 case I40IW_AE_PRIV_OPERATION_DENIED:
 377                 case I40IW_AE_STAG_ZERO_INVALID:
 378                 case I40IW_AE_IB_RREQ_AND_Q1_FULL:
 379                 case I40IW_AE_DDP_UBE_INVALID_DDP_VERSION:
 380                 case I40IW_AE_DDP_UBE_INVALID_MO:
 381                 case I40IW_AE_DDP_UBE_INVALID_QN:
 382                 case I40IW_AE_DDP_NO_L_BIT:
 383                 case I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION:
 384                 case I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE:
 385                 case I40IW_AE_ROE_INVALID_RDMA_READ_REQUEST:
 386                 case I40IW_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP:
 387                 case I40IW_AE_INVALID_ARP_ENTRY:
 388                 case I40IW_AE_INVALID_TCP_OPTION_RCVD:
 389                 case I40IW_AE_STALE_ARP_ENTRY:
 390                 case I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR:
 391                 case I40IW_AE_LLP_SEGMENT_TOO_SMALL:
 392                 case I40IW_AE_LLP_SYN_RECEIVED:
 393                 case I40IW_AE_LLP_TOO_MANY_RETRIES:
 394                 case I40IW_AE_LLP_DOUBT_REACHABILITY:
 395                 case I40IW_AE_LCE_QP_CATASTROPHIC:
 396                 case I40IW_AE_LCE_FUNCTION_CATASTROPHIC:
 397                 case I40IW_AE_LCE_CQ_CATASTROPHIC:
 398                 case I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG:
 399                 case I40IW_AE_UDA_XMIT_IPADDR_MISMATCH:
 400                 case I40IW_AE_QP_SUSPEND_COMPLETE:
 401                         ctx_info->err_rq_idx_valid = false;
 402                 default:
 403                                 if (!info->sq && ctx_info->err_rq_idx_valid) {
 404                                         ctx_info->err_rq_idx = info->wqe_idx;
 405                                         ctx_info->tcp_info_valid = false;
 406                                         ctx_info->iwarp_info_valid = false;
 407                                         ret = dev->iw_priv_qp_ops->qp_setctx(&iwqp->sc_qp,
 408                                                                              iwqp->host_ctx.va,
 409                                                                              ctx_info);
 410                                 }
 411                                 i40iw_terminate_connection(qp, info);
 412                                 break;
 413                 }
 414         } while (1);
 415
 416         if (aeqcnt)
 417                 dev->aeq_ops->repost_aeq_entries(dev, aeqcnt);
 418 }
 419
 420 /**
 421  * i40iw_manage_apbvt - add or delete tcp port
 422  * @iwdev: iwarp device
 423  * @accel_local_port: port for apbvt
 424  * @add_port: add or delete port
 425  */
 426 int i40iw_manage_apbvt(struct i40iw_device *iwdev, u16 accel_local_port, bool add_port)
 427 {
 428         struct i40iw_apbvt_info *info;
 429         enum i40iw_status_code status;
 430         struct i40iw_cqp_request *cqp_request;
 431         struct cqp_commands_info *cqp_info;
 432
 433         cqp_request = i40iw_get_cqp_request(&iwdev->cqp, add_port);
 434         if (!cqp_request)
 435                 return -ENOMEM;
 436
 437         cqp_info = &cqp_request->info;
 438         info = &cqp_info->in.u.manage_apbvt_entry.info;
 439
 440         memset(info, 0, sizeof(*info));
 441         info->add = add_port;
 442         info->port = cpu_to_le16(accel_local_port);
 443
 444         cqp_info->cqp_cmd = OP_MANAGE_APBVT_ENTRY;
 445         cqp_info->post_sq = 1;
 446         cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->cqp.sc_cqp;
 447         cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request;
 448         status = i40iw_handle_cqp_op(iwdev, cqp_request);
 449         if (status)
 450                 i40iw_pr_err("CQP-OP Manage APBVT entry fail");
 451         return status;
 452 }
 453
 454 /**
 455  * i40iw_manage_arp_cache - manage hw arp cache
 456  * @iwdev: iwarp device
 457  * @mac_addr: mac address ptr
 458  * @ip_addr: ip addr for arp cache
 459  * @action: add, delete or modify
 460  */
 461 void i40iw_manage_arp_cache(struct i40iw_device *iwdev,
 462                             unsigned char *mac_addr,
 463                             __be32 *ip_addr,
 464                             bool ipv4,
 465                             u32 action)
 466 {
 467         struct i40iw_add_arp_cache_entry_info *info;
 468         struct i40iw_cqp_request *cqp_request;
 469         struct cqp_commands_info *cqp_info;
 470         int arp_index;
 471
 472         arp_index = i40iw_arp_table(iwdev, ip_addr, ipv4, mac_addr, action);
 473         if (arp_index == -1)
 474                 return;
 475         cqp_request = i40iw_get_cqp_request(&iwdev->cqp, false);
 476         if (!cqp_request)
 477                 return;
 478
 479         cqp_info = &cqp_request->info;
 480         if (action == I40IW_ARP_ADD) {
 481                 cqp_info->cqp_cmd = OP_ADD_ARP_CACHE_ENTRY;
 482                 info = &cqp_info->in.u.add_arp_cache_entry.info;
 483                 memset(info, 0, sizeof(*info));
 484                 info->arp_index = cpu_to_le32(arp_index);
 485                 info->permanent = true;
 486                 ether_addr_copy(info->mac_addr, mac_addr);
 487                 cqp_info->in.u.add_arp_cache_entry.scratch = (uintptr_t)cqp_request;
 488                 cqp_info->in.u.add_arp_cache_entry.cqp = &iwdev->cqp.sc_cqp;
 489         } else {
 490                 cqp_info->cqp_cmd = OP_DELETE_ARP_CACHE_ENTRY;
 491                 cqp_info->in.u.del_arp_cache_entry.scratch = (uintptr_t)cqp_request;
 492                 cqp_info->in.u.del_arp_cache_entry.cqp = &iwdev->cqp.sc_cqp;
 493                 cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index;
 494         }
 495
 496         cqp_info->in.u.add_arp_cache_entry.cqp = &iwdev->cqp.sc_cqp;
 497         cqp_info->in.u.add_arp_cache_entry.scratch = (uintptr_t)cqp_request;
 498         cqp_info->post_sq = 1;
 499         if (i40iw_handle_cqp_op(iwdev, cqp_request))
 500                 i40iw_pr_err("CQP-OP Add/Del Arp Cache entry fail");
 501 }
 502
 503 /**
 504  * i40iw_send_syn_cqp_callback - do syn/ack after qhash
 505  * @cqp_request: qhash cqp completion
 506  * @send_ack: flag send ack
 507  */
 508 static void i40iw_send_syn_cqp_callback(struct i40iw_cqp_request *cqp_request, u32 send_ack)
 509 {
 510         i40iw_send_syn(cqp_request->param, send_ack);
 511 }
 512
 513 /**
 514  * i40iw_manage_qhash - add or modify qhash
 515  * @iwdev: iwarp device
 516  * @cminfo: cm info for qhash
 517  * @etype: type (syn or quad)
 518  * @mtype: type of qhash
 519  * @cmnode: cmnode associated with connection
 520  * @wait: wait for completion
 521  * @user_pri:user pri of the connection
 522  */
 523 enum i40iw_status_code i40iw_manage_qhash(struct i40iw_device *iwdev,
 524                                           struct i40iw_cm_info *cminfo,
 525                                           enum i40iw_quad_entry_type etype,
 526                                           enum i40iw_quad_hash_manage_type mtype,
 527                                           void *cmnode,
 528                                           bool wait)
 529 {
 530         struct i40iw_qhash_table_info *info;
 531         struct i40iw_sc_dev *dev = &iwdev->sc_dev;
 532         enum i40iw_status_code status;
 533         struct i40iw_cqp *iwcqp = &iwdev->cqp;
 534         struct i40iw_cqp_request *cqp_request;
 535         struct cqp_commands_info *cqp_info;
 536
 537         cqp_request = i40iw_get_cqp_request(iwcqp, wait);
 538         if (!cqp_request)
 539                 return I40IW_ERR_NO_MEMORY;
 540         cqp_info = &cqp_request->info;
 541         info = &cqp_info->in.u.manage_qhash_table_entry.info;
 542         memset(info, 0, sizeof(*info));
 543
 544         info->manage = mtype;
 545         info->entry_type = etype;
 546         if (cminfo->vlan_id != 0xFFFF) {
 547                 info->vlan_valid = true;
 548                 info->vlan_id = cpu_to_le16(cminfo->vlan_id);
 549         } else {
 550                 info->vlan_valid = false;
 551         }
 552
 553         info->ipv4_valid = cminfo->ipv4;
 554         ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr);
 555         info->qp_num = cpu_to_le32(dev->ilq->qp_id);
 556         info->dest_port = cpu_to_le16(cminfo->map_loc_port);
 557         info->dest_ip[0] = cpu_to_le32(cminfo->map_loc_addr[0]);
 558         info->dest_ip[1] = cpu_to_le32(cminfo->map_loc_addr[1]);
 559         info->dest_ip[2] = cpu_to_le32(cminfo->map_loc_addr[2]);
 560         info->dest_ip[3] = cpu_to_le32(cminfo->map_loc_addr[3]);
 561         if (etype == I40IW_QHASH_TYPE_TCP_ESTABLISHED) {
 562                 info->src_port = cpu_to_le16(cminfo->map_rem_port);
 563                 info->src_ip[0] = cpu_to_le32(cminfo->map_rem_addr[0]);
 564                 info->src_ip[1] = cpu_to_le32(cminfo->map_rem_addr[1]);
 565                 info->src_ip[2] = cpu_to_le32(cminfo->map_rem_addr[2]);
 566                 info->src_ip[3] = cpu_to_le32(cminfo->map_rem_addr[3]);
 567         }
 568         if (cmnode) {
 569                 cqp_request->callback_fcn = i40iw_send_syn_cqp_callback;
 570                 cqp_request->param = (void *)cmnode;
 571         }
 572
 573         if (info->ipv4_valid)
 574                 i40iw_debug(dev, I40IW_DEBUG_CM,
 575                             "%s:%s IP=%pI4, port=%d, mac=%pM, vlan_id=%d\n",
 576                             __func__, (!mtype) ? "DELETE" : "ADD",
 577                             info->dest_ip,
 578                             info->dest_port, info->mac_addr, cminfo->vlan_id);
 579         else
 580                 i40iw_debug(dev, I40IW_DEBUG_CM,
 581                             "%s:%s IP=%pI6, port=%d, mac=%pM, vlan_id=%d\n",
 582                             __func__, (!mtype) ? "DELETE" : "ADD",
 583                             info->dest_ip,
 584                             info->dest_port, info->mac_addr, cminfo->vlan_id);
 585         cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->cqp.sc_cqp;
 586         cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request;
 587         cqp_info->cqp_cmd = OP_MANAGE_QHASH_TABLE_ENTRY;
 588         cqp_info->post_sq = 1;
 589         status = i40iw_handle_cqp_op(iwdev, cqp_request);
 590         if (status)
 591                 i40iw_pr_err("CQP-OP Manage Qhash Entry fail");
 592         return status;
 593 }
 594
 595 /**
 596  * i40iw_hw_flush_wqes - flush qp's wqe
 597  * @iwdev: iwarp device
 598  * @qp: hardware control qp
 599  * @info: info for flush
 600  * @wait: flag wait for completion
 601  */
 602 enum i40iw_status_code i40iw_hw_flush_wqes(struct i40iw_device *iwdev,
 603                                            struct i40iw_sc_qp *qp,
 604                                            struct i40iw_qp_flush_info *info,
 605                                            bool wait)
 606 {
 607         enum i40iw_status_code status;
 608         struct i40iw_qp_flush_info *hw_info;
 609         struct i40iw_cqp_request *cqp_request;
 610         struct cqp_commands_info *cqp_info;
 611
 612         cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
 613         if (!cqp_request)
 614                 return I40IW_ERR_NO_MEMORY;
 615
 616         cqp_info = &cqp_request->info;
 617         hw_info = &cqp_request->info.in.u.qp_flush_wqes.info;
 618         memcpy(hw_info, info, sizeof(*hw_info));
 619
 620         cqp_info->cqp_cmd = OP_QP_FLUSH_WQES;
 621         cqp_info->post_sq = 1;
 622         cqp_info->in.u.qp_flush_wqes.qp = qp;
 623         cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request;
 624         status = i40iw_handle_cqp_op(iwdev, cqp_request);
 625         if (status)
 626                 i40iw_pr_err("CQP-OP Flush WQE's fail");
 627         return status;
 628 }
 629
 630 /**
 631  * i40iw_hw_manage_vf_pble_bp - manage vf pbles
 632  * @iwdev: iwarp device
 633  * @info: info for managing pble
 634  * @wait: flag wait for completion
 635  */
 636 enum i40iw_status_code i40iw_hw_manage_vf_pble_bp(struct i40iw_device *iwdev,
 637                                                   struct i40iw_manage_vf_pble_info *info,
 638                                                   bool wait)
 639 {
 640         enum i40iw_status_code status;
 641         struct i40iw_manage_vf_pble_info *hw_info;
 642         struct i40iw_cqp_request *cqp_request;
 643         struct cqp_commands_info *cqp_info;
 644
 645         if ((iwdev->init_state < CCQ_CREATED) && wait)
 646                 wait = false;
 647
 648         cqp_request = i40iw_get_cqp_request(&iwdev->cqp, wait);
 649         if (!cqp_request)
 650                 return I40IW_ERR_NO_MEMORY;
 651
 652         cqp_info = &cqp_request->info;
 653         hw_info = &cqp_request->info.in.u.manage_vf_pble_bp.info;
 654         memcpy(hw_info, info, sizeof(*hw_info));
 655
 656         cqp_info->cqp_cmd = OP_MANAGE_VF_PBLE_BP;
 657         cqp_info->post_sq = 1;
 658         cqp_info->in.u.manage_vf_pble_bp.cqp = &iwdev->cqp.sc_cqp;
 659         cqp_info->in.u.manage_vf_pble_bp.scratch = (uintptr_t)cqp_request;
 660         status = i40iw_handle_cqp_op(iwdev, cqp_request);
 661         if (status)
 662                 i40iw_pr_err("CQP-OP Manage VF pble_bp fail");
 663         return status;
 664 }
 665
 666 /**
 667  * i40iw_get_ib_wc - return change flush code to IB's
 668  * @opcode: iwarp flush code
 669  */
 670 static enum ib_wc_status i40iw_get_ib_wc(enum i40iw_flush_opcode opcode)
 671 {
 672         switch (opcode) {
 673         case FLUSH_PROT_ERR:
 674                 return IB_WC_LOC_PROT_ERR;
 675         case FLUSH_REM_ACCESS_ERR:
 676                 return IB_WC_REM_ACCESS_ERR;
 677         case FLUSH_LOC_QP_OP_ERR:
 678                 return IB_WC_LOC_QP_OP_ERR;
 679         case FLUSH_REM_OP_ERR:
 680                 return IB_WC_REM_OP_ERR;
 681         case FLUSH_LOC_LEN_ERR:
 682                 return IB_WC_LOC_LEN_ERR;
 683         case FLUSH_GENERAL_ERR:
 684                 return IB_WC_GENERAL_ERR;
 685         case FLUSH_FATAL_ERR:
 686         default:
 687                 return IB_WC_FATAL_ERR;
 688         }
 689 }
 690
 691 /**
 692  * i40iw_set_flush_info - set flush info
 693  * @pinfo: set flush info
 694  * @min: minor err
 695  * @maj: major err
 696  * @opcode: flush error code
 697  */
 698 static void i40iw_set_flush_info(struct i40iw_qp_flush_info *pinfo,
 699                                  u16 *min,
 700                                  u16 *maj,
 701                                  enum i40iw_flush_opcode opcode)
 702 {
 703         *min = (u16)i40iw_get_ib_wc(opcode);
 704         *maj = CQE_MAJOR_DRV;
 705         pinfo->userflushcode = true;
 706 }
 707
 708 /**
 709  * i40iw_flush_wqes - flush wqe for qp
 710  * @iwdev: iwarp device
 711  * @iwqp: qp to flush wqes
 712  */
 713 void i40iw_flush_wqes(struct i40iw_device *iwdev, struct i40iw_qp *iwqp)
 714 {
 715         struct i40iw_qp_flush_info info;
 716         struct i40iw_qp_flush_info *pinfo = &info;
 717
 718         struct i40iw_sc_qp *qp = &iwqp->sc_qp;
 719
 720         memset(pinfo, 0, sizeof(*pinfo));
 721         info.sq = true;
 722         info.rq = true;
 723         if (qp->term_flags) {
 724                 i40iw_set_flush_info(pinfo, &pinfo->sq_minor_code,
 725                                      &pinfo->sq_major_code, qp->flush_code);
 726                 i40iw_set_flush_info(pinfo, &pinfo->rq_minor_code,
 727                                      &pinfo->rq_major_code, qp->flush_code);
 728         }
 729         (void)i40iw_hw_flush_wqes(iwdev, &iwqp->sc_qp, &info, true);
 730 }