1 /*******************************************************************************
3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenFabrics.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 *******************************************************************************/
37 #include "i40iw_user.h"
38 #include "i40iw_hmc.h"
40 #include "i40iw_virtchnl.h"
42 struct i40iw_cqp_sq_wqe
{
43 u64 buf
[I40IW_CQP_WQE_SIZE
];
46 struct i40iw_sc_aeqe
{
47 u64 buf
[I40IW_AEQE_SIZE
];
51 u64 buf
[I40IW_CEQE_SIZE
];
54 struct i40iw_cqp_ctx
{
55 u64 buf
[I40IW_CQP_CTX_SIZE
];
58 struct i40iw_cq_shadow_area
{
59 u64 buf
[I40IW_SHADOW_AREA_SIZE
];
63 struct i40iw_hmc_info
;
64 struct i40iw_dev_pestat
;
71 struct i40iw_cqp_misc_ops
;
73 struct i40iw_priv_qp_ops
;
74 struct i40iw_priv_cq_ops
;
77 enum i40iw_resource_indicator_type
{
78 I40IW_RSRC_INDICATOR_TYPE_ADAPTER
= 0,
79 I40IW_RSRC_INDICATOR_TYPE_CQ
,
80 I40IW_RSRC_INDICATOR_TYPE_QP
,
81 I40IW_RSRC_INDICATOR_TYPE_SRQ
84 enum i40iw_hdrct_flags
{
90 enum i40iw_term_layers
{
96 enum i40iw_term_error_types
{
97 RDMAP_REMOTE_PROT
= 1,
100 DDP_TAGGED_BUFFER
= 1,
101 DDP_UNTAGGED_BUFFER
= 2,
105 enum i40iw_term_rdma_errors
{
106 RDMAP_INV_STAG
= 0x00,
107 RDMAP_INV_BOUNDS
= 0x01,
109 RDMAP_UNASSOC_STAG
= 0x03,
110 RDMAP_TO_WRAP
= 0x04,
111 RDMAP_INV_RDMAP_VER
= 0x05,
112 RDMAP_UNEXPECTED_OP
= 0x06,
113 RDMAP_CATASTROPHIC_LOCAL
= 0x07,
114 RDMAP_CATASTROPHIC_GLOBAL
= 0x08,
115 RDMAP_CANT_INV_STAG
= 0x09,
116 RDMAP_UNSPECIFIED
= 0xff
119 enum i40iw_term_ddp_errors
{
120 DDP_CATASTROPHIC_LOCAL
= 0x00,
121 DDP_TAGGED_INV_STAG
= 0x00,
122 DDP_TAGGED_BOUNDS
= 0x01,
123 DDP_TAGGED_UNASSOC_STAG
= 0x02,
124 DDP_TAGGED_TO_WRAP
= 0x03,
125 DDP_TAGGED_INV_DDP_VER
= 0x04,
126 DDP_UNTAGGED_INV_QN
= 0x01,
127 DDP_UNTAGGED_INV_MSN_NO_BUF
= 0x02,
128 DDP_UNTAGGED_INV_MSN_RANGE
= 0x03,
129 DDP_UNTAGGED_INV_MO
= 0x04,
130 DDP_UNTAGGED_INV_TOO_LONG
= 0x05,
131 DDP_UNTAGGED_INV_DDP_VER
= 0x06
134 enum i40iw_term_mpa_errors
{
141 enum i40iw_flush_opcode
{
144 FLUSH_REM_ACCESS_ERR
,
152 enum i40iw_term_eventtypes
{
154 TERM_EVENT_QP_ACCESS_ERR
157 struct i40iw_terminate_hdr
{
164 enum i40iw_debug_flag
{
165 I40IW_DEBUG_NONE
= 0x00000000,
166 I40IW_DEBUG_ERR
= 0x00000001,
167 I40IW_DEBUG_INIT
= 0x00000002,
168 I40IW_DEBUG_DEV
= 0x00000004,
169 I40IW_DEBUG_CM
= 0x00000008,
170 I40IW_DEBUG_VERBS
= 0x00000010,
171 I40IW_DEBUG_PUDA
= 0x00000020,
172 I40IW_DEBUG_ILQ
= 0x00000040,
173 I40IW_DEBUG_IEQ
= 0x00000080,
174 I40IW_DEBUG_QP
= 0x00000100,
175 I40IW_DEBUG_CQ
= 0x00000200,
176 I40IW_DEBUG_MR
= 0x00000400,
177 I40IW_DEBUG_PBLE
= 0x00000800,
178 I40IW_DEBUG_WQE
= 0x00001000,
179 I40IW_DEBUG_AEQ
= 0x00002000,
180 I40IW_DEBUG_CQP
= 0x00004000,
181 I40IW_DEBUG_HMC
= 0x00008000,
182 I40IW_DEBUG_USER
= 0x00010000,
183 I40IW_DEBUG_VIRT
= 0x00020000,
184 I40IW_DEBUG_DCB
= 0x00040000,
185 I40IW_DEBUG_CQE
= 0x00800000,
186 I40IW_DEBUG_ALL
= 0xFFFFFFFF
189 enum i40iw_hw_stat_index_32b
{
190 I40IW_HW_STAT_INDEX_IP4RXDISCARD
= 0,
191 I40IW_HW_STAT_INDEX_IP4RXTRUNC
,
192 I40IW_HW_STAT_INDEX_IP4TXNOROUTE
,
193 I40IW_HW_STAT_INDEX_IP6RXDISCARD
,
194 I40IW_HW_STAT_INDEX_IP6RXTRUNC
,
195 I40IW_HW_STAT_INDEX_IP6TXNOROUTE
,
196 I40IW_HW_STAT_INDEX_TCPRTXSEG
,
197 I40IW_HW_STAT_INDEX_TCPRXOPTERR
,
198 I40IW_HW_STAT_INDEX_TCPRXPROTOERR
,
199 I40IW_HW_STAT_INDEX_MAX_32
202 enum i40iw_hw_stat_index_64b
{
203 I40IW_HW_STAT_INDEX_IP4RXOCTS
= 0,
204 I40IW_HW_STAT_INDEX_IP4RXPKTS
,
205 I40IW_HW_STAT_INDEX_IP4RXFRAGS
,
206 I40IW_HW_STAT_INDEX_IP4RXMCPKTS
,
207 I40IW_HW_STAT_INDEX_IP4TXOCTS
,
208 I40IW_HW_STAT_INDEX_IP4TXPKTS
,
209 I40IW_HW_STAT_INDEX_IP4TXFRAGS
,
210 I40IW_HW_STAT_INDEX_IP4TXMCPKTS
,
211 I40IW_HW_STAT_INDEX_IP6RXOCTS
,
212 I40IW_HW_STAT_INDEX_IP6RXPKTS
,
213 I40IW_HW_STAT_INDEX_IP6RXFRAGS
,
214 I40IW_HW_STAT_INDEX_IP6RXMCPKTS
,
215 I40IW_HW_STAT_INDEX_IP6TXOCTS
,
216 I40IW_HW_STAT_INDEX_IP6TXPKTS
,
217 I40IW_HW_STAT_INDEX_IP6TXFRAGS
,
218 I40IW_HW_STAT_INDEX_IP6TXMCPKTS
,
219 I40IW_HW_STAT_INDEX_TCPRXSEGS
,
220 I40IW_HW_STAT_INDEX_TCPTXSEG
,
221 I40IW_HW_STAT_INDEX_RDMARXRDS
,
222 I40IW_HW_STAT_INDEX_RDMARXSNDS
,
223 I40IW_HW_STAT_INDEX_RDMARXWRS
,
224 I40IW_HW_STAT_INDEX_RDMATXRDS
,
225 I40IW_HW_STAT_INDEX_RDMATXSNDS
,
226 I40IW_HW_STAT_INDEX_RDMATXWRS
,
227 I40IW_HW_STAT_INDEX_RDMAVBND
,
228 I40IW_HW_STAT_INDEX_RDMAVINV
,
229 I40IW_HW_STAT_INDEX_MAX_64
232 struct i40iw_dev_hw_stat_offsets
{
233 u32 stat_offset_32
[I40IW_HW_STAT_INDEX_MAX_32
];
234 u32 stat_offset_64
[I40IW_HW_STAT_INDEX_MAX_64
];
237 struct i40iw_dev_hw_stats
{
238 u64 stat_value_32
[I40IW_HW_STAT_INDEX_MAX_32
];
239 u64 stat_value_64
[I40IW_HW_STAT_INDEX_MAX_64
];
242 struct i40iw_device_pestat_ops
{
243 void (*iw_hw_stat_init
)(struct i40iw_dev_pestat
*, u8
, struct i40iw_hw
*, bool);
244 void (*iw_hw_stat_read_32
)(struct i40iw_dev_pestat
*, enum i40iw_hw_stat_index_32b
, u64
*);
245 void (*iw_hw_stat_read_64
)(struct i40iw_dev_pestat
*, enum i40iw_hw_stat_index_64b
, u64
*);
246 void (*iw_hw_stat_read_all
)(struct i40iw_dev_pestat
*, struct i40iw_dev_hw_stats
*);
247 void (*iw_hw_stat_refresh_all
)(struct i40iw_dev_pestat
*);
250 struct i40iw_dev_pestat
{
252 struct i40iw_device_pestat_ops ops
;
253 struct i40iw_dev_hw_stats hw_stats
;
254 struct i40iw_dev_hw_stats last_read_hw_stats
;
255 struct i40iw_dev_hw_stat_offsets hw_stat_offsets
;
256 struct timer_list stats_timer
;
257 spinlock_t stats_lock
; /* rdma stats lock */
263 struct i40iw_hmc_info hmc
;
267 struct list_head rxlist
;
285 struct i40iw_sc_dev
*dev
;
289 struct i40iw_cqp_quanta
{
290 u64 elem
[I40IW_CQP_WQE_SIZE
];
293 struct i40iw_sc_cqp
{
298 struct i40iw_sc_dev
*dev
;
299 enum i40iw_status_code (*process_cqp_sds
)(struct i40iw_sc_dev
*,
300 struct i40iw_update_sds_info
*);
301 struct i40iw_dma_mem sdbuf
;
302 struct i40iw_ring sq_ring
;
303 struct i40iw_cqp_quanta
*sq_base
;
311 bool en_datacenter_tcp
;
317 struct i40iw_sc_aeq
{
320 struct i40iw_sc_dev
*dev
;
321 struct i40iw_sc_aeqe
*aeqe_base
;
324 struct i40iw_ring aeq_ring
;
327 u32 first_pm_pbl_idx
;
331 struct i40iw_sc_ceq
{
334 struct i40iw_sc_dev
*dev
;
335 struct i40iw_ceqe
*ceqe_base
;
339 struct i40iw_ring ceq_ring
;
344 u32 first_pm_pbl_idx
;
349 struct i40iw_cq_uk cq_uk
;
352 struct i40iw_sc_dev
*dev
;
356 u32 shadow_read_threshold
;
364 u32 first_pm_pbl_idx
;
369 struct i40iw_qp_uk qp_uk
;
375 struct i40iw_sc_dev
*dev
;
376 struct i40iw_sc_pd
*pd
;
378 void *llp_stream_handle
;
380 struct i40iw_pfpdu pfpdu
;
384 u16 exception_lan_queue
;
401 enum i40iw_flush_opcode flush_code
;
402 enum i40iw_term_eventtypes eventtype
;
406 struct i40iw_hmc_fpm_misc
{
415 struct i40iw_vchnl_if
{
416 enum i40iw_status_code (*vchnl_recv
)(struct i40iw_sc_dev
*, u32
, u8
*, u16
);
417 enum i40iw_status_code (*vchnl_send
)(struct i40iw_sc_dev
*dev
, u32
, u8
*, u16
);
420 #define I40IW_VCHNL_MAX_VF_MSG_SIZE 512
422 struct i40iw_vchnl_vf_msg_buffer
{
423 struct i40iw_virtchnl_op_buf vchnl_msg
;
424 char parm_buffer
[I40IW_VCHNL_MAX_VF_MSG_SIZE
- 1];
428 struct i40iw_sc_dev
*pf_dev
;
430 struct i40iw_dev_pestat dev_pestat
;
431 struct i40iw_hmc_pble_info
*pble_info
;
432 struct i40iw_hmc_info hmc_info
;
433 struct i40iw_vchnl_vf_msg_buffer vf_msg_buffer
;
434 u64 fpm_query_buf_pa
;
438 bool pf_hmc_initialized
;
440 u16 iw_vf_idx
; /* VF Device table index */
441 bool stats_initialized
;
444 struct i40iw_sc_dev
{
445 struct list_head cqp_cmd_head
; /* head of the CQP command list */
446 spinlock_t cqp_lock
; /* cqp list sync */
447 struct i40iw_dev_uk dev_uk
;
448 struct i40iw_dev_pestat dev_pestat
;
449 struct i40iw_dma_mem vf_fpm_query_buf
[I40IW_MAX_PE_ENABLED_VF_COUNT
];
450 u64 fpm_query_buf_pa
;
451 u64 fpm_commit_buf_pa
;
457 struct i40iw_hmc_info
*hmc_info
;
458 struct i40iw_hmc_pble_info
*pble_info
;
459 struct i40iw_vfdev
*vf_dev
[I40IW_MAX_PE_ENABLED_VF_COUNT
];
460 struct i40iw_sc_cqp
*cqp
;
461 struct i40iw_sc_aeq
*aeq
;
462 struct i40iw_sc_ceq
*ceq
[I40IW_CEQ_MAX_COUNT
];
463 struct i40iw_sc_cq
*ccq
;
464 struct i40iw_cqp_ops
*cqp_ops
;
465 struct i40iw_ccq_ops
*ccq_ops
;
466 struct i40iw_ceq_ops
*ceq_ops
;
467 struct i40iw_aeq_ops
*aeq_ops
;
468 struct i40iw_pd_ops
*iw_pd_ops
;
469 struct i40iw_priv_qp_ops
*iw_priv_qp_ops
;
470 struct i40iw_priv_cq_ops
*iw_priv_cq_ops
;
471 struct i40iw_mr_ops
*mr_ops
;
472 struct i40iw_cqp_misc_ops
*cqp_misc_ops
;
473 struct i40iw_hmc_ops
*hmc_ops
;
474 struct i40iw_vchnl_if vchnl_if
;
476 struct i40iw_virt_mem ilq_mem
;
477 struct i40iw_puda_rsrc
*ilq
;
479 struct i40iw_virt_mem ieq_mem
;
480 struct i40iw_puda_rsrc
*ieq
;
482 struct i40iw_vf_cqp_ops
*iw_vf_cqp_ops
;
484 struct i40iw_hmc_fpm_misc hmc_fpm_misc
;
487 u16 exception_lan_queue
;
492 wait_queue_head_t vf_reqs
;
493 u64 cqp_cmd_stats
[OP_SIZE_CQP_STAT_ARRAY
];
494 struct i40iw_vchnl_vf_msg_buffer vchnl_vf_msg_buf
;
498 struct i40iw_modify_cq_info
{
500 struct i40iw_cqe
*cq_base
;
504 u32 shadow_read_threshold
;
510 bool check_overflow_change
;
511 u32 first_pm_pbl_idx
;
515 struct i40iw_create_qp_info
{
521 bool arp_cache_idx_valid
;
524 struct i40iw_modify_qp_info
{
534 bool arp_cache_idx_valid
;
536 bool remove_hash_idx
;
539 bool cached_var_valid
;
544 struct i40iw_ccq_cqe_info
{
545 struct i40iw_sc_cqp
*cqp
;
554 struct i40iw_l2params
{
555 u16 qs_handle_list
[I40IW_MAX_USER_PRIORITY
];
559 struct i40iw_device_init_info
{
560 u64 fpm_query_buf_pa
;
561 u64 fpm_commit_buf_pa
;
566 enum i40iw_status_code (*vchnl_send
)(struct i40iw_sc_dev
*, u32
, u8
*, u16
);
568 u16 exception_lan_queue
;
574 enum i40iw_cqp_hmc_profile
{
575 I40IW_HMC_PROFILE_DEFAULT
= 1,
576 I40IW_HMC_PROFILE_FAVOR_VF
= 2,
577 I40IW_HMC_PROFILE_EQUAL
= 3,
580 struct i40iw_cqp_init_info
{
584 struct i40iw_sc_dev
*dev
;
585 struct i40iw_cqp_quanta
*sq
;
590 bool en_datacenter_tcp
;
595 struct i40iw_ceq_init_info
{
597 struct i40iw_sc_dev
*dev
;
606 u32 first_pm_pbl_idx
;
609 struct i40iw_aeq_init_info
{
611 struct i40iw_sc_dev
*dev
;
617 u32 first_pm_pbl_idx
;
620 struct i40iw_ccq_init_info
{
623 struct i40iw_sc_dev
*dev
;
624 struct i40iw_cqe
*cq_base
;
629 u32 shadow_read_threshold
;
634 bool avoid_mem_cflct
;
637 u32 first_pm_pbl_idx
;
640 struct i40iwarp_offload_info
{
663 struct i40iw_tcp_offload_info
{
666 bool insert_vlan_tag
;
673 bool avoid_stretch_ack
;
689 u32 time_stamp_recent
;
710 bool ignore_tcp_uns_opt
;
713 struct i40iw_qp_host_ctx_info
{
715 struct i40iw_tcp_offload_info
*tcp_info
;
716 struct i40iwarp_offload_info
*iwarp_info
;
722 bool iwarp_info_valid
;
723 bool err_rq_idx_valid
;
727 struct i40iw_aeqe_info
{
743 struct i40iw_allocate_stag_info
{
751 bool use_hmc_fcn_index
;
756 struct i40iw_reg_ns_stag_info
{
763 u32 first_pm_pbl_index
;
764 enum i40iw_addressing_type addr_type
;
765 i40iw_stag_index stag_idx
;
768 i40iw_stag_key stag_key
;
769 bool use_hmc_fcn_index
;
774 struct i40iw_fast_reg_stag_info
{
782 u32 first_pm_pbl_index
;
783 enum i40iw_addressing_type addr_type
;
784 i40iw_stag_index stag_idx
;
787 i40iw_stag_key stag_key
;
791 bool use_hmc_fcn_index
;
797 struct i40iw_dealloc_stag_info
{
804 struct i40iw_register_shared_stag
{
806 enum i40iw_addressing_type addr_type
;
807 i40iw_stag_index new_stag_idx
;
808 i40iw_stag_index parent_stag_idx
;
811 i40iw_stag_key new_stag_key
;
814 struct i40iw_qp_init_info
{
815 struct i40iw_qp_uk_init_info qp_uk_init_info
;
816 struct i40iw_sc_pd
*pd
;
834 struct i40iw_cq_init_info
{
835 struct i40iw_sc_dev
*dev
;
839 u32 shadow_read_threshold
;
843 u32 first_pm_pbl_idx
;
848 struct i40iw_cq_uk_init_info cq_uk_init_info
;
851 struct i40iw_upload_context_info
{
859 struct i40iw_add_arp_cache_entry_info
{
866 struct i40iw_apbvt_info
{
871 enum i40iw_quad_entry_type
{
872 I40IW_QHASH_TYPE_TCP_ESTABLISHED
= 1,
873 I40IW_QHASH_TYPE_TCP_SYN
,
876 enum i40iw_quad_hash_manage_type
{
877 I40IW_QHASH_MANAGE_TYPE_DELETE
= 0,
878 I40IW_QHASH_MANAGE_TYPE_ADD
,
879 I40IW_QHASH_MANAGE_TYPE_MODIFY
882 struct i40iw_qhash_table_info
{
883 enum i40iw_quad_hash_manage_type manage
;
884 enum i40iw_quad_entry_type entry_type
;
897 struct i40iw_local_mac_ipaddr_entry_info
{
902 struct i40iw_cqp_manage_push_page_info
{
908 struct i40iw_qp_flush_info
{
921 struct i40iw_cqp_commit_fpm_values
{
926 u32 apbvt_inuse_base
;
950 struct i40iw_cqp_query_fpm_values
{
951 u16 first_pe_sd_index
;
976 struct i40iw_cqp_ops
{
977 enum i40iw_status_code (*cqp_init
)(struct i40iw_sc_cqp
*,
978 struct i40iw_cqp_init_info
*);
979 enum i40iw_status_code (*cqp_create
)(struct i40iw_sc_cqp
*, bool, u16
*, u16
*);
980 void (*cqp_post_sq
)(struct i40iw_sc_cqp
*);
981 u64
*(*cqp_get_next_send_wqe
)(struct i40iw_sc_cqp
*, u64 scratch
);
982 enum i40iw_status_code (*cqp_destroy
)(struct i40iw_sc_cqp
*);
983 enum i40iw_status_code (*poll_for_cqp_op_done
)(struct i40iw_sc_cqp
*, u8
,
984 struct i40iw_ccq_cqe_info
*);
987 struct i40iw_ccq_ops
{
988 enum i40iw_status_code (*ccq_init
)(struct i40iw_sc_cq
*,
989 struct i40iw_ccq_init_info
*);
990 enum i40iw_status_code (*ccq_create
)(struct i40iw_sc_cq
*, u64
, bool, bool);
991 enum i40iw_status_code (*ccq_destroy
)(struct i40iw_sc_cq
*, u64
, bool);
992 enum i40iw_status_code (*ccq_create_done
)(struct i40iw_sc_cq
*);
993 enum i40iw_status_code (*ccq_get_cqe_info
)(struct i40iw_sc_cq
*,
994 struct i40iw_ccq_cqe_info
*);
995 void (*ccq_arm
)(struct i40iw_sc_cq
*);
998 struct i40iw_ceq_ops
{
999 enum i40iw_status_code (*ceq_init
)(struct i40iw_sc_ceq
*,
1000 struct i40iw_ceq_init_info
*);
1001 enum i40iw_status_code (*ceq_create
)(struct i40iw_sc_ceq
*, u64
, bool);
1002 enum i40iw_status_code (*cceq_create_done
)(struct i40iw_sc_ceq
*);
1003 enum i40iw_status_code (*cceq_destroy_done
)(struct i40iw_sc_ceq
*);
1004 enum i40iw_status_code (*cceq_create
)(struct i40iw_sc_ceq
*, u64
);
1005 enum i40iw_status_code (*ceq_destroy
)(struct i40iw_sc_ceq
*, u64
, bool);
1006 void *(*process_ceq
)(struct i40iw_sc_dev
*, struct i40iw_sc_ceq
*);
1009 struct i40iw_aeq_ops
{
1010 enum i40iw_status_code (*aeq_init
)(struct i40iw_sc_aeq
*,
1011 struct i40iw_aeq_init_info
*);
1012 enum i40iw_status_code (*aeq_create
)(struct i40iw_sc_aeq
*, u64
, bool);
1013 enum i40iw_status_code (*aeq_destroy
)(struct i40iw_sc_aeq
*, u64
, bool);
1014 enum i40iw_status_code (*get_next_aeqe
)(struct i40iw_sc_aeq
*,
1015 struct i40iw_aeqe_info
*);
1016 enum i40iw_status_code (*repost_aeq_entries
)(struct i40iw_sc_dev
*, u32
);
1017 enum i40iw_status_code (*aeq_create_done
)(struct i40iw_sc_aeq
*);
1018 enum i40iw_status_code (*aeq_destroy_done
)(struct i40iw_sc_aeq
*);
1021 struct i40iw_pd_ops
{
1022 void (*pd_init
)(struct i40iw_sc_dev
*, struct i40iw_sc_pd
*, u16
);
1025 struct i40iw_priv_qp_ops
{
1026 enum i40iw_status_code (*qp_init
)(struct i40iw_sc_qp
*, struct i40iw_qp_init_info
*);
1027 enum i40iw_status_code (*qp_create
)(struct i40iw_sc_qp
*,
1028 struct i40iw_create_qp_info
*, u64
, bool);
1029 enum i40iw_status_code (*qp_modify
)(struct i40iw_sc_qp
*,
1030 struct i40iw_modify_qp_info
*, u64
, bool);
1031 enum i40iw_status_code (*qp_destroy
)(struct i40iw_sc_qp
*, u64
, bool, bool, bool);
1032 enum i40iw_status_code (*qp_flush_wqes
)(struct i40iw_sc_qp
*,
1033 struct i40iw_qp_flush_info
*, u64
, bool);
1034 enum i40iw_status_code (*qp_upload_context
)(struct i40iw_sc_dev
*,
1035 struct i40iw_upload_context_info
*,
1037 enum i40iw_status_code (*qp_setctx
)(struct i40iw_sc_qp
*, u64
*,
1038 struct i40iw_qp_host_ctx_info
*);
1040 void (*qp_send_lsmm
)(struct i40iw_sc_qp
*, void *, u32
, i40iw_stag
);
1041 void (*qp_send_lsmm_nostag
)(struct i40iw_sc_qp
*, void *, u32
);
1042 void (*qp_send_rtt
)(struct i40iw_sc_qp
*, bool);
1043 enum i40iw_status_code (*qp_post_wqe0
)(struct i40iw_sc_qp
*, u8
);
1044 enum i40iw_status_code (*iw_mr_fast_register
)(struct i40iw_sc_qp
*,
1045 struct i40iw_fast_reg_stag_info
*,
1049 struct i40iw_priv_cq_ops
{
1050 enum i40iw_status_code (*cq_init
)(struct i40iw_sc_cq
*, struct i40iw_cq_init_info
*);
1051 enum i40iw_status_code (*cq_create
)(struct i40iw_sc_cq
*, u64
, bool, bool);
1052 enum i40iw_status_code (*cq_destroy
)(struct i40iw_sc_cq
*, u64
, bool);
1053 enum i40iw_status_code (*cq_modify
)(struct i40iw_sc_cq
*,
1054 struct i40iw_modify_cq_info
*, u64
, bool);
1057 struct i40iw_mr_ops
{
1058 enum i40iw_status_code (*alloc_stag
)(struct i40iw_sc_dev
*,
1059 struct i40iw_allocate_stag_info
*, u64
, bool);
1060 enum i40iw_status_code (*mr_reg_non_shared
)(struct i40iw_sc_dev
*,
1061 struct i40iw_reg_ns_stag_info
*,
1063 enum i40iw_status_code (*mr_reg_shared
)(struct i40iw_sc_dev
*,
1064 struct i40iw_register_shared_stag
*,
1066 enum i40iw_status_code (*dealloc_stag
)(struct i40iw_sc_dev
*,
1067 struct i40iw_dealloc_stag_info
*,
1069 enum i40iw_status_code (*query_stag
)(struct i40iw_sc_dev
*, u64
, u32
, bool);
1070 enum i40iw_status_code (*mw_alloc
)(struct i40iw_sc_dev
*, u64
, u32
, u16
, bool);
1073 struct i40iw_cqp_misc_ops
{
1074 enum i40iw_status_code (*manage_push_page
)(struct i40iw_sc_cqp
*,
1075 struct i40iw_cqp_manage_push_page_info
*,
1077 enum i40iw_status_code (*manage_hmc_pm_func_table
)(struct i40iw_sc_cqp
*,
1078 u64
, u8
, bool, bool);
1079 enum i40iw_status_code (*set_hmc_resource_profile
)(struct i40iw_sc_cqp
*,
1080 u64
, u8
, u8
, bool, bool);
1081 enum i40iw_status_code (*commit_fpm_values
)(struct i40iw_sc_cqp
*, u64
, u8
,
1082 struct i40iw_dma_mem
*, bool, u8
);
1083 enum i40iw_status_code (*query_fpm_values
)(struct i40iw_sc_cqp
*, u64
, u8
,
1084 struct i40iw_dma_mem
*, bool, u8
);
1085 enum i40iw_status_code (*static_hmc_pages_allocated
)(struct i40iw_sc_cqp
*,
1086 u64
, u8
, bool, bool);
1087 enum i40iw_status_code (*add_arp_cache_entry
)(struct i40iw_sc_cqp
*,
1088 struct i40iw_add_arp_cache_entry_info
*,
1090 enum i40iw_status_code (*del_arp_cache_entry
)(struct i40iw_sc_cqp
*, u64
, u16
, bool);
1091 enum i40iw_status_code (*query_arp_cache_entry
)(struct i40iw_sc_cqp
*, u64
, u16
, bool);
1092 enum i40iw_status_code (*manage_apbvt_entry
)(struct i40iw_sc_cqp
*,
1093 struct i40iw_apbvt_info
*, u64
, bool);
1094 enum i40iw_status_code (*manage_qhash_table_entry
)(struct i40iw_sc_cqp
*,
1095 struct i40iw_qhash_table_info
*, u64
, bool);
1096 enum i40iw_status_code (*alloc_local_mac_ipaddr_table_entry
)(struct i40iw_sc_cqp
*, u64
, bool);
1097 enum i40iw_status_code (*add_local_mac_ipaddr_entry
)(struct i40iw_sc_cqp
*,
1098 struct i40iw_local_mac_ipaddr_entry_info
*,
1100 enum i40iw_status_code (*del_local_mac_ipaddr_entry
)(struct i40iw_sc_cqp
*, u64
, u8
, u8
, bool);
1101 enum i40iw_status_code (*cqp_nop
)(struct i40iw_sc_cqp
*, u64
, bool);
1102 enum i40iw_status_code (*commit_fpm_values_done
)(struct i40iw_sc_cqp
1104 enum i40iw_status_code (*query_fpm_values_done
)(struct i40iw_sc_cqp
*);
1105 enum i40iw_status_code (*manage_hmc_pm_func_table_done
)(struct i40iw_sc_cqp
*);
1106 enum i40iw_status_code (*update_suspend_qp
)(struct i40iw_sc_cqp
*, struct i40iw_sc_qp
*, u64
);
1107 enum i40iw_status_code (*update_resume_qp
)(struct i40iw_sc_cqp
*, struct i40iw_sc_qp
*, u64
);
1110 struct i40iw_hmc_ops
{
1111 enum i40iw_status_code (*init_iw_hmc
)(struct i40iw_sc_dev
*, u8
);
1112 enum i40iw_status_code (*parse_fpm_query_buf
)(u64
*, struct i40iw_hmc_info
*,
1113 struct i40iw_hmc_fpm_misc
*);
1114 enum i40iw_status_code (*configure_iw_fpm
)(struct i40iw_sc_dev
*, u8
);
1115 enum i40iw_status_code (*parse_fpm_commit_buf
)(u64
*, struct i40iw_hmc_obj_info
*);
1116 enum i40iw_status_code (*create_hmc_object
)(struct i40iw_sc_dev
*dev
,
1117 struct i40iw_hmc_create_obj_info
*);
1118 enum i40iw_status_code (*del_hmc_object
)(struct i40iw_sc_dev
*dev
,
1119 struct i40iw_hmc_del_obj_info
*,
1121 enum i40iw_status_code (*pf_init_vfhmc
)(struct i40iw_sc_dev
*, u8
, u32
*);
1122 enum i40iw_status_code (*vf_configure_vffpm
)(struct i40iw_sc_dev
*, u32
*);
1128 struct i40iw_sc_qp
*qp
;
1129 struct i40iw_create_qp_info info
;
1134 struct i40iw_sc_qp
*qp
;
1135 struct i40iw_modify_qp_info info
;
1140 struct i40iw_sc_qp
*qp
;
1142 bool remove_hash_idx
;
1147 struct i40iw_sc_cq
*cq
;
1149 bool check_overflow
;
1153 struct i40iw_sc_cq
*cq
;
1158 struct i40iw_sc_dev
*dev
;
1159 struct i40iw_allocate_stag_info info
;
1164 struct i40iw_sc_dev
*dev
;
1171 struct i40iw_sc_dev
*dev
;
1172 struct i40iw_reg_ns_stag_info info
;
1174 } mr_reg_non_shared
;
1177 struct i40iw_sc_dev
*dev
;
1178 struct i40iw_dealloc_stag_info info
;
1183 struct i40iw_sc_cqp
*cqp
;
1184 struct i40iw_local_mac_ipaddr_entry_info info
;
1186 } add_local_mac_ipaddr_entry
;
1189 struct i40iw_sc_cqp
*cqp
;
1190 struct i40iw_add_arp_cache_entry_info info
;
1192 } add_arp_cache_entry
;
1195 struct i40iw_sc_cqp
*cqp
;
1198 u8 ignore_ref_count
;
1199 } del_local_mac_ipaddr_entry
;
1202 struct i40iw_sc_cqp
*cqp
;
1205 } del_arp_cache_entry
;
1208 struct i40iw_sc_cqp
*cqp
;
1209 struct i40iw_manage_vf_pble_info info
;
1211 } manage_vf_pble_bp
;
1214 struct i40iw_sc_cqp
*cqp
;
1215 struct i40iw_cqp_manage_push_page_info info
;
1220 struct i40iw_sc_dev
*dev
;
1221 struct i40iw_upload_context_info info
;
1223 } qp_upload_context
;
1226 struct i40iw_sc_cqp
*cqp
;
1228 } alloc_local_mac_ipaddr_entry
;
1231 struct i40iw_sc_dev
*dev
;
1232 struct i40iw_hmc_fcn_info info
;
1237 struct i40iw_sc_ceq
*ceq
;
1242 struct i40iw_sc_ceq
*ceq
;
1247 struct i40iw_sc_aeq
*aeq
;
1252 struct i40iw_sc_aeq
*aeq
;
1257 struct i40iw_sc_qp
*qp
;
1258 struct i40iw_qp_flush_info info
;
1263 struct i40iw_sc_cqp
*cqp
;
1264 void *fpm_values_va
;
1271 struct i40iw_sc_cqp
*cqp
;
1272 void *fpm_values_va
;
1276 } commit_fpm_values
;
1279 struct i40iw_sc_cqp
*cqp
;
1280 struct i40iw_apbvt_info info
;
1282 } manage_apbvt_entry
;
1285 struct i40iw_sc_cqp
*cqp
;
1286 struct i40iw_qhash_table_info info
;
1288 } manage_qhash_table_entry
;
1291 struct i40iw_sc_dev
*dev
;
1292 struct i40iw_update_sds_info info
;
1297 struct i40iw_sc_cqp
*cqp
;
1298 struct i40iw_sc_qp
*qp
;
1304 struct cqp_commands_info
{
1305 struct list_head cqp_cmd_entry
;
1311 struct i40iw_virtchnl_work_info
{
1312 void (*callback_fcn
)(void *vf_dev
);
1313 void *worker_vf_dev
;