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Fix typos in comments
[deliverable/linux.git] / drivers / infiniband / hw / ipath / ipath_iba6120.c
1 /*
2 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 /*
34 * This file contains all of the code that is specific to the
35 * InfiniPath PCIe chip.
36 */
37
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <rdma/ib_verbs.h>
42
43 #include "ipath_kernel.h"
44 #include "ipath_registers.h"
45
46 static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
47
48 /*
49 * This file contains all the chip-specific register information and
50 * access functions for the QLogic InfiniPath PCI-Express chip.
51 *
52 * This lists the InfiniPath registers, in the actual chip layout.
53 * This structure should never be directly accessed.
54 */
55 struct _infinipath_do_not_use_kernel_regs {
56 unsigned long long Revision;
57 unsigned long long Control;
58 unsigned long long PageAlign;
59 unsigned long long PortCnt;
60 unsigned long long DebugPortSelect;
61 unsigned long long Reserved0;
62 unsigned long long SendRegBase;
63 unsigned long long UserRegBase;
64 unsigned long long CounterRegBase;
65 unsigned long long Scratch;
66 unsigned long long Reserved1;
67 unsigned long long Reserved2;
68 unsigned long long IntBlocked;
69 unsigned long long IntMask;
70 unsigned long long IntStatus;
71 unsigned long long IntClear;
72 unsigned long long ErrorMask;
73 unsigned long long ErrorStatus;
74 unsigned long long ErrorClear;
75 unsigned long long HwErrMask;
76 unsigned long long HwErrStatus;
77 unsigned long long HwErrClear;
78 unsigned long long HwDiagCtrl;
79 unsigned long long MDIO;
80 unsigned long long IBCStatus;
81 unsigned long long IBCCtrl;
82 unsigned long long ExtStatus;
83 unsigned long long ExtCtrl;
84 unsigned long long GPIOOut;
85 unsigned long long GPIOMask;
86 unsigned long long GPIOStatus;
87 unsigned long long GPIOClear;
88 unsigned long long RcvCtrl;
89 unsigned long long RcvBTHQP;
90 unsigned long long RcvHdrSize;
91 unsigned long long RcvHdrCnt;
92 unsigned long long RcvHdrEntSize;
93 unsigned long long RcvTIDBase;
94 unsigned long long RcvTIDCnt;
95 unsigned long long RcvEgrBase;
96 unsigned long long RcvEgrCnt;
97 unsigned long long RcvBufBase;
98 unsigned long long RcvBufSize;
99 unsigned long long RxIntMemBase;
100 unsigned long long RxIntMemSize;
101 unsigned long long RcvPartitionKey;
102 unsigned long long Reserved3;
103 unsigned long long RcvPktLEDCnt;
104 unsigned long long Reserved4[8];
105 unsigned long long SendCtrl;
106 unsigned long long SendPIOBufBase;
107 unsigned long long SendPIOSize;
108 unsigned long long SendPIOBufCnt;
109 unsigned long long SendPIOAvailAddr;
110 unsigned long long TxIntMemBase;
111 unsigned long long TxIntMemSize;
112 unsigned long long Reserved5;
113 unsigned long long PCIeRBufTestReg0;
114 unsigned long long PCIeRBufTestReg1;
115 unsigned long long Reserved51[6];
116 unsigned long long SendBufferError;
117 unsigned long long SendBufferErrorCONT1;
118 unsigned long long Reserved6SBE[6];
119 unsigned long long RcvHdrAddr0;
120 unsigned long long RcvHdrAddr1;
121 unsigned long long RcvHdrAddr2;
122 unsigned long long RcvHdrAddr3;
123 unsigned long long RcvHdrAddr4;
124 unsigned long long Reserved7RHA[11];
125 unsigned long long RcvHdrTailAddr0;
126 unsigned long long RcvHdrTailAddr1;
127 unsigned long long RcvHdrTailAddr2;
128 unsigned long long RcvHdrTailAddr3;
129 unsigned long long RcvHdrTailAddr4;
130 unsigned long long Reserved8RHTA[11];
131 unsigned long long Reserved9SW[8];
132 unsigned long long SerdesConfig0;
133 unsigned long long SerdesConfig1;
134 unsigned long long SerdesStatus;
135 unsigned long long XGXSConfig;
136 unsigned long long IBPLLCfg;
137 unsigned long long Reserved10SW2[3];
138 unsigned long long PCIEQ0SerdesConfig0;
139 unsigned long long PCIEQ0SerdesConfig1;
140 unsigned long long PCIEQ0SerdesStatus;
141 unsigned long long Reserved11;
142 unsigned long long PCIEQ1SerdesConfig0;
143 unsigned long long PCIEQ1SerdesConfig1;
144 unsigned long long PCIEQ1SerdesStatus;
145 unsigned long long Reserved12;
146 };
147
148 struct _infinipath_do_not_use_counters {
149 __u64 LBIntCnt;
150 __u64 LBFlowStallCnt;
151 __u64 Reserved1;
152 __u64 TxUnsupVLErrCnt;
153 __u64 TxDataPktCnt;
154 __u64 TxFlowPktCnt;
155 __u64 TxDwordCnt;
156 __u64 TxLenErrCnt;
157 __u64 TxMaxMinLenErrCnt;
158 __u64 TxUnderrunCnt;
159 __u64 TxFlowStallCnt;
160 __u64 TxDroppedPktCnt;
161 __u64 RxDroppedPktCnt;
162 __u64 RxDataPktCnt;
163 __u64 RxFlowPktCnt;
164 __u64 RxDwordCnt;
165 __u64 RxLenErrCnt;
166 __u64 RxMaxMinLenErrCnt;
167 __u64 RxICRCErrCnt;
168 __u64 RxVCRCErrCnt;
169 __u64 RxFlowCtrlErrCnt;
170 __u64 RxBadFormatCnt;
171 __u64 RxLinkProblemCnt;
172 __u64 RxEBPCnt;
173 __u64 RxLPCRCErrCnt;
174 __u64 RxBufOvflCnt;
175 __u64 RxTIDFullErrCnt;
176 __u64 RxTIDValidErrCnt;
177 __u64 RxPKeyMismatchCnt;
178 __u64 RxP0HdrEgrOvflCnt;
179 __u64 RxP1HdrEgrOvflCnt;
180 __u64 RxP2HdrEgrOvflCnt;
181 __u64 RxP3HdrEgrOvflCnt;
182 __u64 RxP4HdrEgrOvflCnt;
183 __u64 RxP5HdrEgrOvflCnt;
184 __u64 RxP6HdrEgrOvflCnt;
185 __u64 RxP7HdrEgrOvflCnt;
186 __u64 RxP8HdrEgrOvflCnt;
187 __u64 Reserved6;
188 __u64 Reserved7;
189 __u64 IBStatusChangeCnt;
190 __u64 IBLinkErrRecoveryCnt;
191 __u64 IBLinkDownedCnt;
192 __u64 IBSymbolErrCnt;
193 };
194
195 #define IPATH_KREG_OFFSET(field) (offsetof( \
196 struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
197 #define IPATH_CREG_OFFSET(field) (offsetof( \
198 struct _infinipath_do_not_use_counters, field) / sizeof(u64))
199
200 static const struct ipath_kregs ipath_pe_kregs = {
201 .kr_control = IPATH_KREG_OFFSET(Control),
202 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
203 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
204 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
205 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
206 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
207 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
208 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
209 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
210 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
211 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
212 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
213 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
214 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
215 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
216 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
217 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
218 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
219 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
220 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
221 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
222 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
223 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
224 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
225 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
226 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
227 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
228 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
229 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
230 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
231 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
232 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
233 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
234 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
235 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
236 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
237 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
238 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
239 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
240 .kr_revision = IPATH_KREG_OFFSET(Revision),
241 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
242 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
243 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
244 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
245 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
246 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
247 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
248 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
249 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
250 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
251 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
252 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
253 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
254 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
255 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
256 .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
257
258 /*
259 * These should not be used directly via ipath_write_kreg64(),
260 * use them with ipath_write_kreg64_port(),
261 */
262 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
263 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
264
265 /* The rcvpktled register controls one of the debug port signals, so
266 * a packet activity LED can be connected to it. */
267 .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
268 .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
269 .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
270 .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
271 .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
272 .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
273 .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
274 .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
275 .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
276 };
277
278 static const struct ipath_cregs ipath_pe_cregs = {
279 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
280 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
281 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
282 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
283 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
284 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
285 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
286 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
287 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
288 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
289 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
290 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
291 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
292 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
293 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
294 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
295 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
296 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
297 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
298 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
299 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
300 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
301 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
302 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
303 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
304 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
305 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
306 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
307 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
308 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
309 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
310 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
311 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
312 };
313
314 /* kr_control bits */
315 #define INFINIPATH_C_RESET 1U
316
317 /* kr_intstatus, kr_intclear, kr_intmask bits */
318 #define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
319 #define INFINIPATH_I_RCVURG_SHIFT 0
320 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
321 #define INFINIPATH_I_RCVAVAIL_SHIFT 12
322
323 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
324 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
325 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
326 #define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
327 #define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
328 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
329 #define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
330 #define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
331 #define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
332 #define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
333 #define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
334 #define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
335 #define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL
336
337 #define IBA6120_IBCS_LINKTRAININGSTATE_MASK 0xf
338 #define IBA6120_IBCS_LINKSTATE_SHIFT 4
339
340 /* kr_extstatus bits */
341 #define INFINIPATH_EXTS_FREQSEL 0x2
342 #define INFINIPATH_EXTS_SERDESSEL 0x4
343 #define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
344 #define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000
345
346 /* kr_xgxsconfig bits */
347 #define INFINIPATH_XGXS_RESET 0x5ULL
348
349 #define _IPATH_GPIO_SDA_NUM 1
350 #define _IPATH_GPIO_SCL_NUM 0
351
352 #define IPATH_GPIO_SDA (1ULL << \
353 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
354 #define IPATH_GPIO_SCL (1ULL << \
355 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
356
357 #define INFINIPATH_RT_BUFSIZE_MASK 0xe0000000ULL
358 #define INFINIPATH_RT_BUFSIZE_SHIFTVAL(tid) \
359 ((((tid) & INFINIPATH_RT_BUFSIZE_MASK) >> 29) + 11 - 1)
360 #define INFINIPATH_RT_BUFSIZE(tid) (1 << INFINIPATH_RT_BUFSIZE_SHIFTVAL(tid))
361 #define INFINIPATH_RT_IS_VALID(tid) \
362 (((tid) & INFINIPATH_RT_BUFSIZE_MASK) && \
363 ((((tid) & INFINIPATH_RT_BUFSIZE_MASK) != INFINIPATH_RT_BUFSIZE_MASK)))
364 #define INFINIPATH_RT_ADDR_MASK 0x1FFFFFFFULL /* 29 bits valid */
365 #define INFINIPATH_RT_ADDR_SHIFT 10
366
367 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
368 #define INFINIPATH_R_TAILUPD_SHIFT 31
369
370 /* 6120 specific hardware errors... */
371 static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
372 INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
373 INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
374 /*
375 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
376 * parity or memory parity error failures, because most likely we
377 * won't be able to talk to the core of the chip. Nonetheless, we
378 * might see them, if they are in parts of the PCIe core that aren't
379 * essential.
380 */
381 INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
382 INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
383 INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
384 INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
385 INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
386 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
387 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
388 };
389
390 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
391 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
392 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
393 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
394 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
395
396 static void ipath_pe_put_tid_2(struct ipath_devdata *, u64 __iomem *,
397 u32, unsigned long);
398
399 /*
400 * On platforms using this chip, and not having ordered WC stores, we
401 * can get TXE parity errors due to speculative reads to the PIO buffers,
402 * and this, due to a chip bug can result in (many) false parity error
403 * reports. So it's a debug print on those, and an info print on systems
404 * where the speculative reads don't occur.
405 */
406 static void ipath_pe_txe_recover(struct ipath_devdata *dd)
407 {
408 if (ipath_unordered_wc())
409 ipath_dbg("Recovering from TXE PIO parity error\n");
410 else {
411 ++ipath_stats.sps_txeparity;
412 dev_info(&dd->pcidev->dev,
413 "Recovering from TXE PIO parity error\n");
414 }
415 }
416
417
418 /**
419 * ipath_pe_handle_hwerrors - display hardware errors.
420 * @dd: the infinipath device
421 * @msg: the output buffer
422 * @msgl: the size of the output buffer
423 *
424 * Use same msg buffer as regular errors to avoid excessive stack
425 * use. Most hardware errors are catastrophic, but for right now,
426 * we'll print them and continue. We reuse the same message buffer as
427 * ipath_handle_errors() to avoid excessive stack usage.
428 */
429 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
430 size_t msgl)
431 {
432 ipath_err_t hwerrs;
433 u32 bits, ctrl;
434 int isfatal = 0;
435 char bitsmsg[64];
436 int log_idx;
437
438 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
439 if (!hwerrs) {
440 /*
441 * better than printing cofusing messages
442 * This seems to be related to clearing the crc error, or
443 * the pll error during init.
444 */
445 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
446 return;
447 } else if (hwerrs == ~0ULL) {
448 ipath_dev_err(dd, "Read of hardware error status failed "
449 "(all bits set); ignoring\n");
450 return;
451 }
452 ipath_stats.sps_hwerrs++;
453
454 /* Always clear the error status register, except MEMBISTFAIL,
455 * regardless of whether we continue or stop using the chip.
456 * We want that set so we know it failed, even across driver reload.
457 * We'll still ignore it in the hwerrmask. We do this partly for
458 * diagnostics, but also for support */
459 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
460 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
461
462 hwerrs &= dd->ipath_hwerrmask;
463
464 /* We log some errors to EEPROM, check if we have any of those. */
465 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
466 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
467 ipath_inc_eeprom_err(dd, log_idx, 1);
468
469 /*
470 * make sure we get this much out, unless told to be quiet,
471 * or it's occurred within the last 5 seconds
472 */
473 if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
474 RXE_EAGER_PARITY)) ||
475 (ipath_debug & __IPATH_VERBDBG))
476 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
477 "(cleared)\n", (unsigned long long) hwerrs);
478 dd->ipath_lasthwerror |= hwerrs;
479
480 if (hwerrs & ~dd->ipath_hwe_bitsextant)
481 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
482 "%llx set\n", (unsigned long long)
483 (hwerrs & ~dd->ipath_hwe_bitsextant));
484
485 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
486 if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
487 /*
488 * parity errors in send memory are recoverable,
489 * just cancel the send (if indicated in * sendbuffererror),
490 * count the occurrence, unfreeze (if no other handled
491 * hardware error bits are set), and continue. They can
492 * occur if a processor speculative read is done to the PIO
493 * buffer while we are sending a packet, for example.
494 */
495 if (hwerrs & TXE_PIO_PARITY) {
496 ipath_pe_txe_recover(dd);
497 hwerrs &= ~TXE_PIO_PARITY;
498 }
499 if (!hwerrs) {
500 static u32 freeze_cnt;
501
502 freeze_cnt++;
503 ipath_dbg("Clearing freezemode on ignored or recovered "
504 "hardware error (%u)\n", freeze_cnt);
505 ipath_clear_freeze(dd);
506 }
507 }
508
509 *msg = '\0';
510
511 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
512 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
513 msgl);
514 /* ignore from now on, so disable until driver reloaded */
515 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
516 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
517 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
518 dd->ipath_hwerrmask);
519 }
520
521 ipath_format_hwerrors(hwerrs,
522 ipath_6120_hwerror_msgs,
523 sizeof(ipath_6120_hwerror_msgs)/
524 sizeof(ipath_6120_hwerror_msgs[0]),
525 msg, msgl);
526
527 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
528 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
529 bits = (u32) ((hwerrs >>
530 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
531 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
532 snprintf(bitsmsg, sizeof bitsmsg,
533 "[PCIe Mem Parity Errs %x] ", bits);
534 strlcat(msg, bitsmsg, msgl);
535 }
536
537 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
538 INFINIPATH_HWE_COREPLL_RFSLIP )
539
540 if (hwerrs & _IPATH_PLL_FAIL) {
541 snprintf(bitsmsg, sizeof bitsmsg,
542 "[PLL failed (%llx), InfiniPath hardware unusable]",
543 (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
544 strlcat(msg, bitsmsg, msgl);
545 /* ignore from now on, so disable until driver reloaded */
546 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
547 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
548 dd->ipath_hwerrmask);
549 }
550
551 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
552 /*
553 * If it occurs, it is left masked since the external
554 * interface is unused
555 */
556 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
557 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
558 dd->ipath_hwerrmask);
559 }
560
561 if (hwerrs) {
562 /*
563 * if any set that we aren't ignoring; only
564 * make the complaint once, in case it's stuck
565 * or recurring, and we get here multiple
566 * times.
567 */
568 ipath_dev_err(dd, "%s hardware error\n", msg);
569 if (dd->ipath_flags & IPATH_INITTED) {
570 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
571 ipath_setup_pe_setextled(dd,
572 INFINIPATH_IBCS_L_STATE_DOWN,
573 INFINIPATH_IBCS_LT_STATE_DISABLED);
574 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
575 "mode), no longer usable, SN %.16s\n",
576 dd->ipath_serial);
577 isfatal = 1;
578 }
579 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
580 /* mark as having had error */
581 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
582 /*
583 * mark as not usable, at a minimum until driver
584 * is reloaded, probably until reboot, since no
585 * other reset is possible.
586 */
587 dd->ipath_flags &= ~IPATH_INITTED;
588 } else
589 *msg = 0; /* recovered from all of them */
590
591 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg && msg) {
592 /*
593 * for /sys status file ; if no trailing brace is copied,
594 * we'll know it was truncated.
595 */
596 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
597 "{%s}", msg);
598 }
599 }
600
601 /**
602 * ipath_pe_boardname - fill in the board name
603 * @dd: the infinipath device
604 * @name: the output buffer
605 * @namelen: the size of the output buffer
606 *
607 * info is based on the board revision register
608 */
609 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
610 size_t namelen)
611 {
612 char *n = NULL;
613 u8 boardrev = dd->ipath_boardrev;
614 int ret;
615
616 switch (boardrev) {
617 case 0:
618 n = "InfiniPath_Emulation";
619 break;
620 case 1:
621 n = "InfiniPath_QLE7140-Bringup";
622 break;
623 case 2:
624 n = "InfiniPath_QLE7140";
625 break;
626 case 3:
627 n = "InfiniPath_QMI7140";
628 break;
629 case 4:
630 n = "InfiniPath_QEM7140";
631 break;
632 case 5:
633 n = "InfiniPath_QMH7140";
634 break;
635 case 6:
636 n = "InfiniPath_QLE7142";
637 break;
638 default:
639 ipath_dev_err(dd,
640 "Don't yet know about board with ID %u\n",
641 boardrev);
642 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
643 boardrev);
644 break;
645 }
646 if (n)
647 snprintf(name, namelen, "%s", n);
648
649 if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
650 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
651 dd->ipath_majrev, dd->ipath_minrev);
652 ret = 1;
653 } else {
654 ret = 0;
655 if (dd->ipath_minrev >= 2)
656 dd->ipath_f_put_tid = ipath_pe_put_tid_2;
657 }
658
659 /*
660 * set here, not in ipath_init_*_funcs because we have to do
661 * it after we can read chip registers.
662 */
663 dd->ipath_ureg_align =
664 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
665
666 return ret;
667 }
668
669 /**
670 * ipath_pe_init_hwerrors - enable hardware errors
671 * @dd: the infinipath device
672 *
673 * now that we have finished initializing everything that might reasonably
674 * cause a hardware error, and cleared those errors bits as they occur,
675 * we can enable hardware errors in the mask (potentially enabling
676 * freeze mode), and enable hardware errors as errors (along with
677 * everything else) in errormask
678 */
679 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
680 {
681 ipath_err_t val;
682 u64 extsval;
683
684 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
685
686 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
687 ipath_dev_err(dd, "MemBIST did not complete!\n");
688 if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
689 ipath_dbg("MemBIST corrected\n");
690
691 val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */
692
693 if (!dd->ipath_boardrev) // no PLL for Emulator
694 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
695
696 if (dd->ipath_minrev < 2) {
697 /* workaround bug 9460 in internal interface bus parity
698 * checking. Fixed (HW bug 9490) in Rev2.
699 */
700 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
701 }
702 dd->ipath_hwerrmask = val;
703 }
704
705 /**
706 * ipath_pe_bringup_serdes - bring up the serdes
707 * @dd: the infinipath device
708 */
709 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
710 {
711 u64 val, config1, prev_val;
712 int ret = 0;
713
714 ipath_dbg("Trying to bringup serdes\n");
715
716 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
717 INFINIPATH_HWE_SERDESPLLFAILED) {
718 ipath_dbg("At start, serdes PLL failed bit set "
719 "in hwerrstatus, clearing and continuing\n");
720 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
721 INFINIPATH_HWE_SERDESPLLFAILED);
722 }
723
724 dd->ibdeltainprog = 1;
725 dd->ibsymsnap =
726 ipath_read_creg32(dd, dd->ipath_cregs->cr_ibsymbolerrcnt);
727 dd->iblnkerrsnap =
728 ipath_read_creg32(dd, dd->ipath_cregs->cr_iblinkerrrecovcnt);
729
730 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
731 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
732
733 ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
734 "xgxsconfig %llx\n", (unsigned long long) val,
735 (unsigned long long) config1, (unsigned long long)
736 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
737
738 /*
739 * Force reset on, also set rxdetect enable. Must do before reading
740 * serdesstatus at least for simulation, or some of the bits in
741 * serdes status will come back as undefined and cause simulation
742 * failures
743 */
744 val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
745 | INFINIPATH_SERDC0_L1PWR_DN;
746 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
747 /* be sure chip saw it */
748 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
749 udelay(5); /* need pll reset set at least for a bit */
750 /*
751 * after PLL is reset, set the per-lane Resets and TxIdle and
752 * clear the PLL reset and rxdetect (to get falling edge).
753 * Leave L1PWR bits set (permanently)
754 */
755 val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
756 | INFINIPATH_SERDC0_L1PWR_DN);
757 val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
758 ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
759 "and txidle (%llx)\n", (unsigned long long) val);
760 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
761 /* be sure chip saw it */
762 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
763 /* need PLL reset clear for at least 11 usec before lane
764 * resets cleared; give it a few more to be sure */
765 udelay(15);
766 val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
767
768 ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
769 "(writing %llx)\n", (unsigned long long) val);
770 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
771 /* be sure chip saw it */
772 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
773
774 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
775 prev_val = val;
776 if (val & INFINIPATH_XGXS_RESET)
777 val &= ~INFINIPATH_XGXS_RESET;
778 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
779 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
780 /* need to compensate for Tx inversion in partner */
781 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
782 INFINIPATH_XGXS_RX_POL_SHIFT);
783 val |= dd->ipath_rx_pol_inv <<
784 INFINIPATH_XGXS_RX_POL_SHIFT;
785 }
786 if (val != prev_val)
787 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
788
789 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
790
791 /* clear current and de-emphasis bits */
792 config1 &= ~0x0ffffffff00ULL;
793 /* set current to 20ma */
794 config1 |= 0x00000000000ULL;
795 /* set de-emphasis to -5.68dB */
796 config1 |= 0x0cccc000000ULL;
797 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
798
799 ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
800 "config1=%llx, sstatus=%llx xgxs=%llx\n",
801 (unsigned long long) val, (unsigned long long) config1,
802 (unsigned long long)
803 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
804 (unsigned long long)
805 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
806
807 return ret;
808 }
809
810 /**
811 * ipath_pe_quiet_serdes - set serdes to txidle
812 * @dd: the infinipath device
813 * Called when driver is being unloaded
814 */
815 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
816 {
817 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
818
819 if (dd->ibsymdelta || dd->iblnkerrdelta ||
820 dd->ibdeltainprog) {
821 u64 diagc;
822 /* enable counter writes */
823 diagc = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwdiagctrl);
824 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwdiagctrl,
825 diagc | INFINIPATH_DC_COUNTERWREN);
826
827 if (dd->ibsymdelta || dd->ibdeltainprog) {
828 val = ipath_read_creg32(dd,
829 dd->ipath_cregs->cr_ibsymbolerrcnt);
830 if (dd->ibdeltainprog)
831 val -= val - dd->ibsymsnap;
832 val -= dd->ibsymdelta;
833 ipath_write_creg(dd,
834 dd->ipath_cregs->cr_ibsymbolerrcnt, val);
835 }
836 if (dd->iblnkerrdelta || dd->ibdeltainprog) {
837 val = ipath_read_creg32(dd,
838 dd->ipath_cregs->cr_iblinkerrrecovcnt);
839 if (dd->ibdeltainprog)
840 val -= val - dd->iblnkerrsnap;
841 val -= dd->iblnkerrdelta;
842 ipath_write_creg(dd,
843 dd->ipath_cregs->cr_iblinkerrrecovcnt, val);
844 }
845
846 /* and disable counter writes */
847 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwdiagctrl, diagc);
848 }
849 val |= INFINIPATH_SERDC0_TXIDLE;
850 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
851 (unsigned long long) val);
852 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
853 }
854
855 static int ipath_pe_intconfig(struct ipath_devdata *dd)
856 {
857 u32 chiprev;
858
859 /*
860 * If the chip supports added error indication via GPIO pins,
861 * enable interrupts on those bits so the interrupt routine
862 * can count the events. Also set flag so interrupt routine
863 * can know they are expected.
864 */
865 chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
866 if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
867 /* Rev2+ reports extra errors via internal GPIO pins */
868 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
869 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
870 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
871 dd->ipath_gpio_mask);
872 }
873 return 0;
874 }
875
876 /**
877 * ipath_setup_pe_setextled - set the state of the two external LEDs
878 * @dd: the infinipath device
879 * @lst: the L state
880 * @ltst: the LT state
881
882 * These LEDs indicate the physical and logical state of IB link.
883 * For this chip (at least with recommended board pinouts), LED1
884 * is Yellow (logical state) and LED2 is Green (physical state),
885 *
886 * Note: We try to match the Mellanox HCA LED behavior as best
887 * we can. Green indicates physical link state is OK (something is
888 * plugged in, and we can train).
889 * Amber indicates the link is logically up (ACTIVE).
890 * Mellanox further blinks the amber LED to indicate data packet
891 * activity, but we have no hardware support for that, so it would
892 * require waking up every 10-20 msecs and checking the counters
893 * on the chip, and then turning the LED off if appropriate. That's
894 * visible overhead, so not something we will do.
895 *
896 */
897 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
898 u64 ltst)
899 {
900 u64 extctl;
901 unsigned long flags = 0;
902
903 /* the diags use the LED to indicate diag info, so we leave
904 * the external LED alone when the diags are running */
905 if (ipath_diag_inuse)
906 return;
907
908 /* Allow override of LED display for, e.g. Locating system in rack */
909 if (dd->ipath_led_override) {
910 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
911 ? INFINIPATH_IBCS_LT_STATE_LINKUP
912 : INFINIPATH_IBCS_LT_STATE_DISABLED;
913 lst = (dd->ipath_led_override & IPATH_LED_LOG)
914 ? INFINIPATH_IBCS_L_STATE_ACTIVE
915 : INFINIPATH_IBCS_L_STATE_DOWN;
916 }
917
918 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
919 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
920 INFINIPATH_EXTC_LED2PRIPORT_ON);
921
922 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
923 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
924 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
925 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
926 dd->ipath_extctrl = extctl;
927 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
928 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
929 }
930
931 /**
932 * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
933 * @dd: the infinipath device
934 *
935 * This is called during driver unload.
936 * We do the pci_disable_msi here, not in generic code, because it
937 * isn't used for the HT chips. If we do end up needing pci_enable_msi
938 * at some point in the future for HT, we'll move the call back
939 * into the main init_one code.
940 */
941 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
942 {
943 dd->ipath_msi_lo = 0; /* just in case unload fails */
944 pci_disable_msi(dd->pcidev);
945 }
946
947 static void ipath_6120_pcie_params(struct ipath_devdata *dd)
948 {
949 u16 linkstat, speed;
950 int pos;
951
952 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP);
953 if (!pos) {
954 ipath_dev_err(dd, "Can't find PCI Express capability!\n");
955 goto bail;
956 }
957
958 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
959 &linkstat);
960 /*
961 * speed is bits 0-4, linkwidth is bits 4-8
962 * no defines for them in headers
963 */
964 speed = linkstat & 0xf;
965 linkstat >>= 4;
966 linkstat &= 0x1f;
967 dd->ipath_lbus_width = linkstat;
968
969 switch (speed) {
970 case 1:
971 dd->ipath_lbus_speed = 2500; /* Gen1, 2.5GHz */
972 break;
973 case 2:
974 dd->ipath_lbus_speed = 5000; /* Gen1, 5GHz */
975 break;
976 default: /* not defined, assume gen1 */
977 dd->ipath_lbus_speed = 2500;
978 break;
979 }
980
981 if (linkstat < 8)
982 ipath_dev_err(dd,
983 "PCIe width %u (x8 HCA), performance reduced\n",
984 linkstat);
985 else
986 ipath_cdbg(VERBOSE, "PCIe speed %u width %u (x8 HCA)\n",
987 dd->ipath_lbus_speed, linkstat);
988
989 if (speed != 1)
990 ipath_dev_err(dd,
991 "PCIe linkspeed %u is incorrect; "
992 "should be 1 (2500)!\n", speed);
993 bail:
994 /* fill in string, even on errors */
995 snprintf(dd->ipath_lbus_info, sizeof(dd->ipath_lbus_info),
996 "PCIe,%uMHz,x%u\n",
997 dd->ipath_lbus_speed,
998 dd->ipath_lbus_width);
999
1000 return;
1001 }
1002
1003 /**
1004 * ipath_setup_pe_config - setup PCIe config related stuff
1005 * @dd: the infinipath device
1006 * @pdev: the PCI device
1007 *
1008 * The pci_enable_msi() call will fail on systems with MSI quirks
1009 * such as those with AMD8131, even if the device of interest is not
1010 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
1011 * late in 2.6.16).
1012 * All that can be done is to edit the kernel source to remove the quirk
1013 * check until that is fixed.
1014 * We do not need to call enable_msi() for our HyperTransport chip,
1015 * even though it uses MSI, and we want to avoid the quirk warning, so
1016 * So we call enable_msi only for PCIe. If we do end up needing
1017 * pci_enable_msi at some point in the future for HT, we'll move the
1018 * call back into the main init_one code.
1019 * We save the msi lo and hi values, so we can restore them after
1020 * chip reset (the kernel PCI infrastructure doesn't yet handle that
1021 * correctly).
1022 */
1023 static int ipath_setup_pe_config(struct ipath_devdata *dd,
1024 struct pci_dev *pdev)
1025 {
1026 int pos, ret;
1027
1028 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
1029 ret = pci_enable_msi(dd->pcidev);
1030 if (ret)
1031 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
1032 "interrupts may not work\n", ret);
1033 /* continue even if it fails, we may still be OK... */
1034 dd->ipath_irq = pdev->irq;
1035
1036 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1037 u16 control;
1038 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1039 &dd->ipath_msi_lo);
1040 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1041 &dd->ipath_msi_hi);
1042 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1043 &control);
1044 /* now save the data (vector) info */
1045 pci_read_config_word(dd->pcidev,
1046 pos + ((control & PCI_MSI_FLAGS_64BIT)
1047 ? 12 : 8),
1048 &dd->ipath_msi_data);
1049 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
1050 "0x%x, control=0x%x\n", dd->ipath_msi_data,
1051 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1052 control);
1053 /* we save the cachelinesize also, although it doesn't
1054 * really matter */
1055 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1056 &dd->ipath_pci_cacheline);
1057 } else
1058 ipath_dev_err(dd, "Can't find MSI capability, "
1059 "can't save MSI settings for reset\n");
1060
1061 ipath_6120_pcie_params(dd);
1062
1063 dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
1064 dd->ipath_link_speed_supported = IPATH_IB_SDR;
1065 dd->ipath_link_width_enabled = IB_WIDTH_4X;
1066 dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported;
1067 /* these can't change for this chip, so set once */
1068 dd->ipath_link_width_active = dd->ipath_link_width_enabled;
1069 dd->ipath_link_speed_active = dd->ipath_link_speed_enabled;
1070 return 0;
1071 }
1072
1073 static void ipath_init_pe_variables(struct ipath_devdata *dd)
1074 {
1075 /*
1076 * setup the register offsets, since they are different for each
1077 * chip
1078 */
1079 dd->ipath_kregs = &ipath_pe_kregs;
1080 dd->ipath_cregs = &ipath_pe_cregs;
1081
1082 /*
1083 * bits for selecting i2c direction and values,
1084 * used for I2C serial flash
1085 */
1086 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1087 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1088 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1089 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1090
1091 /*
1092 * Fill in data for field-values that change in newer chips.
1093 * We dynamically specify only the mask for LINKTRAININGSTATE
1094 * and only the shift for LINKSTATE, as they are the only ones
1095 * that change. Also precalculate the 3 link states of interest
1096 * and the combined mask.
1097 */
1098 dd->ibcs_ls_shift = IBA6120_IBCS_LINKSTATE_SHIFT;
1099 dd->ibcs_lts_mask = IBA6120_IBCS_LINKTRAININGSTATE_MASK;
1100 dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK <<
1101 dd->ibcs_ls_shift) | dd->ibcs_lts_mask;
1102 dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1103 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1104 (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift);
1105 dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1106 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1107 (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift);
1108 dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1109 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1110 (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift);
1111
1112 /*
1113 * Fill in data for ibcc field-values that change in newer chips.
1114 * We dynamically specify only the mask for LINKINITCMD
1115 * and only the shift for LINKCMD and MAXPKTLEN, as they are
1116 * the only ones that change.
1117 */
1118 dd->ibcc_lic_mask = INFINIPATH_IBCC_LINKINITCMD_MASK;
1119 dd->ibcc_lc_shift = INFINIPATH_IBCC_LINKCMD_SHIFT;
1120 dd->ibcc_mpl_shift = INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
1121
1122 /* Fill in shifts for RcvCtrl. */
1123 dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1124 dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
1125 dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
1126 dd->ipath_r_portcfg_shift = 0; /* Not on IBA6120 */
1127
1128 /* variables for sanity checking interrupt and errors */
1129 dd->ipath_hwe_bitsextant =
1130 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1131 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1132 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1133 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1134 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
1135 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
1136 INFINIPATH_HWE_PCIE1PLLFAILED |
1137 INFINIPATH_HWE_PCIE0PLLFAILED |
1138 INFINIPATH_HWE_PCIEPOISONEDTLP |
1139 INFINIPATH_HWE_PCIECPLTIMEOUT |
1140 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
1141 INFINIPATH_HWE_PCIEBUSPARITYXADM |
1142 INFINIPATH_HWE_PCIEBUSPARITYRADM |
1143 INFINIPATH_HWE_MEMBISTFAILED |
1144 INFINIPATH_HWE_COREPLL_FBSLIP |
1145 INFINIPATH_HWE_COREPLL_RFSLIP |
1146 INFINIPATH_HWE_SERDESPLLFAILED |
1147 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1148 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1149 dd->ipath_i_bitsextant =
1150 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1151 (INFINIPATH_I_RCVAVAIL_MASK <<
1152 INFINIPATH_I_RCVAVAIL_SHIFT) |
1153 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1154 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1155 dd->ipath_e_bitsextant =
1156 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1157 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1158 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1159 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1160 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1161 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1162 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1163 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1164 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1165 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1166 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1167 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1168 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1169 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1170 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1171 INFINIPATH_E_HARDWARE;
1172
1173 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1174 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1175 dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT;
1176 dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT;
1177
1178 /*
1179 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1180 * 2 is Some Misc, 3 is reserved for future.
1181 */
1182 dd->ipath_eep_st_masks[0].hwerrs_to_log =
1183 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1184 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1185
1186 /* Ignore errors in PIO/PBC on systems with unordered write-combining */
1187 if (ipath_unordered_wc())
1188 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
1189
1190 dd->ipath_eep_st_masks[1].hwerrs_to_log =
1191 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1192 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1193
1194 dd->ipath_eep_st_masks[2].errs_to_log = INFINIPATH_E_RESET;
1195 dd->delay_mult = 2; /* SDR, 4X, can't change */
1196 }
1197
1198 /* setup the MSI stuff again after a reset. I'd like to just call
1199 * pci_enable_msi() and request_irq() again, but when I do that,
1200 * the MSI enable bit doesn't get set in the command word, and
1201 * we switch to to a different interrupt vector, which is confusing,
1202 * so I instead just do it all inline. Perhaps somehow can tie this
1203 * into the PCIe hotplug support at some point
1204 * Note, because I'm doing it all here, I don't call pci_disable_msi()
1205 * or free_irq() at the start of ipath_setup_pe_reset().
1206 */
1207 static int ipath_reinit_msi(struct ipath_devdata *dd)
1208 {
1209 int pos;
1210 u16 control;
1211 int ret;
1212
1213 if (!dd->ipath_msi_lo) {
1214 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
1215 "initial setup failed?\n");
1216 ret = 0;
1217 goto bail;
1218 }
1219
1220 if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1221 ipath_dev_err(dd, "Can't find MSI capability, "
1222 "can't restore MSI settings\n");
1223 ret = 0;
1224 goto bail;
1225 }
1226 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1227 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1228 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1229 dd->ipath_msi_lo);
1230 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1231 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1232 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1233 dd->ipath_msi_hi);
1234 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1235 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1236 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1237 "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1238 control, control | PCI_MSI_FLAGS_ENABLE);
1239 control |= PCI_MSI_FLAGS_ENABLE;
1240 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1241 control);
1242 }
1243 /* now rewrite the data (vector) info */
1244 pci_write_config_word(dd->pcidev, pos +
1245 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1246 dd->ipath_msi_data);
1247 /* we restore the cachelinesize also, although it doesn't really
1248 * matter */
1249 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1250 dd->ipath_pci_cacheline);
1251 /* and now set the pci master bit again */
1252 pci_set_master(dd->pcidev);
1253 ret = 1;
1254
1255 bail:
1256 return ret;
1257 }
1258
1259 /* This routine sleeps, so it can only be called from user context, not
1260 * from interrupt context. If we need interrupt context, we can split
1261 * it into two routines.
1262 */
1263 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1264 {
1265 u64 val;
1266 int i;
1267 int ret;
1268 u16 cmdval;
1269
1270 pci_read_config_word(dd->pcidev, PCI_COMMAND, &cmdval);
1271
1272 /* Use ERROR so it shows up in logs, etc. */
1273 ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1274 /* keep chip from being accessed in a few places */
1275 dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1276 val = dd->ipath_control | INFINIPATH_C_RESET;
1277 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1278 mb();
1279
1280 for (i = 1; i <= 5; i++) {
1281 int r;
1282 /* allow MBIST, etc. to complete; longer on each retry.
1283 * We sometimes get machine checks from bus timeout if no
1284 * response, so for now, make it *really* long.
1285 */
1286 msleep(1000 + (1 + i) * 2000);
1287 if ((r =
1288 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1289 dd->ipath_pcibar0)))
1290 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1291 r);
1292 if ((r =
1293 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1294 dd->ipath_pcibar1)))
1295 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1296 r);
1297 /* now re-enable memory access */
1298 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmdval);
1299 if ((r = pci_enable_device(dd->pcidev)))
1300 ipath_dev_err(dd, "pci_enable_device failed after "
1301 "reset: %d\n", r);
1302 /*
1303 * whether it fully enabled or not, mark as present,
1304 * again (but not INITTED)
1305 */
1306 dd->ipath_flags |= IPATH_PRESENT;
1307 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1308 if (val == dd->ipath_revision) {
1309 ipath_cdbg(VERBOSE, "Got matching revision "
1310 "register %llx on try %d\n",
1311 (unsigned long long) val, i);
1312 ret = ipath_reinit_msi(dd);
1313 goto bail;
1314 }
1315 /* Probably getting -1 back */
1316 ipath_dbg("Didn't get expected revision register, "
1317 "got %llx, try %d\n", (unsigned long long) val,
1318 i + 1);
1319 }
1320 ret = 0; /* failed */
1321
1322 bail:
1323 if (ret)
1324 ipath_6120_pcie_params(dd);
1325 return ret;
1326 }
1327
1328 /**
1329 * ipath_pe_put_tid - write a TID in chip
1330 * @dd: the infinipath device
1331 * @tidptr: pointer to the expected TID (in chip) to update
1332 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1333 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1334 *
1335 * This exists as a separate routine to allow for special locking etc.
1336 * It's used for both the full cleanup on exit, as well as the normal
1337 * setup and teardown.
1338 */
1339 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1340 u32 type, unsigned long pa)
1341 {
1342 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1343 unsigned long flags = 0; /* keep gcc quiet */
1344 int tidx;
1345 spinlock_t *tidlockp;
1346
1347 if (!dd->ipath_kregbase)
1348 return;
1349
1350 if (pa != dd->ipath_tidinvalid) {
1351 if (pa & ((1U << 11) - 1)) {
1352 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1353 "not 2KB aligned!\n", pa);
1354 return;
1355 }
1356 pa >>= 11;
1357 /* paranoia check */
1358 if (pa & ~INFINIPATH_RT_ADDR_MASK)
1359 ipath_dev_err(dd,
1360 "BUG: Physical page address 0x%lx "
1361 "has bits set in 31-29\n", pa);
1362
1363 if (type == RCVHQ_RCV_TYPE_EAGER)
1364 pa |= dd->ipath_tidtemplate;
1365 else /* for now, always full 4KB page */
1366 pa |= 2 << 29;
1367 }
1368
1369 /*
1370 * Workaround chip bug 9437 by writing the scratch register
1371 * before and after the TID, and with an io write barrier.
1372 * We use a spinlock around the writes, so they can't intermix
1373 * with other TID (eager or expected) writes (the chip bug
1374 * is triggered by back to back TID writes). Unfortunately, this
1375 * call can be done from interrupt level for the port 0 eager TIDs,
1376 * so we have to use irqsave locks.
1377 */
1378 /*
1379 * Assumes tidptr always > ipath_egrtidbase
1380 * if type == RCVHQ_RCV_TYPE_EAGER.
1381 */
1382 tidx = tidptr - dd->ipath_egrtidbase;
1383
1384 tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->ipath_rcvegrcnt)
1385 ? &dd->ipath_kernel_tid_lock : &dd->ipath_user_tid_lock;
1386 spin_lock_irqsave(tidlockp, flags);
1387 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1388 writel(pa, tidp32);
1389 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1390 mmiowb();
1391 spin_unlock_irqrestore(tidlockp, flags);
1392 }
1393
1394 /**
1395 * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1396 * @dd: the infinipath device
1397 * @tidptr: pointer to the expected TID (in chip) to update
1398 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1399 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1400 *
1401 * This exists as a separate routine to allow for selection of the
1402 * appropriate "flavor". The static calls in cleanup just use the
1403 * revision-agnostic form, as they are not performance critical.
1404 */
1405 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1406 u32 type, unsigned long pa)
1407 {
1408 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1409 u32 tidx;
1410
1411 if (!dd->ipath_kregbase)
1412 return;
1413
1414 if (pa != dd->ipath_tidinvalid) {
1415 if (pa & ((1U << 11) - 1)) {
1416 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1417 "not 2KB aligned!\n", pa);
1418 return;
1419 }
1420 pa >>= 11;
1421 /* paranoia check */
1422 if (pa & ~INFINIPATH_RT_ADDR_MASK)
1423 ipath_dev_err(dd,
1424 "BUG: Physical page address 0x%lx "
1425 "has bits set in 31-29\n", pa);
1426
1427 if (type == RCVHQ_RCV_TYPE_EAGER)
1428 pa |= dd->ipath_tidtemplate;
1429 else /* for now, always full 4KB page */
1430 pa |= 2 << 29;
1431 }
1432 tidx = tidptr - dd->ipath_egrtidbase;
1433 writel(pa, tidp32);
1434 mmiowb();
1435 }
1436
1437
1438 /**
1439 * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1440 * @dd: the infinipath device
1441 * @port: the port
1442 *
1443 * clear all TID entries for a port, expected and eager.
1444 * Used from ipath_close(). On this chip, TIDs are only 32 bits,
1445 * not 64, but they are still on 64 bit boundaries, so tidbase
1446 * is declared as u64 * for the pointer math, even though we write 32 bits
1447 */
1448 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1449 {
1450 u64 __iomem *tidbase;
1451 unsigned long tidinv;
1452 int i;
1453
1454 if (!dd->ipath_kregbase)
1455 return;
1456
1457 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1458
1459 tidinv = dd->ipath_tidinvalid;
1460 tidbase = (u64 __iomem *)
1461 ((char __iomem *)(dd->ipath_kregbase) +
1462 dd->ipath_rcvtidbase +
1463 port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1464
1465 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1466 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1467 tidinv);
1468
1469 tidbase = (u64 __iomem *)
1470 ((char __iomem *)(dd->ipath_kregbase) +
1471 dd->ipath_rcvegrbase +
1472 port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1473
1474 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1475 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1476 tidinv);
1477 }
1478
1479 /**
1480 * ipath_pe_tidtemplate - setup constants for TID updates
1481 * @dd: the infinipath device
1482 *
1483 * We setup stuff that we use a lot, to avoid calculating each time
1484 */
1485 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1486 {
1487 u32 egrsize = dd->ipath_rcvegrbufsize;
1488
1489 /* For now, we always allocate 4KB buffers (at init) so we can
1490 * receive max size packets. We may want a module parameter to
1491 * specify 2KB or 4KB and/or make be per port instead of per device
1492 * for those who want to reduce memory footprint. Note that the
1493 * ipath_rcvhdrentsize size must be large enough to hold the largest
1494 * IB header (currently 96 bytes) that we expect to handle (plus of
1495 * course the 2 dwords of RHF).
1496 */
1497 if (egrsize == 2048)
1498 dd->ipath_tidtemplate = 1U << 29;
1499 else if (egrsize == 4096)
1500 dd->ipath_tidtemplate = 2U << 29;
1501 else {
1502 egrsize = 4096;
1503 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1504 "%u, using %u\n", dd->ipath_rcvegrbufsize,
1505 egrsize);
1506 dd->ipath_tidtemplate = 2U << 29;
1507 }
1508 dd->ipath_tidinvalid = 0;
1509 }
1510
1511 static int ipath_pe_early_init(struct ipath_devdata *dd)
1512 {
1513 dd->ipath_flags |= IPATH_4BYTE_TID;
1514 if (ipath_unordered_wc())
1515 dd->ipath_flags |= IPATH_PIO_FLUSH_WC;
1516
1517 /*
1518 * For openfabrics, we need to be able to handle an IB header of
1519 * 24 dwords. HT chip has arbitrary sized receive buffers, so we
1520 * made them the same size as the PIO buffers. This chip does not
1521 * handle arbitrary size buffers, so we need the header large enough
1522 * to handle largest IB header, but still have room for a 2KB MTU
1523 * standard IB packet.
1524 */
1525 dd->ipath_rcvhdrentsize = 24;
1526 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1527 dd->ipath_rhf_offset = 0;
1528 dd->ipath_egrtidbase = (u64 __iomem *)
1529 ((char __iomem *) dd->ipath_kregbase + dd->ipath_rcvegrbase);
1530
1531 dd->ipath_rcvegrbufsize = ipath_mtu4096 ? 4096 : 2048;
1532 /*
1533 * the min() check here is currently a nop, but it may not always
1534 * be, depending on just how we do ipath_rcvegrbufsize
1535 */
1536 dd->ipath_ibmaxlen = min(ipath_mtu4096 ? dd->ipath_piosize4k :
1537 dd->ipath_piosize2k,
1538 dd->ipath_rcvegrbufsize +
1539 (dd->ipath_rcvhdrentsize << 2));
1540 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1541
1542 /*
1543 * We can request a receive interrupt for 1 or
1544 * more packets from current offset. For now, we set this
1545 * up for a single packet.
1546 */
1547 dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1548
1549 ipath_get_eeprom_info(dd);
1550
1551 return 0;
1552 }
1553
1554 int __attribute__((weak)) ipath_unordered_wc(void)
1555 {
1556 return 0;
1557 }
1558
1559 /**
1560 * ipath_init_pe_get_base_info - set chip-specific flags for user code
1561 * @pd: the infinipath port
1562 * @kbase: ipath_base_info pointer
1563 *
1564 * We set the PCIE flag because the lower bandwidth on PCIe vs
1565 * HyperTransport can affect some user packet algorithms.
1566 */
1567 static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1568 {
1569 struct ipath_base_info *kinfo = kbase;
1570 struct ipath_devdata *dd;
1571
1572 if (ipath_unordered_wc()) {
1573 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1574 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1575 }
1576 else
1577 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1578
1579 if (pd == NULL)
1580 goto done;
1581
1582 dd = pd->port_dd;
1583
1584 done:
1585 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE |
1586 IPATH_RUNTIME_FORCE_PIOAVAIL | IPATH_RUNTIME_PIO_REGSWAPPED;
1587 return 0;
1588 }
1589
1590 static void ipath_pe_free_irq(struct ipath_devdata *dd)
1591 {
1592 free_irq(dd->ipath_irq, dd);
1593 dd->ipath_irq = 0;
1594 }
1595
1596
1597 static struct ipath_message_header *
1598 ipath_pe_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr)
1599 {
1600 return (struct ipath_message_header *)
1601 &rhf_addr[sizeof(u64) / sizeof(u32)];
1602 }
1603
1604 static void ipath_pe_config_ports(struct ipath_devdata *dd, ushort cfgports)
1605 {
1606 dd->ipath_portcnt =
1607 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1608 dd->ipath_p0_rcvegrcnt =
1609 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
1610 }
1611
1612 static void ipath_pe_read_counters(struct ipath_devdata *dd,
1613 struct infinipath_counters *cntrs)
1614 {
1615 cntrs->LBIntCnt =
1616 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1617 cntrs->LBFlowStallCnt =
1618 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1619 cntrs->TxSDmaDescCnt = 0;
1620 cntrs->TxUnsupVLErrCnt =
1621 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1622 cntrs->TxDataPktCnt =
1623 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1624 cntrs->TxFlowPktCnt =
1625 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1626 cntrs->TxDwordCnt =
1627 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1628 cntrs->TxLenErrCnt =
1629 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1630 cntrs->TxMaxMinLenErrCnt =
1631 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1632 cntrs->TxUnderrunCnt =
1633 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1634 cntrs->TxFlowStallCnt =
1635 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1636 cntrs->TxDroppedPktCnt =
1637 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1638 cntrs->RxDroppedPktCnt =
1639 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1640 cntrs->RxDataPktCnt =
1641 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1642 cntrs->RxFlowPktCnt =
1643 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1644 cntrs->RxDwordCnt =
1645 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1646 cntrs->RxLenErrCnt =
1647 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1648 cntrs->RxMaxMinLenErrCnt =
1649 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1650 cntrs->RxICRCErrCnt =
1651 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1652 cntrs->RxVCRCErrCnt =
1653 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1654 cntrs->RxFlowCtrlErrCnt =
1655 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1656 cntrs->RxBadFormatCnt =
1657 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1658 cntrs->RxLinkProblemCnt =
1659 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1660 cntrs->RxEBPCnt =
1661 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1662 cntrs->RxLPCRCErrCnt =
1663 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1664 cntrs->RxBufOvflCnt =
1665 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1666 cntrs->RxTIDFullErrCnt =
1667 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1668 cntrs->RxTIDValidErrCnt =
1669 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1670 cntrs->RxPKeyMismatchCnt =
1671 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1672 cntrs->RxP0HdrEgrOvflCnt =
1673 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1674 cntrs->RxP1HdrEgrOvflCnt =
1675 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1676 cntrs->RxP2HdrEgrOvflCnt =
1677 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1678 cntrs->RxP3HdrEgrOvflCnt =
1679 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1680 cntrs->RxP4HdrEgrOvflCnt =
1681 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1682 cntrs->RxP5HdrEgrOvflCnt = 0;
1683 cntrs->RxP6HdrEgrOvflCnt = 0;
1684 cntrs->RxP7HdrEgrOvflCnt = 0;
1685 cntrs->RxP8HdrEgrOvflCnt = 0;
1686 cntrs->RxP9HdrEgrOvflCnt = 0;
1687 cntrs->RxP10HdrEgrOvflCnt = 0;
1688 cntrs->RxP11HdrEgrOvflCnt = 0;
1689 cntrs->RxP12HdrEgrOvflCnt = 0;
1690 cntrs->RxP13HdrEgrOvflCnt = 0;
1691 cntrs->RxP14HdrEgrOvflCnt = 0;
1692 cntrs->RxP15HdrEgrOvflCnt = 0;
1693 cntrs->RxP16HdrEgrOvflCnt = 0;
1694 cntrs->IBStatusChangeCnt =
1695 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1696 cntrs->IBLinkErrRecoveryCnt =
1697 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1698 cntrs->IBLinkDownedCnt =
1699 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1700 cntrs->IBSymbolErrCnt =
1701 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1702 cntrs->RxVL15DroppedPktCnt = 0;
1703 cntrs->RxOtherLocalPhyErrCnt = 0;
1704 cntrs->PcieRetryBufDiagQwordCnt = 0;
1705 cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1706 cntrs->LocalLinkIntegrityErrCnt = dd->ipath_lli_errs;
1707 cntrs->RxVlErrCnt = 0;
1708 cntrs->RxDlidFltrCnt = 0;
1709 }
1710
1711
1712 /* no interrupt fallback for these chips */
1713 static int ipath_pe_nointr_fallback(struct ipath_devdata *dd)
1714 {
1715 return 0;
1716 }
1717
1718
1719 /*
1720 * reset the XGXS (between serdes and IBC). Slightly less intrusive
1721 * than resetting the IBC or external link state, and useful in some
1722 * cases to cause some retraining. To do this right, we reset IBC
1723 * as well.
1724 */
1725 static void ipath_pe_xgxs_reset(struct ipath_devdata *dd)
1726 {
1727 u64 val, prev_val;
1728
1729 prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1730 val = prev_val | INFINIPATH_XGXS_RESET;
1731 prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */
1732 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1733 dd->ipath_control & ~INFINIPATH_C_LINKENABLE);
1734 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1735 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1736 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val);
1737 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1738 dd->ipath_control);
1739 }
1740
1741
1742 static int ipath_pe_get_ib_cfg(struct ipath_devdata *dd, int which)
1743 {
1744 int ret;
1745
1746 switch (which) {
1747 case IPATH_IB_CFG_LWID:
1748 ret = dd->ipath_link_width_active;
1749 break;
1750 case IPATH_IB_CFG_SPD:
1751 ret = dd->ipath_link_speed_active;
1752 break;
1753 case IPATH_IB_CFG_LWID_ENB:
1754 ret = dd->ipath_link_width_enabled;
1755 break;
1756 case IPATH_IB_CFG_SPD_ENB:
1757 ret = dd->ipath_link_speed_enabled;
1758 break;
1759 default:
1760 ret = -ENOTSUPP;
1761 break;
1762 }
1763 return ret;
1764 }
1765
1766
1767 /* we assume range checking is already done, if needed */
1768 static int ipath_pe_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val)
1769 {
1770 int ret = 0;
1771
1772 if (which == IPATH_IB_CFG_LWID_ENB)
1773 dd->ipath_link_width_enabled = val;
1774 else if (which == IPATH_IB_CFG_SPD_ENB)
1775 dd->ipath_link_speed_enabled = val;
1776 else
1777 ret = -ENOTSUPP;
1778 return ret;
1779 }
1780
1781 static void ipath_pe_config_jint(struct ipath_devdata *dd, u16 a, u16 b)
1782 {
1783 }
1784
1785
1786 static int ipath_pe_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs)
1787 {
1788 if (ibup) {
1789 if (dd->ibdeltainprog) {
1790 dd->ibdeltainprog = 0;
1791 dd->ibsymdelta +=
1792 ipath_read_creg32(dd,
1793 dd->ipath_cregs->cr_ibsymbolerrcnt) -
1794 dd->ibsymsnap;
1795 dd->iblnkerrdelta +=
1796 ipath_read_creg32(dd,
1797 dd->ipath_cregs->cr_iblinkerrrecovcnt) -
1798 dd->iblnkerrsnap;
1799 }
1800 } else {
1801 dd->ipath_lli_counter = 0;
1802 if (!dd->ibdeltainprog) {
1803 dd->ibdeltainprog = 1;
1804 dd->ibsymsnap =
1805 ipath_read_creg32(dd,
1806 dd->ipath_cregs->cr_ibsymbolerrcnt);
1807 dd->iblnkerrsnap =
1808 ipath_read_creg32(dd,
1809 dd->ipath_cregs->cr_iblinkerrrecovcnt);
1810 }
1811 }
1812
1813 ipath_setup_pe_setextled(dd, ipath_ib_linkstate(dd, ibcs),
1814 ipath_ib_linktrstate(dd, ibcs));
1815 return 0;
1816 }
1817
1818
1819 /**
1820 * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1821 * @dd: the infinipath device
1822 *
1823 * This is global, and is called directly at init to set up the
1824 * chip-specific function pointers for later use.
1825 */
1826 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1827 {
1828 dd->ipath_f_intrsetup = ipath_pe_intconfig;
1829 dd->ipath_f_bus = ipath_setup_pe_config;
1830 dd->ipath_f_reset = ipath_setup_pe_reset;
1831 dd->ipath_f_get_boardname = ipath_pe_boardname;
1832 dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1833 dd->ipath_f_early_init = ipath_pe_early_init;
1834 dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1835 dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1836 dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1837 dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1838 /*
1839 * _f_put_tid may get changed after we read the chip revision,
1840 * but we start with the safe version for all revs
1841 */
1842 dd->ipath_f_put_tid = ipath_pe_put_tid;
1843 dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1844 dd->ipath_f_setextled = ipath_setup_pe_setextled;
1845 dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1846 dd->ipath_f_free_irq = ipath_pe_free_irq;
1847 dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1848 dd->ipath_f_intr_fallback = ipath_pe_nointr_fallback;
1849 dd->ipath_f_xgxs_reset = ipath_pe_xgxs_reset;
1850 dd->ipath_f_get_msgheader = ipath_pe_get_msgheader;
1851 dd->ipath_f_config_ports = ipath_pe_config_ports;
1852 dd->ipath_f_read_counters = ipath_pe_read_counters;
1853 dd->ipath_f_get_ib_cfg = ipath_pe_get_ib_cfg;
1854 dd->ipath_f_set_ib_cfg = ipath_pe_set_ib_cfg;
1855 dd->ipath_f_config_jint = ipath_pe_config_jint;
1856 dd->ipath_f_ib_updown = ipath_pe_ib_updown;
1857
1858
1859 /* initialize chip-specific variables */
1860 ipath_init_pe_variables(dd);
1861 }
1862
Linux kernel - Deliverables
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