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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[deliverable/linux.git] / drivers / infiniband / hw / ipath / ipath_iba6120.c
1 /*
2 * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 /*
34 * This file contains all of the code that is specific to the
35 * InfiniPath PCIe chip.
36 */
37
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <rdma/ib_verbs.h>
42
43 #include "ipath_kernel.h"
44 #include "ipath_registers.h"
45
46 static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
47
48 /*
49 * This file contains all the chip-specific register information and
50 * access functions for the QLogic InfiniPath PCI-Express chip.
51 *
52 * This lists the InfiniPath registers, in the actual chip layout.
53 * This structure should never be directly accessed.
54 */
55 struct _infinipath_do_not_use_kernel_regs {
56 unsigned long long Revision;
57 unsigned long long Control;
58 unsigned long long PageAlign;
59 unsigned long long PortCnt;
60 unsigned long long DebugPortSelect;
61 unsigned long long Reserved0;
62 unsigned long long SendRegBase;
63 unsigned long long UserRegBase;
64 unsigned long long CounterRegBase;
65 unsigned long long Scratch;
66 unsigned long long Reserved1;
67 unsigned long long Reserved2;
68 unsigned long long IntBlocked;
69 unsigned long long IntMask;
70 unsigned long long IntStatus;
71 unsigned long long IntClear;
72 unsigned long long ErrorMask;
73 unsigned long long ErrorStatus;
74 unsigned long long ErrorClear;
75 unsigned long long HwErrMask;
76 unsigned long long HwErrStatus;
77 unsigned long long HwErrClear;
78 unsigned long long HwDiagCtrl;
79 unsigned long long MDIO;
80 unsigned long long IBCStatus;
81 unsigned long long IBCCtrl;
82 unsigned long long ExtStatus;
83 unsigned long long ExtCtrl;
84 unsigned long long GPIOOut;
85 unsigned long long GPIOMask;
86 unsigned long long GPIOStatus;
87 unsigned long long GPIOClear;
88 unsigned long long RcvCtrl;
89 unsigned long long RcvBTHQP;
90 unsigned long long RcvHdrSize;
91 unsigned long long RcvHdrCnt;
92 unsigned long long RcvHdrEntSize;
93 unsigned long long RcvTIDBase;
94 unsigned long long RcvTIDCnt;
95 unsigned long long RcvEgrBase;
96 unsigned long long RcvEgrCnt;
97 unsigned long long RcvBufBase;
98 unsigned long long RcvBufSize;
99 unsigned long long RxIntMemBase;
100 unsigned long long RxIntMemSize;
101 unsigned long long RcvPartitionKey;
102 unsigned long long Reserved3;
103 unsigned long long RcvPktLEDCnt;
104 unsigned long long Reserved4[8];
105 unsigned long long SendCtrl;
106 unsigned long long SendPIOBufBase;
107 unsigned long long SendPIOSize;
108 unsigned long long SendPIOBufCnt;
109 unsigned long long SendPIOAvailAddr;
110 unsigned long long TxIntMemBase;
111 unsigned long long TxIntMemSize;
112 unsigned long long Reserved5;
113 unsigned long long PCIeRBufTestReg0;
114 unsigned long long PCIeRBufTestReg1;
115 unsigned long long Reserved51[6];
116 unsigned long long SendBufferError;
117 unsigned long long SendBufferErrorCONT1;
118 unsigned long long Reserved6SBE[6];
119 unsigned long long RcvHdrAddr0;
120 unsigned long long RcvHdrAddr1;
121 unsigned long long RcvHdrAddr2;
122 unsigned long long RcvHdrAddr3;
123 unsigned long long RcvHdrAddr4;
124 unsigned long long Reserved7RHA[11];
125 unsigned long long RcvHdrTailAddr0;
126 unsigned long long RcvHdrTailAddr1;
127 unsigned long long RcvHdrTailAddr2;
128 unsigned long long RcvHdrTailAddr3;
129 unsigned long long RcvHdrTailAddr4;
130 unsigned long long Reserved8RHTA[11];
131 unsigned long long Reserved9SW[8];
132 unsigned long long SerdesConfig0;
133 unsigned long long SerdesConfig1;
134 unsigned long long SerdesStatus;
135 unsigned long long XGXSConfig;
136 unsigned long long IBPLLCfg;
137 unsigned long long Reserved10SW2[3];
138 unsigned long long PCIEQ0SerdesConfig0;
139 unsigned long long PCIEQ0SerdesConfig1;
140 unsigned long long PCIEQ0SerdesStatus;
141 unsigned long long Reserved11;
142 unsigned long long PCIEQ1SerdesConfig0;
143 unsigned long long PCIEQ1SerdesConfig1;
144 unsigned long long PCIEQ1SerdesStatus;
145 unsigned long long Reserved12;
146 };
147
148 struct _infinipath_do_not_use_counters {
149 __u64 LBIntCnt;
150 __u64 LBFlowStallCnt;
151 __u64 Reserved1;
152 __u64 TxUnsupVLErrCnt;
153 __u64 TxDataPktCnt;
154 __u64 TxFlowPktCnt;
155 __u64 TxDwordCnt;
156 __u64 TxLenErrCnt;
157 __u64 TxMaxMinLenErrCnt;
158 __u64 TxUnderrunCnt;
159 __u64 TxFlowStallCnt;
160 __u64 TxDroppedPktCnt;
161 __u64 RxDroppedPktCnt;
162 __u64 RxDataPktCnt;
163 __u64 RxFlowPktCnt;
164 __u64 RxDwordCnt;
165 __u64 RxLenErrCnt;
166 __u64 RxMaxMinLenErrCnt;
167 __u64 RxICRCErrCnt;
168 __u64 RxVCRCErrCnt;
169 __u64 RxFlowCtrlErrCnt;
170 __u64 RxBadFormatCnt;
171 __u64 RxLinkProblemCnt;
172 __u64 RxEBPCnt;
173 __u64 RxLPCRCErrCnt;
174 __u64 RxBufOvflCnt;
175 __u64 RxTIDFullErrCnt;
176 __u64 RxTIDValidErrCnt;
177 __u64 RxPKeyMismatchCnt;
178 __u64 RxP0HdrEgrOvflCnt;
179 __u64 RxP1HdrEgrOvflCnt;
180 __u64 RxP2HdrEgrOvflCnt;
181 __u64 RxP3HdrEgrOvflCnt;
182 __u64 RxP4HdrEgrOvflCnt;
183 __u64 RxP5HdrEgrOvflCnt;
184 __u64 RxP6HdrEgrOvflCnt;
185 __u64 RxP7HdrEgrOvflCnt;
186 __u64 RxP8HdrEgrOvflCnt;
187 __u64 Reserved6;
188 __u64 Reserved7;
189 __u64 IBStatusChangeCnt;
190 __u64 IBLinkErrRecoveryCnt;
191 __u64 IBLinkDownedCnt;
192 __u64 IBSymbolErrCnt;
193 };
194
195 #define IPATH_KREG_OFFSET(field) (offsetof( \
196 struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
197 #define IPATH_CREG_OFFSET(field) (offsetof( \
198 struct _infinipath_do_not_use_counters, field) / sizeof(u64))
199
200 static const struct ipath_kregs ipath_pe_kregs = {
201 .kr_control = IPATH_KREG_OFFSET(Control),
202 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
203 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
204 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
205 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
206 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
207 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
208 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
209 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
210 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
211 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
212 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
213 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
214 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
215 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
216 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
217 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
218 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
219 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
220 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
221 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
222 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
223 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
224 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
225 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
226 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
227 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
228 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
229 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
230 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
231 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
232 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
233 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
234 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
235 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
236 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
237 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
238 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
239 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
240 .kr_revision = IPATH_KREG_OFFSET(Revision),
241 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
242 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
243 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
244 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
245 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
246 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
247 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
248 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
249 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
250 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
251 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
252 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
253 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
254 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
255 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
256 .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
257
258 /*
259 * These should not be used directly via ipath_write_kreg64(),
260 * use them with ipath_write_kreg64_port(),
261 */
262 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
263 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
264
265 /* The rcvpktled register controls one of the debug port signals, so
266 * a packet activity LED can be connected to it. */
267 .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
268 .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
269 .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
270 .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
271 .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
272 .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
273 .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
274 .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
275 .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
276 };
277
278 static const struct ipath_cregs ipath_pe_cregs = {
279 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
280 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
281 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
282 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
283 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
284 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
285 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
286 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
287 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
288 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
289 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
290 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
291 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
292 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
293 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
294 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
295 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
296 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
297 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
298 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
299 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
300 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
301 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
302 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
303 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
304 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
305 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
306 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
307 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
308 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
309 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
310 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
311 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
312 };
313
314 /* kr_control bits */
315 #define INFINIPATH_C_RESET 1U
316
317 /* kr_intstatus, kr_intclear, kr_intmask bits */
318 #define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
319 #define INFINIPATH_I_RCVURG_SHIFT 0
320 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
321 #define INFINIPATH_I_RCVAVAIL_SHIFT 12
322
323 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
324 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK 0x000000000000003fULL
325 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
326 #define INFINIPATH_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
327 #define INFINIPATH_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
328 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
329 #define INFINIPATH_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
330 #define INFINIPATH_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
331 #define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
332 #define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
333 #define INFINIPATH_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
334 #define INFINIPATH_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
335 #define INFINIPATH_HWE_SERDESPLLFAILED 0x1000000000000000ULL
336
337 #define IBA6120_IBCS_LINKTRAININGSTATE_MASK 0xf
338 #define IBA6120_IBCS_LINKSTATE_SHIFT 4
339
340 /* kr_extstatus bits */
341 #define INFINIPATH_EXTS_FREQSEL 0x2
342 #define INFINIPATH_EXTS_SERDESSEL 0x4
343 #define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
344 #define INFINIPATH_EXTS_MEMBIST_FOUND 0x0000000000008000
345
346 /* kr_xgxsconfig bits */
347 #define INFINIPATH_XGXS_RESET 0x5ULL
348
349 #define _IPATH_GPIO_SDA_NUM 1
350 #define _IPATH_GPIO_SCL_NUM 0
351
352 #define IPATH_GPIO_SDA (1ULL << \
353 (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
354 #define IPATH_GPIO_SCL (1ULL << \
355 (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
356
357 #define INFINIPATH_RT_BUFSIZE_MASK 0xe0000000ULL
358 #define INFINIPATH_RT_BUFSIZE_SHIFTVAL(tid) \
359 ((((tid) & INFINIPATH_RT_BUFSIZE_MASK) >> 29) + 11 - 1)
360 #define INFINIPATH_RT_BUFSIZE(tid) (1 << INFINIPATH_RT_BUFSIZE_SHIFTVAL(tid))
361 #define INFINIPATH_RT_IS_VALID(tid) \
362 (((tid) & INFINIPATH_RT_BUFSIZE_MASK) && \
363 ((((tid) & INFINIPATH_RT_BUFSIZE_MASK) != INFINIPATH_RT_BUFSIZE_MASK)))
364 #define INFINIPATH_RT_ADDR_MASK 0x1FFFFFFFULL /* 29 bits valid */
365 #define INFINIPATH_RT_ADDR_SHIFT 10
366
367 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
368 #define INFINIPATH_R_TAILUPD_SHIFT 31
369
370 /* 6120 specific hardware errors... */
371 static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
372 INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
373 INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
374 /*
375 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
376 * parity or memory parity error failures, because most likely we
377 * won't be able to talk to the core of the chip. Nonetheless, we
378 * might see them, if they are in parts of the PCIe core that aren't
379 * essential.
380 */
381 INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
382 INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
383 INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
384 INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
385 INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
386 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
387 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
388 };
389
390 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
391 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
392 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
393 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
394 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
395
396 static void ipath_pe_put_tid_2(struct ipath_devdata *, u64 __iomem *,
397 u32, unsigned long);
398
399 /*
400 * On platforms using this chip, and not having ordered WC stores, we
401 * can get TXE parity errors due to speculative reads to the PIO buffers,
402 * and this, due to a chip bug can result in (many) false parity error
403 * reports. So it's a debug print on those, and an info print on systems
404 * where the speculative reads don't occur.
405 */
406 static void ipath_pe_txe_recover(struct ipath_devdata *dd)
407 {
408 if (ipath_unordered_wc())
409 ipath_dbg("Recovering from TXE PIO parity error\n");
410 else {
411 ++ipath_stats.sps_txeparity;
412 dev_info(&dd->pcidev->dev,
413 "Recovering from TXE PIO parity error\n");
414 }
415 }
416
417
418 /**
419 * ipath_pe_handle_hwerrors - display hardware errors.
420 * @dd: the infinipath device
421 * @msg: the output buffer
422 * @msgl: the size of the output buffer
423 *
424 * Use same msg buffer as regular errors to avoid excessive stack
425 * use. Most hardware errors are catastrophic, but for right now,
426 * we'll print them and continue. We reuse the same message buffer as
427 * ipath_handle_errors() to avoid excessive stack usage.
428 */
429 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
430 size_t msgl)
431 {
432 ipath_err_t hwerrs;
433 u32 bits, ctrl;
434 int isfatal = 0;
435 char bitsmsg[64];
436 int log_idx;
437
438 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
439 if (!hwerrs) {
440 /*
441 * better than printing cofusing messages
442 * This seems to be related to clearing the crc error, or
443 * the pll error during init.
444 */
445 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
446 return;
447 } else if (hwerrs == ~0ULL) {
448 ipath_dev_err(dd, "Read of hardware error status failed "
449 "(all bits set); ignoring\n");
450 return;
451 }
452 ipath_stats.sps_hwerrs++;
453
454 /* Always clear the error status register, except MEMBISTFAIL,
455 * regardless of whether we continue or stop using the chip.
456 * We want that set so we know it failed, even across driver reload.
457 * We'll still ignore it in the hwerrmask. We do this partly for
458 * diagnostics, but also for support */
459 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
460 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
461
462 hwerrs &= dd->ipath_hwerrmask;
463
464 /* We log some errors to EEPROM, check if we have any of those. */
465 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
466 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
467 ipath_inc_eeprom_err(dd, log_idx, 1);
468
469 /*
470 * make sure we get this much out, unless told to be quiet,
471 * or it's occurred within the last 5 seconds
472 */
473 if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
474 RXE_EAGER_PARITY)) ||
475 (ipath_debug & __IPATH_VERBDBG))
476 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
477 "(cleared)\n", (unsigned long long) hwerrs);
478 dd->ipath_lasthwerror |= hwerrs;
479
480 if (hwerrs & ~dd->ipath_hwe_bitsextant)
481 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
482 "%llx set\n", (unsigned long long)
483 (hwerrs & ~dd->ipath_hwe_bitsextant));
484
485 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
486 if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
487 /*
488 * parity errors in send memory are recoverable,
489 * just cancel the send (if indicated in * sendbuffererror),
490 * count the occurrence, unfreeze (if no other handled
491 * hardware error bits are set), and continue. They can
492 * occur if a processor speculative read is done to the PIO
493 * buffer while we are sending a packet, for example.
494 */
495 if (hwerrs & TXE_PIO_PARITY) {
496 ipath_pe_txe_recover(dd);
497 hwerrs &= ~TXE_PIO_PARITY;
498 }
499 if (!hwerrs) {
500 static u32 freeze_cnt;
501
502 freeze_cnt++;
503 ipath_dbg("Clearing freezemode on ignored or recovered "
504 "hardware error (%u)\n", freeze_cnt);
505 ipath_clear_freeze(dd);
506 }
507 }
508
509 *msg = '\0';
510
511 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
512 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
513 msgl);
514 /* ignore from now on, so disable until driver reloaded */
515 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
516 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
517 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
518 dd->ipath_hwerrmask);
519 }
520
521 ipath_format_hwerrors(hwerrs,
522 ipath_6120_hwerror_msgs,
523 sizeof(ipath_6120_hwerror_msgs)/
524 sizeof(ipath_6120_hwerror_msgs[0]),
525 msg, msgl);
526
527 if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
528 << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
529 bits = (u32) ((hwerrs >>
530 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
531 INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
532 snprintf(bitsmsg, sizeof bitsmsg,
533 "[PCIe Mem Parity Errs %x] ", bits);
534 strlcat(msg, bitsmsg, msgl);
535 }
536
537 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
538 INFINIPATH_HWE_COREPLL_RFSLIP )
539
540 if (hwerrs & _IPATH_PLL_FAIL) {
541 snprintf(bitsmsg, sizeof bitsmsg,
542 "[PLL failed (%llx), InfiniPath hardware unusable]",
543 (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
544 strlcat(msg, bitsmsg, msgl);
545 /* ignore from now on, so disable until driver reloaded */
546 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
547 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
548 dd->ipath_hwerrmask);
549 }
550
551 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
552 /*
553 * If it occurs, it is left masked since the external
554 * interface is unused
555 */
556 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
557 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
558 dd->ipath_hwerrmask);
559 }
560
561 if (hwerrs) {
562 /*
563 * if any set that we aren't ignoring; only
564 * make the complaint once, in case it's stuck
565 * or recurring, and we get here multiple
566 * times.
567 */
568 ipath_dev_err(dd, "%s hardware error\n", msg);
569 if (dd->ipath_flags & IPATH_INITTED) {
570 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
571 ipath_setup_pe_setextled(dd,
572 INFINIPATH_IBCS_L_STATE_DOWN,
573 INFINIPATH_IBCS_LT_STATE_DISABLED);
574 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
575 "mode), no longer usable, SN %.16s\n",
576 dd->ipath_serial);
577 isfatal = 1;
578 }
579 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
580 /* mark as having had error */
581 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
582 /*
583 * mark as not usable, at a minimum until driver
584 * is reloaded, probably until reboot, since no
585 * other reset is possible.
586 */
587 dd->ipath_flags &= ~IPATH_INITTED;
588 } else
589 *msg = 0; /* recovered from all of them */
590
591 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg && msg) {
592 /*
593 * for /sys status file ; if no trailing brace is copied,
594 * we'll know it was truncated.
595 */
596 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
597 "{%s}", msg);
598 }
599 }
600
601 /**
602 * ipath_pe_boardname - fill in the board name
603 * @dd: the infinipath device
604 * @name: the output buffer
605 * @namelen: the size of the output buffer
606 *
607 * info is based on the board revision register
608 */
609 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
610 size_t namelen)
611 {
612 char *n = NULL;
613 u8 boardrev = dd->ipath_boardrev;
614 int ret;
615
616 switch (boardrev) {
617 case 0:
618 n = "InfiniPath_Emulation";
619 break;
620 case 1:
621 n = "InfiniPath_QLE7140-Bringup";
622 break;
623 case 2:
624 n = "InfiniPath_QLE7140";
625 break;
626 case 3:
627 n = "InfiniPath_QMI7140";
628 break;
629 case 4:
630 n = "InfiniPath_QEM7140";
631 break;
632 case 5:
633 n = "InfiniPath_QMH7140";
634 break;
635 case 6:
636 n = "InfiniPath_QLE7142";
637 break;
638 default:
639 ipath_dev_err(dd,
640 "Don't yet know about board with ID %u\n",
641 boardrev);
642 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
643 boardrev);
644 break;
645 }
646 if (n)
647 snprintf(name, namelen, "%s", n);
648
649 if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
650 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
651 dd->ipath_majrev, dd->ipath_minrev);
652 ret = 1;
653 } else {
654 ret = 0;
655 if (dd->ipath_minrev >= 2)
656 dd->ipath_f_put_tid = ipath_pe_put_tid_2;
657 }
658
659 /*
660 * set here, not in ipath_init_*_funcs because we have to do
661 * it after we can read chip registers.
662 */
663 dd->ipath_ureg_align =
664 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
665
666 return ret;
667 }
668
669 /**
670 * ipath_pe_init_hwerrors - enable hardware errors
671 * @dd: the infinipath device
672 *
673 * now that we have finished initializing everything that might reasonably
674 * cause a hardware error, and cleared those errors bits as they occur,
675 * we can enable hardware errors in the mask (potentially enabling
676 * freeze mode), and enable hardware errors as errors (along with
677 * everything else) in errormask
678 */
679 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
680 {
681 ipath_err_t val;
682 u64 extsval;
683
684 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
685
686 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
687 ipath_dev_err(dd, "MemBIST did not complete!\n");
688 if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
689 ipath_dbg("MemBIST corrected\n");
690
691 val = ~0ULL; /* barring bugs, all hwerrors become interrupts, */
692
693 if (!dd->ipath_boardrev) // no PLL for Emulator
694 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
695
696 if (dd->ipath_minrev < 2) {
697 /* workaround bug 9460 in internal interface bus parity
698 * checking. Fixed (HW bug 9490) in Rev2.
699 */
700 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
701 }
702 dd->ipath_hwerrmask = val;
703 }
704
705 /**
706 * ipath_pe_bringup_serdes - bring up the serdes
707 * @dd: the infinipath device
708 */
709 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
710 {
711 u64 val, config1, prev_val;
712 int ret = 0;
713
714 ipath_dbg("Trying to bringup serdes\n");
715
716 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
717 INFINIPATH_HWE_SERDESPLLFAILED) {
718 ipath_dbg("At start, serdes PLL failed bit set "
719 "in hwerrstatus, clearing and continuing\n");
720 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
721 INFINIPATH_HWE_SERDESPLLFAILED);
722 }
723
724 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
725 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
726
727 ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
728 "xgxsconfig %llx\n", (unsigned long long) val,
729 (unsigned long long) config1, (unsigned long long)
730 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
731
732 /*
733 * Force reset on, also set rxdetect enable. Must do before reading
734 * serdesstatus at least for simulation, or some of the bits in
735 * serdes status will come back as undefined and cause simulation
736 * failures
737 */
738 val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
739 | INFINIPATH_SERDC0_L1PWR_DN;
740 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
741 /* be sure chip saw it */
742 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
743 udelay(5); /* need pll reset set at least for a bit */
744 /*
745 * after PLL is reset, set the per-lane Resets and TxIdle and
746 * clear the PLL reset and rxdetect (to get falling edge).
747 * Leave L1PWR bits set (permanently)
748 */
749 val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
750 | INFINIPATH_SERDC0_L1PWR_DN);
751 val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
752 ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
753 "and txidle (%llx)\n", (unsigned long long) val);
754 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
755 /* be sure chip saw it */
756 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
757 /* need PLL reset clear for at least 11 usec before lane
758 * resets cleared; give it a few more to be sure */
759 udelay(15);
760 val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
761
762 ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
763 "(writing %llx)\n", (unsigned long long) val);
764 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
765 /* be sure chip saw it */
766 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
767
768 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
769 prev_val = val;
770 if (val & INFINIPATH_XGXS_RESET)
771 val &= ~INFINIPATH_XGXS_RESET;
772 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
773 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
774 /* need to compensate for Tx inversion in partner */
775 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
776 INFINIPATH_XGXS_RX_POL_SHIFT);
777 val |= dd->ipath_rx_pol_inv <<
778 INFINIPATH_XGXS_RX_POL_SHIFT;
779 }
780 if (val != prev_val)
781 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
782
783 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
784
785 /* clear current and de-emphasis bits */
786 config1 &= ~0x0ffffffff00ULL;
787 /* set current to 20ma */
788 config1 |= 0x00000000000ULL;
789 /* set de-emphasis to -5.68dB */
790 config1 |= 0x0cccc000000ULL;
791 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
792
793 ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
794 "config1=%llx, sstatus=%llx xgxs=%llx\n",
795 (unsigned long long) val, (unsigned long long) config1,
796 (unsigned long long)
797 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
798 (unsigned long long)
799 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
800
801 return ret;
802 }
803
804 /**
805 * ipath_pe_quiet_serdes - set serdes to txidle
806 * @dd: the infinipath device
807 * Called when driver is being unloaded
808 */
809 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
810 {
811 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
812
813 val |= INFINIPATH_SERDC0_TXIDLE;
814 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
815 (unsigned long long) val);
816 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
817 }
818
819 static int ipath_pe_intconfig(struct ipath_devdata *dd)
820 {
821 u32 chiprev;
822
823 /*
824 * If the chip supports added error indication via GPIO pins,
825 * enable interrupts on those bits so the interrupt routine
826 * can count the events. Also set flag so interrupt routine
827 * can know they are expected.
828 */
829 chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
830 if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
831 /* Rev2+ reports extra errors via internal GPIO pins */
832 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
833 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
834 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
835 dd->ipath_gpio_mask);
836 }
837 return 0;
838 }
839
840 /**
841 * ipath_setup_pe_setextled - set the state of the two external LEDs
842 * @dd: the infinipath device
843 * @lst: the L state
844 * @ltst: the LT state
845
846 * These LEDs indicate the physical and logical state of IB link.
847 * For this chip (at least with recommended board pinouts), LED1
848 * is Yellow (logical state) and LED2 is Green (physical state),
849 *
850 * Note: We try to match the Mellanox HCA LED behavior as best
851 * we can. Green indicates physical link state is OK (something is
852 * plugged in, and we can train).
853 * Amber indicates the link is logically up (ACTIVE).
854 * Mellanox further blinks the amber LED to indicate data packet
855 * activity, but we have no hardware support for that, so it would
856 * require waking up every 10-20 msecs and checking the counters
857 * on the chip, and then turning the LED off if appropriate. That's
858 * visible overhead, so not something we will do.
859 *
860 */
861 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
862 u64 ltst)
863 {
864 u64 extctl;
865 unsigned long flags = 0;
866
867 /* the diags use the LED to indicate diag info, so we leave
868 * the external LED alone when the diags are running */
869 if (ipath_diag_inuse)
870 return;
871
872 /* Allow override of LED display for, e.g. Locating system in rack */
873 if (dd->ipath_led_override) {
874 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
875 ? INFINIPATH_IBCS_LT_STATE_LINKUP
876 : INFINIPATH_IBCS_LT_STATE_DISABLED;
877 lst = (dd->ipath_led_override & IPATH_LED_LOG)
878 ? INFINIPATH_IBCS_L_STATE_ACTIVE
879 : INFINIPATH_IBCS_L_STATE_DOWN;
880 }
881
882 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
883 extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
884 INFINIPATH_EXTC_LED2PRIPORT_ON);
885
886 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
887 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
888 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
889 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
890 dd->ipath_extctrl = extctl;
891 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
892 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
893 }
894
895 /**
896 * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
897 * @dd: the infinipath device
898 *
899 * This is called during driver unload.
900 * We do the pci_disable_msi here, not in generic code, because it
901 * isn't used for the HT chips. If we do end up needing pci_enable_msi
902 * at some point in the future for HT, we'll move the call back
903 * into the main init_one code.
904 */
905 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
906 {
907 dd->ipath_msi_lo = 0; /* just in case unload fails */
908 pci_disable_msi(dd->pcidev);
909 }
910
911 static void ipath_6120_pcie_params(struct ipath_devdata *dd)
912 {
913 u16 linkstat, speed;
914 int pos;
915
916 pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP);
917 if (!pos) {
918 ipath_dev_err(dd, "Can't find PCI Express capability!\n");
919 goto bail;
920 }
921
922 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
923 &linkstat);
924 /*
925 * speed is bits 0-4, linkwidth is bits 4-8
926 * no defines for them in headers
927 */
928 speed = linkstat & 0xf;
929 linkstat >>= 4;
930 linkstat &= 0x1f;
931 dd->ipath_lbus_width = linkstat;
932
933 switch (speed) {
934 case 1:
935 dd->ipath_lbus_speed = 2500; /* Gen1, 2.5GHz */
936 break;
937 case 2:
938 dd->ipath_lbus_speed = 5000; /* Gen1, 5GHz */
939 break;
940 default: /* not defined, assume gen1 */
941 dd->ipath_lbus_speed = 2500;
942 break;
943 }
944
945 if (linkstat < 8)
946 ipath_dev_err(dd,
947 "PCIe width %u (x8 HCA), performance reduced\n",
948 linkstat);
949 else
950 ipath_cdbg(VERBOSE, "PCIe speed %u width %u (x8 HCA)\n",
951 dd->ipath_lbus_speed, linkstat);
952
953 if (speed != 1)
954 ipath_dev_err(dd,
955 "PCIe linkspeed %u is incorrect; "
956 "should be 1 (2500)!\n", speed);
957 bail:
958 /* fill in string, even on errors */
959 snprintf(dd->ipath_lbus_info, sizeof(dd->ipath_lbus_info),
960 "PCIe,%uMHz,x%u\n",
961 dd->ipath_lbus_speed,
962 dd->ipath_lbus_width);
963
964 return;
965 }
966
967 /**
968 * ipath_setup_pe_config - setup PCIe config related stuff
969 * @dd: the infinipath device
970 * @pdev: the PCI device
971 *
972 * The pci_enable_msi() call will fail on systems with MSI quirks
973 * such as those with AMD8131, even if the device of interest is not
974 * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
975 * late in 2.6.16).
976 * All that can be done is to edit the kernel source to remove the quirk
977 * check until that is fixed.
978 * We do not need to call enable_msi() for our HyperTransport chip,
979 * even though it uses MSI, and we want to avoid the quirk warning, so
980 * So we call enable_msi only for PCIe. If we do end up needing
981 * pci_enable_msi at some point in the future for HT, we'll move the
982 * call back into the main init_one code.
983 * We save the msi lo and hi values, so we can restore them after
984 * chip reset (the kernel PCI infrastructure doesn't yet handle that
985 * correctly).
986 */
987 static int ipath_setup_pe_config(struct ipath_devdata *dd,
988 struct pci_dev *pdev)
989 {
990 int pos, ret;
991
992 dd->ipath_msi_lo = 0; /* used as a flag during reset processing */
993 ret = pci_enable_msi(dd->pcidev);
994 if (ret)
995 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
996 "interrupts may not work\n", ret);
997 /* continue even if it fails, we may still be OK... */
998 dd->ipath_irq = pdev->irq;
999
1000 if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1001 u16 control;
1002 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1003 &dd->ipath_msi_lo);
1004 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1005 &dd->ipath_msi_hi);
1006 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1007 &control);
1008 /* now save the data (vector) info */
1009 pci_read_config_word(dd->pcidev,
1010 pos + ((control & PCI_MSI_FLAGS_64BIT)
1011 ? 12 : 8),
1012 &dd->ipath_msi_data);
1013 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
1014 "0x%x, control=0x%x\n", dd->ipath_msi_data,
1015 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1016 control);
1017 /* we save the cachelinesize also, although it doesn't
1018 * really matter */
1019 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1020 &dd->ipath_pci_cacheline);
1021 } else
1022 ipath_dev_err(dd, "Can't find MSI capability, "
1023 "can't save MSI settings for reset\n");
1024
1025 ipath_6120_pcie_params(dd);
1026
1027 dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
1028 dd->ipath_link_speed_supported = IPATH_IB_SDR;
1029 dd->ipath_link_width_enabled = IB_WIDTH_4X;
1030 dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported;
1031 /* these can't change for this chip, so set once */
1032 dd->ipath_link_width_active = dd->ipath_link_width_enabled;
1033 dd->ipath_link_speed_active = dd->ipath_link_speed_enabled;
1034 return 0;
1035 }
1036
1037 static void ipath_init_pe_variables(struct ipath_devdata *dd)
1038 {
1039 /*
1040 * setup the register offsets, since they are different for each
1041 * chip
1042 */
1043 dd->ipath_kregs = &ipath_pe_kregs;
1044 dd->ipath_cregs = &ipath_pe_cregs;
1045
1046 /*
1047 * bits for selecting i2c direction and values,
1048 * used for I2C serial flash
1049 */
1050 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1051 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1052 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1053 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1054
1055 /*
1056 * Fill in data for field-values that change in newer chips.
1057 * We dynamically specify only the mask for LINKTRAININGSTATE
1058 * and only the shift for LINKSTATE, as they are the only ones
1059 * that change. Also precalculate the 3 link states of interest
1060 * and the combined mask.
1061 */
1062 dd->ibcs_ls_shift = IBA6120_IBCS_LINKSTATE_SHIFT;
1063 dd->ibcs_lts_mask = IBA6120_IBCS_LINKTRAININGSTATE_MASK;
1064 dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK <<
1065 dd->ibcs_ls_shift) | dd->ibcs_lts_mask;
1066 dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1067 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1068 (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift);
1069 dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1070 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1071 (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift);
1072 dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1073 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1074 (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift);
1075
1076 /*
1077 * Fill in data for ibcc field-values that change in newer chips.
1078 * We dynamically specify only the mask for LINKINITCMD
1079 * and only the shift for LINKCMD and MAXPKTLEN, as they are
1080 * the only ones that change.
1081 */
1082 dd->ibcc_lic_mask = INFINIPATH_IBCC_LINKINITCMD_MASK;
1083 dd->ibcc_lc_shift = INFINIPATH_IBCC_LINKCMD_SHIFT;
1084 dd->ibcc_mpl_shift = INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
1085
1086 /* Fill in shifts for RcvCtrl. */
1087 dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1088 dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
1089 dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
1090 dd->ipath_r_portcfg_shift = 0; /* Not on IBA6120 */
1091
1092 /* variables for sanity checking interrupt and errors */
1093 dd->ipath_hwe_bitsextant =
1094 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1095 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1096 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1097 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1098 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
1099 INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
1100 INFINIPATH_HWE_PCIE1PLLFAILED |
1101 INFINIPATH_HWE_PCIE0PLLFAILED |
1102 INFINIPATH_HWE_PCIEPOISONEDTLP |
1103 INFINIPATH_HWE_PCIECPLTIMEOUT |
1104 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
1105 INFINIPATH_HWE_PCIEBUSPARITYXADM |
1106 INFINIPATH_HWE_PCIEBUSPARITYRADM |
1107 INFINIPATH_HWE_MEMBISTFAILED |
1108 INFINIPATH_HWE_COREPLL_FBSLIP |
1109 INFINIPATH_HWE_COREPLL_RFSLIP |
1110 INFINIPATH_HWE_SERDESPLLFAILED |
1111 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1112 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1113 dd->ipath_i_bitsextant =
1114 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1115 (INFINIPATH_I_RCVAVAIL_MASK <<
1116 INFINIPATH_I_RCVAVAIL_SHIFT) |
1117 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1118 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1119 dd->ipath_e_bitsextant =
1120 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1121 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1122 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1123 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1124 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1125 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1126 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1127 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1128 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1129 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1130 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1131 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1132 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1133 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1134 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1135 INFINIPATH_E_HARDWARE;
1136
1137 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1138 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1139 dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT;
1140 dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT;
1141
1142 /*
1143 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1144 * 2 is Some Misc, 3 is reserved for future.
1145 */
1146 dd->ipath_eep_st_masks[0].hwerrs_to_log =
1147 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1148 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1149
1150 /* Ignore errors in PIO/PBC on systems with unordered write-combining */
1151 if (ipath_unordered_wc())
1152 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
1153
1154 dd->ipath_eep_st_masks[1].hwerrs_to_log =
1155 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1156 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1157
1158 dd->ipath_eep_st_masks[2].errs_to_log = INFINIPATH_E_RESET;
1159 dd->delay_mult = 2; /* SDR, 4X, can't change */
1160 }
1161
1162 /* setup the MSI stuff again after a reset. I'd like to just call
1163 * pci_enable_msi() and request_irq() again, but when I do that,
1164 * the MSI enable bit doesn't get set in the command word, and
1165 * we switch to to a different interrupt vector, which is confusing,
1166 * so I instead just do it all inline. Perhaps somehow can tie this
1167 * into the PCIe hotplug support at some point
1168 * Note, because I'm doing it all here, I don't call pci_disable_msi()
1169 * or free_irq() at the start of ipath_setup_pe_reset().
1170 */
1171 static int ipath_reinit_msi(struct ipath_devdata *dd)
1172 {
1173 int pos;
1174 u16 control;
1175 int ret;
1176
1177 if (!dd->ipath_msi_lo) {
1178 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
1179 "initial setup failed?\n");
1180 ret = 0;
1181 goto bail;
1182 }
1183
1184 if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1185 ipath_dev_err(dd, "Can't find MSI capability, "
1186 "can't restore MSI settings\n");
1187 ret = 0;
1188 goto bail;
1189 }
1190 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1191 dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1192 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1193 dd->ipath_msi_lo);
1194 ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1195 dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1196 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1197 dd->ipath_msi_hi);
1198 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1199 if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1200 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1201 "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1202 control, control | PCI_MSI_FLAGS_ENABLE);
1203 control |= PCI_MSI_FLAGS_ENABLE;
1204 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1205 control);
1206 }
1207 /* now rewrite the data (vector) info */
1208 pci_write_config_word(dd->pcidev, pos +
1209 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1210 dd->ipath_msi_data);
1211 /* we restore the cachelinesize also, although it doesn't really
1212 * matter */
1213 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1214 dd->ipath_pci_cacheline);
1215 /* and now set the pci master bit again */
1216 pci_set_master(dd->pcidev);
1217 ret = 1;
1218
1219 bail:
1220 return ret;
1221 }
1222
1223 /* This routine sleeps, so it can only be called from user context, not
1224 * from interrupt context. If we need interrupt context, we can split
1225 * it into two routines.
1226 */
1227 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1228 {
1229 u64 val;
1230 int i;
1231 int ret;
1232 u16 cmdval;
1233
1234 pci_read_config_word(dd->pcidev, PCI_COMMAND, &cmdval);
1235
1236 /* Use ERROR so it shows up in logs, etc. */
1237 ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1238 /* keep chip from being accessed in a few places */
1239 dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1240 val = dd->ipath_control | INFINIPATH_C_RESET;
1241 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1242 mb();
1243
1244 for (i = 1; i <= 5; i++) {
1245 int r;
1246 /* allow MBIST, etc. to complete; longer on each retry.
1247 * We sometimes get machine checks from bus timeout if no
1248 * response, so for now, make it *really* long.
1249 */
1250 msleep(1000 + (1 + i) * 2000);
1251 if ((r =
1252 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1253 dd->ipath_pcibar0)))
1254 ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1255 r);
1256 if ((r =
1257 pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1258 dd->ipath_pcibar1)))
1259 ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1260 r);
1261 /* now re-enable memory access */
1262 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmdval);
1263 if ((r = pci_enable_device(dd->pcidev)))
1264 ipath_dev_err(dd, "pci_enable_device failed after "
1265 "reset: %d\n", r);
1266 /*
1267 * whether it fully enabled or not, mark as present,
1268 * again (but not INITTED)
1269 */
1270 dd->ipath_flags |= IPATH_PRESENT;
1271 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1272 if (val == dd->ipath_revision) {
1273 ipath_cdbg(VERBOSE, "Got matching revision "
1274 "register %llx on try %d\n",
1275 (unsigned long long) val, i);
1276 ret = ipath_reinit_msi(dd);
1277 goto bail;
1278 }
1279 /* Probably getting -1 back */
1280 ipath_dbg("Didn't get expected revision register, "
1281 "got %llx, try %d\n", (unsigned long long) val,
1282 i + 1);
1283 }
1284 ret = 0; /* failed */
1285
1286 bail:
1287 if (ret)
1288 ipath_6120_pcie_params(dd);
1289 return ret;
1290 }
1291
1292 /**
1293 * ipath_pe_put_tid - write a TID in chip
1294 * @dd: the infinipath device
1295 * @tidptr: pointer to the expected TID (in chip) to udpate
1296 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1297 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1298 *
1299 * This exists as a separate routine to allow for special locking etc.
1300 * It's used for both the full cleanup on exit, as well as the normal
1301 * setup and teardown.
1302 */
1303 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1304 u32 type, unsigned long pa)
1305 {
1306 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1307 unsigned long flags = 0; /* keep gcc quiet */
1308 int tidx;
1309 spinlock_t *tidlockp;
1310
1311 if (!dd->ipath_kregbase)
1312 return;
1313
1314 if (pa != dd->ipath_tidinvalid) {
1315 if (pa & ((1U << 11) - 1)) {
1316 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1317 "not 2KB aligned!\n", pa);
1318 return;
1319 }
1320 pa >>= 11;
1321 /* paranoia check */
1322 if (pa & ~INFINIPATH_RT_ADDR_MASK)
1323 ipath_dev_err(dd,
1324 "BUG: Physical page address 0x%lx "
1325 "has bits set in 31-29\n", pa);
1326
1327 if (type == RCVHQ_RCV_TYPE_EAGER)
1328 pa |= dd->ipath_tidtemplate;
1329 else /* for now, always full 4KB page */
1330 pa |= 2 << 29;
1331 }
1332
1333 /*
1334 * Workaround chip bug 9437 by writing the scratch register
1335 * before and after the TID, and with an io write barrier.
1336 * We use a spinlock around the writes, so they can't intermix
1337 * with other TID (eager or expected) writes (the chip bug
1338 * is triggered by back to back TID writes). Unfortunately, this
1339 * call can be done from interrupt level for the port 0 eager TIDs,
1340 * so we have to use irqsave locks.
1341 */
1342 /*
1343 * Assumes tidptr always > ipath_egrtidbase
1344 * if type == RCVHQ_RCV_TYPE_EAGER.
1345 */
1346 tidx = tidptr - dd->ipath_egrtidbase;
1347
1348 tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->ipath_rcvegrcnt)
1349 ? &dd->ipath_kernel_tid_lock : &dd->ipath_user_tid_lock;
1350 spin_lock_irqsave(tidlockp, flags);
1351 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1352 writel(pa, tidp32);
1353 ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1354 mmiowb();
1355 spin_unlock_irqrestore(tidlockp, flags);
1356 }
1357
1358 /**
1359 * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1360 * @dd: the infinipath device
1361 * @tidptr: pointer to the expected TID (in chip) to udpate
1362 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1363 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1364 *
1365 * This exists as a separate routine to allow for selection of the
1366 * appropriate "flavor". The static calls in cleanup just use the
1367 * revision-agnostic form, as they are not performance critical.
1368 */
1369 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1370 u32 type, unsigned long pa)
1371 {
1372 u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1373 u32 tidx;
1374
1375 if (!dd->ipath_kregbase)
1376 return;
1377
1378 if (pa != dd->ipath_tidinvalid) {
1379 if (pa & ((1U << 11) - 1)) {
1380 dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1381 "not 2KB aligned!\n", pa);
1382 return;
1383 }
1384 pa >>= 11;
1385 /* paranoia check */
1386 if (pa & ~INFINIPATH_RT_ADDR_MASK)
1387 ipath_dev_err(dd,
1388 "BUG: Physical page address 0x%lx "
1389 "has bits set in 31-29\n", pa);
1390
1391 if (type == RCVHQ_RCV_TYPE_EAGER)
1392 pa |= dd->ipath_tidtemplate;
1393 else /* for now, always full 4KB page */
1394 pa |= 2 << 29;
1395 }
1396 tidx = tidptr - dd->ipath_egrtidbase;
1397 writel(pa, tidp32);
1398 mmiowb();
1399 }
1400
1401
1402 /**
1403 * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1404 * @dd: the infinipath device
1405 * @port: the port
1406 *
1407 * clear all TID entries for a port, expected and eager.
1408 * Used from ipath_close(). On this chip, TIDs are only 32 bits,
1409 * not 64, but they are still on 64 bit boundaries, so tidbase
1410 * is declared as u64 * for the pointer math, even though we write 32 bits
1411 */
1412 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1413 {
1414 u64 __iomem *tidbase;
1415 unsigned long tidinv;
1416 int i;
1417
1418 if (!dd->ipath_kregbase)
1419 return;
1420
1421 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1422
1423 tidinv = dd->ipath_tidinvalid;
1424 tidbase = (u64 __iomem *)
1425 ((char __iomem *)(dd->ipath_kregbase) +
1426 dd->ipath_rcvtidbase +
1427 port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1428
1429 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1430 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1431 tidinv);
1432
1433 tidbase = (u64 __iomem *)
1434 ((char __iomem *)(dd->ipath_kregbase) +
1435 dd->ipath_rcvegrbase +
1436 port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1437
1438 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1439 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1440 tidinv);
1441 }
1442
1443 /**
1444 * ipath_pe_tidtemplate - setup constants for TID updates
1445 * @dd: the infinipath device
1446 *
1447 * We setup stuff that we use a lot, to avoid calculating each time
1448 */
1449 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1450 {
1451 u32 egrsize = dd->ipath_rcvegrbufsize;
1452
1453 /* For now, we always allocate 4KB buffers (at init) so we can
1454 * receive max size packets. We may want a module parameter to
1455 * specify 2KB or 4KB and/or make be per port instead of per device
1456 * for those who want to reduce memory footprint. Note that the
1457 * ipath_rcvhdrentsize size must be large enough to hold the largest
1458 * IB header (currently 96 bytes) that we expect to handle (plus of
1459 * course the 2 dwords of RHF).
1460 */
1461 if (egrsize == 2048)
1462 dd->ipath_tidtemplate = 1U << 29;
1463 else if (egrsize == 4096)
1464 dd->ipath_tidtemplate = 2U << 29;
1465 else {
1466 egrsize = 4096;
1467 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1468 "%u, using %u\n", dd->ipath_rcvegrbufsize,
1469 egrsize);
1470 dd->ipath_tidtemplate = 2U << 29;
1471 }
1472 dd->ipath_tidinvalid = 0;
1473 }
1474
1475 static int ipath_pe_early_init(struct ipath_devdata *dd)
1476 {
1477 dd->ipath_flags |= IPATH_4BYTE_TID;
1478 if (ipath_unordered_wc())
1479 dd->ipath_flags |= IPATH_PIO_FLUSH_WC;
1480
1481 /*
1482 * For openfabrics, we need to be able to handle an IB header of
1483 * 24 dwords. HT chip has arbitrary sized receive buffers, so we
1484 * made them the same size as the PIO buffers. This chip does not
1485 * handle arbitrary size buffers, so we need the header large enough
1486 * to handle largest IB header, but still have room for a 2KB MTU
1487 * standard IB packet.
1488 */
1489 dd->ipath_rcvhdrentsize = 24;
1490 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1491 dd->ipath_rhf_offset = 0;
1492 dd->ipath_egrtidbase = (u64 __iomem *)
1493 ((char __iomem *) dd->ipath_kregbase + dd->ipath_rcvegrbase);
1494
1495 dd->ipath_rcvegrbufsize = ipath_mtu4096 ? 4096 : 2048;
1496 /*
1497 * the min() check here is currently a nop, but it may not always
1498 * be, depending on just how we do ipath_rcvegrbufsize
1499 */
1500 dd->ipath_ibmaxlen = min(ipath_mtu4096 ? dd->ipath_piosize4k :
1501 dd->ipath_piosize2k,
1502 dd->ipath_rcvegrbufsize +
1503 (dd->ipath_rcvhdrentsize << 2));
1504 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1505
1506 /*
1507 * We can request a receive interrupt for 1 or
1508 * more packets from current offset. For now, we set this
1509 * up for a single packet.
1510 */
1511 dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1512
1513 ipath_get_eeprom_info(dd);
1514
1515 return 0;
1516 }
1517
1518 int __attribute__((weak)) ipath_unordered_wc(void)
1519 {
1520 return 0;
1521 }
1522
1523 /**
1524 * ipath_init_pe_get_base_info - set chip-specific flags for user code
1525 * @pd: the infinipath port
1526 * @kbase: ipath_base_info pointer
1527 *
1528 * We set the PCIE flag because the lower bandwidth on PCIe vs
1529 * HyperTransport can affect some user packet algorithms.
1530 */
1531 static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1532 {
1533 struct ipath_base_info *kinfo = kbase;
1534 struct ipath_devdata *dd;
1535
1536 if (ipath_unordered_wc()) {
1537 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1538 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1539 }
1540 else
1541 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1542
1543 if (pd == NULL)
1544 goto done;
1545
1546 dd = pd->port_dd;
1547
1548 done:
1549 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE |
1550 IPATH_RUNTIME_FORCE_PIOAVAIL | IPATH_RUNTIME_PIO_REGSWAPPED;
1551 return 0;
1552 }
1553
1554 static void ipath_pe_free_irq(struct ipath_devdata *dd)
1555 {
1556 free_irq(dd->ipath_irq, dd);
1557 dd->ipath_irq = 0;
1558 }
1559
1560
1561 static struct ipath_message_header *
1562 ipath_pe_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr)
1563 {
1564 return (struct ipath_message_header *)
1565 &rhf_addr[sizeof(u64) / sizeof(u32)];
1566 }
1567
1568 static void ipath_pe_config_ports(struct ipath_devdata *dd, ushort cfgports)
1569 {
1570 dd->ipath_portcnt =
1571 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1572 dd->ipath_p0_rcvegrcnt =
1573 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
1574 }
1575
1576 static void ipath_pe_read_counters(struct ipath_devdata *dd,
1577 struct infinipath_counters *cntrs)
1578 {
1579 cntrs->LBIntCnt =
1580 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1581 cntrs->LBFlowStallCnt =
1582 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1583 cntrs->TxSDmaDescCnt = 0;
1584 cntrs->TxUnsupVLErrCnt =
1585 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1586 cntrs->TxDataPktCnt =
1587 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1588 cntrs->TxFlowPktCnt =
1589 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1590 cntrs->TxDwordCnt =
1591 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1592 cntrs->TxLenErrCnt =
1593 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1594 cntrs->TxMaxMinLenErrCnt =
1595 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1596 cntrs->TxUnderrunCnt =
1597 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1598 cntrs->TxFlowStallCnt =
1599 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1600 cntrs->TxDroppedPktCnt =
1601 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1602 cntrs->RxDroppedPktCnt =
1603 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1604 cntrs->RxDataPktCnt =
1605 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1606 cntrs->RxFlowPktCnt =
1607 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1608 cntrs->RxDwordCnt =
1609 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1610 cntrs->RxLenErrCnt =
1611 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1612 cntrs->RxMaxMinLenErrCnt =
1613 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1614 cntrs->RxICRCErrCnt =
1615 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1616 cntrs->RxVCRCErrCnt =
1617 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1618 cntrs->RxFlowCtrlErrCnt =
1619 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1620 cntrs->RxBadFormatCnt =
1621 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1622 cntrs->RxLinkProblemCnt =
1623 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1624 cntrs->RxEBPCnt =
1625 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1626 cntrs->RxLPCRCErrCnt =
1627 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1628 cntrs->RxBufOvflCnt =
1629 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1630 cntrs->RxTIDFullErrCnt =
1631 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1632 cntrs->RxTIDValidErrCnt =
1633 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1634 cntrs->RxPKeyMismatchCnt =
1635 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1636 cntrs->RxP0HdrEgrOvflCnt =
1637 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1638 cntrs->RxP1HdrEgrOvflCnt =
1639 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1640 cntrs->RxP2HdrEgrOvflCnt =
1641 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1642 cntrs->RxP3HdrEgrOvflCnt =
1643 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1644 cntrs->RxP4HdrEgrOvflCnt =
1645 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1646 cntrs->RxP5HdrEgrOvflCnt = 0;
1647 cntrs->RxP6HdrEgrOvflCnt = 0;
1648 cntrs->RxP7HdrEgrOvflCnt = 0;
1649 cntrs->RxP8HdrEgrOvflCnt = 0;
1650 cntrs->RxP9HdrEgrOvflCnt = 0;
1651 cntrs->RxP10HdrEgrOvflCnt = 0;
1652 cntrs->RxP11HdrEgrOvflCnt = 0;
1653 cntrs->RxP12HdrEgrOvflCnt = 0;
1654 cntrs->RxP13HdrEgrOvflCnt = 0;
1655 cntrs->RxP14HdrEgrOvflCnt = 0;
1656 cntrs->RxP15HdrEgrOvflCnt = 0;
1657 cntrs->RxP16HdrEgrOvflCnt = 0;
1658 cntrs->IBStatusChangeCnt =
1659 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1660 cntrs->IBLinkErrRecoveryCnt =
1661 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1662 cntrs->IBLinkDownedCnt =
1663 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1664 cntrs->IBSymbolErrCnt =
1665 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1666 cntrs->RxVL15DroppedPktCnt = 0;
1667 cntrs->RxOtherLocalPhyErrCnt = 0;
1668 cntrs->PcieRetryBufDiagQwordCnt = 0;
1669 cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1670 cntrs->LocalLinkIntegrityErrCnt = dd->ipath_lli_errs;
1671 cntrs->RxVlErrCnt = 0;
1672 cntrs->RxDlidFltrCnt = 0;
1673 }
1674
1675
1676 /* no interrupt fallback for these chips */
1677 static int ipath_pe_nointr_fallback(struct ipath_devdata *dd)
1678 {
1679 return 0;
1680 }
1681
1682
1683 /*
1684 * reset the XGXS (between serdes and IBC). Slightly less intrusive
1685 * than resetting the IBC or external link state, and useful in some
1686 * cases to cause some retraining. To do this right, we reset IBC
1687 * as well.
1688 */
1689 static void ipath_pe_xgxs_reset(struct ipath_devdata *dd)
1690 {
1691 u64 val, prev_val;
1692
1693 prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1694 val = prev_val | INFINIPATH_XGXS_RESET;
1695 prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */
1696 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1697 dd->ipath_control & ~INFINIPATH_C_LINKENABLE);
1698 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1699 ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1700 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val);
1701 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1702 dd->ipath_control);
1703 }
1704
1705
1706 static int ipath_pe_get_ib_cfg(struct ipath_devdata *dd, int which)
1707 {
1708 int ret;
1709
1710 switch (which) {
1711 case IPATH_IB_CFG_LWID:
1712 ret = dd->ipath_link_width_active;
1713 break;
1714 case IPATH_IB_CFG_SPD:
1715 ret = dd->ipath_link_speed_active;
1716 break;
1717 case IPATH_IB_CFG_LWID_ENB:
1718 ret = dd->ipath_link_width_enabled;
1719 break;
1720 case IPATH_IB_CFG_SPD_ENB:
1721 ret = dd->ipath_link_speed_enabled;
1722 break;
1723 default:
1724 ret = -ENOTSUPP;
1725 break;
1726 }
1727 return ret;
1728 }
1729
1730
1731 /* we assume range checking is already done, if needed */
1732 static int ipath_pe_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val)
1733 {
1734 int ret = 0;
1735
1736 if (which == IPATH_IB_CFG_LWID_ENB)
1737 dd->ipath_link_width_enabled = val;
1738 else if (which == IPATH_IB_CFG_SPD_ENB)
1739 dd->ipath_link_speed_enabled = val;
1740 else
1741 ret = -ENOTSUPP;
1742 return ret;
1743 }
1744
1745 static void ipath_pe_config_jint(struct ipath_devdata *dd, u16 a, u16 b)
1746 {
1747 }
1748
1749
1750 static int ipath_pe_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs)
1751 {
1752 ipath_setup_pe_setextled(dd, ipath_ib_linkstate(dd, ibcs),
1753 ipath_ib_linktrstate(dd, ibcs));
1754 return 0;
1755 }
1756
1757
1758 /**
1759 * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1760 * @dd: the infinipath device
1761 *
1762 * This is global, and is called directly at init to set up the
1763 * chip-specific function pointers for later use.
1764 */
1765 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1766 {
1767 dd->ipath_f_intrsetup = ipath_pe_intconfig;
1768 dd->ipath_f_bus = ipath_setup_pe_config;
1769 dd->ipath_f_reset = ipath_setup_pe_reset;
1770 dd->ipath_f_get_boardname = ipath_pe_boardname;
1771 dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1772 dd->ipath_f_early_init = ipath_pe_early_init;
1773 dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1774 dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1775 dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1776 dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1777 /*
1778 * _f_put_tid may get changed after we read the chip revision,
1779 * but we start with the safe version for all revs
1780 */
1781 dd->ipath_f_put_tid = ipath_pe_put_tid;
1782 dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1783 dd->ipath_f_setextled = ipath_setup_pe_setextled;
1784 dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1785 dd->ipath_f_free_irq = ipath_pe_free_irq;
1786 dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1787 dd->ipath_f_intr_fallback = ipath_pe_nointr_fallback;
1788 dd->ipath_f_xgxs_reset = ipath_pe_xgxs_reset;
1789 dd->ipath_f_get_msgheader = ipath_pe_get_msgheader;
1790 dd->ipath_f_config_ports = ipath_pe_config_ports;
1791 dd->ipath_f_read_counters = ipath_pe_read_counters;
1792 dd->ipath_f_get_ib_cfg = ipath_pe_get_ib_cfg;
1793 dd->ipath_f_set_ib_cfg = ipath_pe_set_ib_cfg;
1794 dd->ipath_f_config_jint = ipath_pe_config_jint;
1795 dd->ipath_f_ib_updown = ipath_pe_ib_updown;
1796
1797
1798 /* initialize chip-specific variables */
1799 ipath_init_pe_variables(dd);
1800 }
1801
Linux kernel - Deliverables
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