1 #ifndef _IPATH_KERNEL_H
2 #define _IPATH_KERNEL_H
4 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
5 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 * This header file is the base header file for infinipath kernel code
38 * ipath_user.h serves a similar purpose for user code.
41 #include <linux/interrupt.h>
44 #include "ipath_common.h"
45 #include "ipath_debug.h"
46 #include "ipath_registers.h"
48 /* only s/w major version of InfiniPath we can handle */
49 #define IPATH_CHIP_VERS_MAJ 2U
51 /* don't care about this except printing */
52 #define IPATH_CHIP_VERS_MIN 0U
54 /* temporary, maybe always */
55 extern struct infinipath_stats ipath_stats
;
57 #define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ
59 struct ipath_portdata
{
60 void **port_rcvegrbuf
;
61 dma_addr_t
*port_rcvegrbuf_phys
;
62 /* rcvhdrq base, needs mmap before useful */
64 /* kernel virtual address where hdrqtail is updated */
65 volatile __le64
*port_rcvhdrtail_kvaddr
;
67 * temp buffer for expected send setup, allocated at open, instead
70 void *port_tid_pg_list
;
71 /* when waiting for rcv or pioavail */
72 wait_queue_head_t port_wait
;
74 * rcvegr bufs base, physical, must fit
75 * in 44 bits so 32 bit programs mmap64 44 bit works)
77 dma_addr_t port_rcvegr_phys
;
78 /* mmap of hdrq, must fit in 44 bits */
79 dma_addr_t port_rcvhdrq_phys
;
80 dma_addr_t port_rcvhdrqtailaddr_phys
;
82 * number of opens on this instance (0 or 1; ignoring forks, dup,
87 * how much space to leave at start of eager TID entries for
88 * protocol use, on each TID
90 /* instead of calculating it */
92 /* chip offset of PIO buffers for this port */
94 /* how many alloc_pages() chunks in port_rcvegrbuf_pages */
95 u32 port_rcvegrbuf_chunks
;
96 /* how many egrbufs per chunk */
97 u32 port_rcvegrbufs_perchunk
;
98 /* order for port_rcvegrbuf_pages */
99 size_t port_rcvegrbuf_size
;
100 /* rcvhdrq size (for freeing) */
101 size_t port_rcvhdrq_size
;
102 /* next expected TID to check when looking for free */
104 /* next expected TID to check */
105 unsigned long port_flag
;
106 /* WAIT_RCV that timed out, no interrupt */
108 /* WAIT_PIO that timed out, no interrupt */
110 /* WAIT_RCV already happened, no wait */
112 /* WAIT_PIO already happened, no wait */
114 /* total number of rcvhdrqfull errors */
116 /* pid of process using this port */
118 /* same size as task_struct .comm[] */
120 /* pkeys set by this use of this port */
122 /* so file ops can get at unit */
123 struct ipath_devdata
*port_dd
;
129 * control information for layered drivers
131 struct _ipath_layer
{
135 struct ipath_devdata
{
136 struct list_head ipath_list
;
138 struct ipath_kregs
const *ipath_kregs
;
139 struct ipath_cregs
const *ipath_cregs
;
141 /* mem-mapped pointer to base of chip regs */
142 u64 __iomem
*ipath_kregbase
;
143 /* end of mem-mapped chip space; range checking */
144 u64 __iomem
*ipath_kregend
;
145 /* physical address of chip for io_remap, etc. */
146 unsigned long ipath_physaddr
;
147 /* base of memory alloced for ipath_kregbase, for free */
148 u64
*ipath_kregalloc
;
150 * virtual address where port0 rcvhdrqtail updated for this unit.
151 * only written to by the chip, not the driver.
153 volatile __le64
*ipath_hdrqtailptr
;
154 /* ipath_cfgports pointers */
155 struct ipath_portdata
**ipath_pd
;
156 /* sk_buffs used by port 0 eager receive queue */
157 struct sk_buff
**ipath_port0_skbs
;
158 /* kvirt address of 1st 2k pio buffer */
159 void __iomem
*ipath_pio2kbase
;
160 /* kvirt address of 1st 4k pio buffer */
161 void __iomem
*ipath_pio4kbase
;
163 * points to area where PIOavail registers will be DMA'ed.
164 * Has to be on a page of it's own, because the page will be
165 * mapped into user program space. This copy is *ONLY* ever
166 * written by DMA, not by the driver! Need a copy per device
167 * when we get to multiple devices
169 volatile __le64
*ipath_pioavailregs_dma
;
170 /* physical address where updates occur */
171 dma_addr_t ipath_pioavailregs_phys
;
172 struct _ipath_layer ipath_layer
;
174 int (*ipath_f_intrsetup
)(struct ipath_devdata
*);
175 /* setup on-chip bus config */
176 int (*ipath_f_bus
)(struct ipath_devdata
*, struct pci_dev
*);
177 /* hard reset chip */
178 int (*ipath_f_reset
)(struct ipath_devdata
*);
179 int (*ipath_f_get_boardname
)(struct ipath_devdata
*, char *,
181 void (*ipath_f_init_hwerrors
)(struct ipath_devdata
*);
182 void (*ipath_f_handle_hwerrors
)(struct ipath_devdata
*, char *,
184 void (*ipath_f_quiet_serdes
)(struct ipath_devdata
*);
185 int (*ipath_f_bringup_serdes
)(struct ipath_devdata
*);
186 int (*ipath_f_early_init
)(struct ipath_devdata
*);
187 void (*ipath_f_clear_tids
)(struct ipath_devdata
*, unsigned);
188 void (*ipath_f_put_tid
)(struct ipath_devdata
*, u64 __iomem
*,
190 void (*ipath_f_tidtemplate
)(struct ipath_devdata
*);
191 void (*ipath_f_cleanup
)(struct ipath_devdata
*);
192 void (*ipath_f_setextled
)(struct ipath_devdata
*, u64
, u64
);
193 /* fill out chip-specific fields */
194 int (*ipath_f_get_base_info
)(struct ipath_portdata
*, void *);
195 struct ipath_ibdev
*verbs_dev
;
196 struct timer_list verbs_timer
;
197 /* total dwords sent (summed from counter) */
199 /* total dwords rcvd (summed from counter) */
201 /* total packets sent (summed from counter) */
203 /* total packets rcvd (summed from counter) */
205 /* ipath_statusp initially points to this. */
207 /* GUID for this interface, in network order */
210 * aggregrate of error bits reported since last cleared, for
211 * limiting of error reporting
213 ipath_err_t ipath_lasterror
;
215 * aggregrate of error bits reported since last cleared, for
216 * limiting of hwerror reporting
218 ipath_err_t ipath_lasthwerror
;
220 * errors masked because they occur too fast, also includes errors
221 * that are always ignored (ipath_ignorederrs)
223 ipath_err_t ipath_maskederrs
;
224 /* time in jiffies at which to re-enable maskederrs */
225 unsigned long ipath_unmasktime
;
227 * errors always ignored (masked), at least for a given
228 * chip/device, because they are wrong or not useful
230 ipath_err_t ipath_ignorederrs
;
231 /* count of egrfull errors, combined for all ports */
232 u64 ipath_last_tidfull
;
233 /* for ipath_qcheck() */
234 u64 ipath_lastport0rcv_cnt
;
235 /* template for writing TIDs */
236 u64 ipath_tidtemplate
;
237 /* value to write to free TIDs */
238 u64 ipath_tidinvalid
;
239 /* PE-800 rcv interrupt setup */
240 u64 ipath_rhdrhead_intr_off
;
242 /* size of memory at ipath_kregbase */
244 /* number of registers used for pioavail */
246 /* IPATH_POLL, etc. */
248 /* ipath_flags driver is waiting for */
249 u32 ipath_state_wanted
;
250 /* last buffer for user use, first buf for kernel use is this
252 u32 ipath_lastport_piobuf
;
253 /* is a stats timer active */
254 u32 ipath_stats_timer_active
;
255 /* dwords sent read from counter */
257 /* dwords received read from counter */
259 /* sent packets read from counter */
261 /* received packets read from counter */
263 /* pio bufs allocated per port */
266 * number of ports configured as max; zero is set to number chip
267 * supports, less gives more pio bufs/port, etc.
270 /* port0 rcvhdrq head offset */
272 /* count of port 0 hdrqfull errors */
273 u32 ipath_p0_hdrqfull
;
276 * (*cfgports) used to suppress multiple instances of same
277 * port staying stuck at same point
279 u32
*ipath_lastrcvhdrqtails
;
281 * (*cfgports) used to suppress multiple instances of same
282 * port staying stuck at same point
284 u32
*ipath_lastegrheads
;
286 * index of last piobuffer we used. Speeds up searching, by
287 * starting at this point. Doesn't matter if multiple cpu's use and
288 * update, last updater is only write that matters. Whenever it
289 * wraps, we update shadow copies. Need a copy per device when we
290 * get to multiple devices
292 u32 ipath_lastpioindex
;
293 /* max length of freezemsg */
296 * consecutive times we wanted a PIO buffer but were unable to
299 u32 ipath_consec_nopiobuf
;
301 * hint that we should update ipath_pioavailshadow before
302 * looking for a PIO buffer
304 u32 ipath_upd_pio_shadow
;
305 /* so we can rewrite it after a chip reset */
307 /* so we can rewrite it after a chip reset */
310 /* HT/PCI Vendor ID (here for NodeInfo) */
312 /* HT/PCI Device ID (here for NodeInfo) */
314 /* offset in HT config space of slave/primary interface block */
315 u8 ipath_ht_slave_off
;
316 /* for write combining settings */
317 unsigned long ipath_wc_cookie
;
318 /* ref count for each pkey */
319 atomic_t ipath_pkeyrefs
[4];
320 /* shadow copy of all exptids physaddr; used only by funcsim */
321 u64
*ipath_tidsimshadow
;
322 /* shadow copy of struct page *'s for exp tid pages */
323 struct page
**ipath_pageshadow
;
324 /* lock to workaround chip bug 9437 */
325 spinlock_t ipath_tid_lock
;
329 * this address is mapped readonly into user processes so they can
330 * get status cheaply, whenever they want.
333 /* freeze msg if hw error put chip in freeze */
334 char *ipath_freezemsg
;
335 /* pci access data structure */
336 struct pci_dev
*pcidev
;
337 struct cdev
*user_cdev
;
338 struct cdev
*diag_cdev
;
339 struct class_device
*user_class_dev
;
340 struct class_device
*diag_class_dev
;
341 /* timer used to prevent stats overflow, error throttling, etc. */
342 struct timer_list ipath_stats_timer
;
343 /* check for stale messages in rcv queue */
344 /* only allow one intr at a time. */
345 unsigned long ipath_rcv_pending
;
346 void *ipath_dummy_hdrq
; /* used after port close */
347 dma_addr_t ipath_dummy_hdrq_phys
;
350 * Shadow copies of registers; size indicates read access size.
351 * Most of them are readonly, but some are write-only register,
352 * where we manipulate the bits in the shadow copy, and then write
353 * the shadow copy to infinipath.
355 * We deliberately make most of these 32 bits, since they have
356 * restricted range. For any that we read, we won't to generate 32
357 * bit accesses, since Opteron will generate 2 separate 32 bit HT
358 * transactions for a 64 bit read, and we want to avoid unnecessary
362 /* This is the 64 bit group */
365 * shadow of pioavail, check to be sure it's large enough at
368 unsigned long ipath_pioavailshadow
[8];
369 /* shadow of kr_gpio_out, for rmw ops */
371 /* kr_revision shadow */
374 * shadow of ibcctrl, for interrupt handling of link changes,
379 * last ibcstatus, to suppress "duplicate" status change messages,
382 u64 ipath_lastibcstat
;
383 /* hwerrmask shadow */
384 ipath_err_t ipath_hwerrmask
;
385 /* interrupt config reg shadow */
387 /* kr_sendpiobufbase value */
388 u64 ipath_piobufbase
;
390 /* these are the "32 bit" regs */
393 * number of GUIDs in the flash for this interface; may need some
394 * rethinking for setting on other ifaces
398 * the following two are 32-bit bitmasks, but {test,clear,set}_bit
399 * all expect bit fields to be "unsigned long"
401 /* shadow kr_rcvctrl */
402 unsigned long ipath_rcvctrl
;
403 /* shadow kr_sendctrl */
404 unsigned long ipath_sendctrl
;
406 /* value we put in kr_rcvhdrcnt */
408 /* value we put in kr_rcvhdrsize */
409 u32 ipath_rcvhdrsize
;
410 /* value we put in kr_rcvhdrentsize */
411 u32 ipath_rcvhdrentsize
;
412 /* offset of last entry in rcvhdrq */
414 /* kr_portcnt value */
416 /* kr_pagealign value */
418 /* number of "2KB" PIO buffers */
420 /* size in bytes of "2KB" PIO buffers */
422 /* number of "4KB" PIO buffers */
424 /* size in bytes of "4KB" PIO buffers */
426 /* kr_rcvegrbase value */
427 u32 ipath_rcvegrbase
;
428 /* kr_rcvegrcnt value */
430 /* kr_rcvtidbase value */
431 u32 ipath_rcvtidbase
;
432 /* kr_rcvtidcnt value */
438 /* kr_counterregbase */
440 /* shadow the control register contents */
442 /* shadow the gpio output contents */
444 /* PCI revision register (HTC rev on FPGA) */
447 /* chip address space used by 4k pio buffers */
449 /* The MTU programmed for this unit */
452 * The max size IB packet, included IB headers that we can send.
453 * Starts same as ipath_piosize, but is affected when ibmtu is
454 * changed, or by size of eager buffers
458 * ibmaxlen at init time, limited by chip and by receive buffer
459 * size. Not changed after init.
461 u32 ipath_init_ibmaxlen
;
462 /* size of each rcvegrbuffer */
463 u32 ipath_rcvegrbufsize
;
464 /* width (2,4,8,16,32) from HT config reg */
466 /* HT speed (200,400,800,1000) from HT config */
468 /* ports waiting for PIOavail intr */
469 unsigned long ipath_portpiowait
;
471 * number of sequential ibcstatus change for polling active/quiet
472 * (i.e., link not coming up).
475 /* low and high portions of MSI capability/vector */
477 /* saved after PCIe init for restore after reset */
479 /* MSI data (vector) saved for restore */
481 /* MLID programmed for this instance */
483 /* LID programmed for this instance */
485 /* list of pkeys programmed; 0 if not set */
488 * ASCII serial number, from flash, large enough for original
489 * all digit strings, and longer QLogic serial number format
492 /* human readable board version */
493 u8 ipath_boardversion
[80];
494 /* chip major rev, from ipath_revision */
496 /* chip minor rev, from ipath_revision */
498 /* board rev, from ipath_revision */
500 /* unit # of this chip, if present */
502 /* saved for restore after reset */
503 u8 ipath_pci_cacheline
;
504 /* LID mask control */
507 /* local link integrity counter */
508 u32 ipath_lli_counter
;
509 /* local link integrity errors */
510 u32 ipath_lli_errors
;
513 extern struct list_head ipath_dev_list
;
514 extern spinlock_t ipath_devs_lock
;
515 extern struct ipath_devdata
*ipath_lookup(int unit
);
517 int ipath_init_chip(struct ipath_devdata
*, int);
518 int ipath_enable_wc(struct ipath_devdata
*dd
);
519 void ipath_disable_wc(struct ipath_devdata
*dd
);
520 int ipath_count_units(int *npresentp
, int *nupp
, u32
*maxportsp
);
521 void ipath_shutdown_device(struct ipath_devdata
*);
523 struct file_operations
;
524 int ipath_cdev_init(int minor
, char *name
, struct file_operations
*fops
,
525 struct cdev
**cdevp
, struct class_device
**class_devp
);
526 void ipath_cdev_cleanup(struct cdev
**cdevp
,
527 struct class_device
**class_devp
);
529 int ipath_diag_add(struct ipath_devdata
*);
530 void ipath_diag_remove(struct ipath_devdata
*);
532 extern wait_queue_head_t ipath_state_wait
;
534 int ipath_user_add(struct ipath_devdata
*dd
);
535 void ipath_user_remove(struct ipath_devdata
*dd
);
537 struct sk_buff
*ipath_alloc_skb(struct ipath_devdata
*dd
, gfp_t
);
539 extern int ipath_diag_inuse
;
541 irqreturn_t
ipath_intr(int irq
, void *devid
, struct pt_regs
*regs
);
542 void ipath_decode_err(char *buf
, size_t blen
, ipath_err_t err
);
543 #if __IPATH_INFO || __IPATH_DBG
544 extern const char *ipath_ibcstatus_str
[];
547 /* clean up any per-chip chip-specific stuff */
548 void ipath_chip_cleanup(struct ipath_devdata
*);
549 /* clean up any chip type-specific stuff */
550 void ipath_chip_done(void);
552 /* check to see if we have to force ordering for write combining */
553 int ipath_unordered_wc(void);
555 void ipath_disarm_piobufs(struct ipath_devdata
*, unsigned first
,
558 int ipath_create_rcvhdrq(struct ipath_devdata
*, struct ipath_portdata
*);
559 void ipath_free_pddata(struct ipath_devdata
*, struct ipath_portdata
*);
561 int ipath_parse_ushort(const char *str
, unsigned short *valp
);
563 void ipath_kreceive(struct ipath_devdata
*);
564 int ipath_setrcvhdrsize(struct ipath_devdata
*, unsigned);
565 int ipath_reset_device(int);
566 void ipath_get_faststats(unsigned long);
567 int ipath_set_linkstate(struct ipath_devdata
*, u8
);
568 int ipath_set_mtu(struct ipath_devdata
*, u16
);
569 int ipath_set_lid(struct ipath_devdata
*, u32
, u8
);
571 /* for use in system calls, where we want to know device type, etc. */
572 #define port_fp(fp) ((struct ipath_portdata *) (fp)->private_data)
575 * values for ipath_flags
577 /* The chip is up and initted */
578 #define IPATH_INITTED 0x2
579 /* set if any user code has set kr_rcvhdrsize */
580 #define IPATH_RCVHDRSZ_SET 0x4
581 /* The chip is present and valid for accesses */
582 #define IPATH_PRESENT 0x8
583 /* HT link0 is only 8 bits wide, ignore upper byte crc
585 #define IPATH_8BIT_IN_HT0 0x10
586 /* HT link1 is only 8 bits wide, ignore upper byte crc
588 #define IPATH_8BIT_IN_HT1 0x20
589 /* The link is down */
590 #define IPATH_LINKDOWN 0x40
591 /* The link level is up (0x11) */
592 #define IPATH_LINKINIT 0x80
593 /* The link is in the armed (0x21) state */
594 #define IPATH_LINKARMED 0x100
595 /* The link is in the active (0x31) state */
596 #define IPATH_LINKACTIVE 0x200
597 /* link current state is unknown */
598 #define IPATH_LINKUNK 0x400
599 /* no IB cable, or no device on IB cable */
600 #define IPATH_NOCABLE 0x4000
601 /* Supports port zero per packet receive interrupts via
603 #define IPATH_GPIO_INTR 0x8000
604 /* uses the coded 4byte TID, not 8 byte */
605 #define IPATH_4BYTE_TID 0x10000
606 /* packet/word counters are 32 bit, else those 4 counters
608 #define IPATH_32BITCOUNTERS 0x20000
609 /* can miss port0 rx interrupts */
610 #define IPATH_POLL_RX_INTR 0x40000
611 #define IPATH_DISABLED 0x80000 /* administratively disabled */
613 /* portdata flag bit offsets */
614 /* waiting for a packet to arrive */
615 #define IPATH_PORT_WAITING_RCV 2
616 /* waiting for a PIO buffer to be available */
617 #define IPATH_PORT_WAITING_PIO 3
619 /* free up any allocated data at closes */
620 void ipath_free_data(struct ipath_portdata
*dd
);
621 int ipath_waitfor_mdio_cmdready(struct ipath_devdata
*);
622 int ipath_waitfor_complete(struct ipath_devdata
*, ipath_kreg
, u64
, u64
*);
623 u32 __iomem
*ipath_getpiobuf(struct ipath_devdata
*, u32
*);
624 /* init PE-800-specific func */
625 void ipath_init_pe800_funcs(struct ipath_devdata
*);
626 /* init HT-400-specific func */
627 void ipath_init_ht400_funcs(struct ipath_devdata
*);
628 void ipath_get_eeprom_info(struct ipath_devdata
*);
629 u64
ipath_snap_cntr(struct ipath_devdata
*, ipath_creg
);
632 * number of words used for protocol header if not set by ipath_userinit();
634 #define IPATH_DFLT_RCVHDRSIZE 9
636 #define IPATH_MDIO_CMD_WRITE 1
637 #define IPATH_MDIO_CMD_READ 2
638 #define IPATH_MDIO_CLD_DIV 25 /* to get 2.5 Mhz mdio clock */
639 #define IPATH_MDIO_CMDVALID 0x40000000 /* bit 30 */
640 #define IPATH_MDIO_DATAVALID 0x80000000 /* bit 31 */
641 #define IPATH_MDIO_CTRL_STD 0x0
643 static inline u64
ipath_mdio_req(int cmd
, int dev
, int reg
, int data
)
645 return (((u64
) IPATH_MDIO_CLD_DIV
) << 32) |
652 /* signal and fifo status, in bank 31 */
653 #define IPATH_MDIO_CTRL_XGXS_REG_8 0x8
654 /* controls loopback, redundancy */
655 #define IPATH_MDIO_CTRL_8355_REG_1 0x10
656 /* premph, encdec, etc. */
657 #define IPATH_MDIO_CTRL_8355_REG_2 0x11
659 #define IPATH_MDIO_CTRL_8355_REG_6 0x15
660 #define IPATH_MDIO_CTRL_8355_REG_9 0x18
661 #define IPATH_MDIO_CTRL_8355_REG_10 0x1D
663 int ipath_get_user_pages(unsigned long, size_t, struct page
**);
664 int ipath_get_user_pages_nocopy(unsigned long, struct page
**);
665 void ipath_release_user_pages(struct page
**, size_t);
666 void ipath_release_user_pages_on_close(struct page
**, size_t);
667 int ipath_eeprom_read(struct ipath_devdata
*, u8
, void *, int);
668 int ipath_eeprom_write(struct ipath_devdata
*, u8
, const void *, int);
670 /* these are used for the registers that vary with port */
671 void ipath_write_kreg_port(const struct ipath_devdata
*, ipath_kreg
,
673 u64
ipath_read_kreg64_port(const struct ipath_devdata
*, ipath_kreg
,
677 * We could have a single register get/put routine, that takes a group type,
678 * but this is somewhat clearer and cleaner. It also gives us some error
679 * checking. 64 bit register reads should always work, but are inefficient
680 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
681 * so we use kreg32 wherever possible. User register and counter register
682 * reads are always 32 bit reads, so only one form of those routines.
686 * At the moment, none of the s-registers are writable, so no
687 * ipath_write_sreg(), and none of the c-registers are writable, so no
688 * ipath_write_creg().
692 * ipath_read_ureg32 - read 32-bit virtualized per-port register
694 * @regno: register number
697 * Return the contents of a register that is virtualized to be per port.
698 * Returns -1 on errors (not distinguishable from valid contents at
699 * runtime; we may add a separate error variable at some point).
701 static inline u32
ipath_read_ureg32(const struct ipath_devdata
*dd
,
702 ipath_ureg regno
, int port
)
704 if (!dd
->ipath_kregbase
|| !(dd
->ipath_flags
& IPATH_PRESENT
))
707 return readl(regno
+ (u64 __iomem
*)
708 (dd
->ipath_uregbase
+
709 (char __iomem
*)dd
->ipath_kregbase
+
710 dd
->ipath_palign
* port
));
714 * ipath_write_ureg - write 32-bit virtualized per-port register
716 * @regno: register number
720 * Write the contents of a register that is virtualized to be per port.
722 static inline void ipath_write_ureg(const struct ipath_devdata
*dd
,
723 ipath_ureg regno
, u64 value
, int port
)
725 u64 __iomem
*ubase
= (u64 __iomem
*)
726 (dd
->ipath_uregbase
+ (char __iomem
*) dd
->ipath_kregbase
+
727 dd
->ipath_palign
* port
);
728 if (dd
->ipath_kregbase
)
729 writeq(value
, &ubase
[regno
]);
732 static inline u32
ipath_read_kreg32(const struct ipath_devdata
*dd
,
735 if (!dd
->ipath_kregbase
|| !(dd
->ipath_flags
& IPATH_PRESENT
))
737 return readl((u32 __iomem
*) & dd
->ipath_kregbase
[regno
]);
740 static inline u64
ipath_read_kreg64(const struct ipath_devdata
*dd
,
743 if (!dd
->ipath_kregbase
|| !(dd
->ipath_flags
& IPATH_PRESENT
))
746 return readq(&dd
->ipath_kregbase
[regno
]);
749 static inline void ipath_write_kreg(const struct ipath_devdata
*dd
,
750 ipath_kreg regno
, u64 value
)
752 if (dd
->ipath_kregbase
)
753 writeq(value
, &dd
->ipath_kregbase
[regno
]);
756 static inline u64
ipath_read_creg(const struct ipath_devdata
*dd
,
759 if (!dd
->ipath_kregbase
|| !(dd
->ipath_flags
& IPATH_PRESENT
))
762 return readq(regno
+ (u64 __iomem
*)
763 (dd
->ipath_cregbase
+
764 (char __iomem
*)dd
->ipath_kregbase
));
767 static inline u32
ipath_read_creg32(const struct ipath_devdata
*dd
,
770 if (!dd
->ipath_kregbase
|| !(dd
->ipath_flags
& IPATH_PRESENT
))
772 return readl(regno
+ (u64 __iomem
*)
773 (dd
->ipath_cregbase
+
774 (char __iomem
*)dd
->ipath_kregbase
));
781 struct device_driver
;
783 extern const char ib_ipath_version
[];
785 int ipath_driver_create_group(struct device_driver
*);
786 void ipath_driver_remove_group(struct device_driver
*);
788 int ipath_device_create_group(struct device
*, struct ipath_devdata
*);
789 void ipath_device_remove_group(struct device
*, struct ipath_devdata
*);
790 int ipath_expose_reset(struct device
*);
792 int ipath_diagpkt_add(void);
793 void ipath_diagpkt_remove(void);
795 int ipath_init_ipathfs(void);
796 void ipath_exit_ipathfs(void);
797 int ipathfs_add_device(struct ipath_devdata
*);
798 int ipathfs_remove_device(struct ipath_devdata
*);
801 * Flush write combining store buffers (if present) and perform a write
804 #if defined(CONFIG_X86_64)
805 #define ipath_flush_wc() asm volatile("sfence" ::: "memory")
807 #define ipath_flush_wc() wmb()
810 extern unsigned ipath_debug
; /* debugging bit mask */
812 const char *ipath_get_unit_name(int unit
);
814 extern struct mutex ipath_mutex
;
816 #define IPATH_DRV_NAME "ib_ipath"
817 #define IPATH_MAJOR 233
818 #define IPATH_USER_MINOR_BASE 0
819 #define IPATH_DIAGPKT_MINOR 127
820 #define IPATH_DIAG_MINOR_BASE 129
821 #define IPATH_NMINORS 255
823 #define ipath_dev_err(dd,fmt,...) \
825 const struct ipath_devdata *__dd = (dd); \
827 dev_err(&__dd->pcidev->dev, "%s: " fmt, \
828 ipath_get_unit_name(__dd->ipath_unit), \
831 printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \
832 ipath_get_unit_name(__dd->ipath_unit), \
838 # define __IPATH_DBG_WHICH(which,fmt,...) \
840 if(unlikely(ipath_debug&(which))) \
841 printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
842 __func__,##__VA_ARGS__); \
845 # define ipath_dbg(fmt,...) \
846 __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__)
847 # define ipath_cdbg(which,fmt,...) \
848 __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__)
850 #else /* ! _IPATH_DEBUGGING */
852 # define ipath_dbg(fmt,...)
853 # define ipath_cdbg(which,fmt,...)
855 #endif /* _IPATH_DEBUGGING */
857 #endif /* _IPATH_KERNEL_H */