drivers/infiniband/hw/ipath/ipath_kernel.h

   1 #ifndef _IPATH_KERNEL_H
   2 #define _IPATH_KERNEL_H
   3 /*
   4  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
   5  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 /*
  37  * This header file is the base header file for infinipath kernel code
  38  * ipath_user.h serves a similar purpose for user code.
  39  */
  40
  41 #include <linux/interrupt.h>
  42 #include <asm/io.h>
  43
  44 #include "ipath_common.h"
  45 #include "ipath_debug.h"
  46 #include "ipath_registers.h"
  47
  48 /* only s/w major version of InfiniPath we can handle */
  49 #define IPATH_CHIP_VERS_MAJ 2U
  50
  51 /* don't care about this except printing */
  52 #define IPATH_CHIP_VERS_MIN 0U
  53
  54 /* temporary, maybe always */
  55 extern struct infinipath_stats ipath_stats;
  56
  57 #define IPATH_CHIP_SWVERSION IPATH_CHIP_VERS_MAJ
  58
  59 struct ipath_portdata {
  60         void **port_rcvegrbuf;
  61         dma_addr_t *port_rcvegrbuf_phys;
  62         /* rcvhdrq base, needs mmap before useful */
  63         void *port_rcvhdrq;
  64         /* kernel virtual address where hdrqtail is updated */
  65         volatile __le64 *port_rcvhdrtail_kvaddr;
  66         /*
  67          * temp buffer for expected send setup, allocated at open, instead
  68          * of each setup call
  69          */
  70         void *port_tid_pg_list;
  71         /* when waiting for rcv or pioavail */
  72         wait_queue_head_t port_wait;
  73         /*
  74          * rcvegr bufs base, physical, must fit
  75          * in 44 bits so 32 bit programs mmap64 44 bit works)
  76          */
  77         dma_addr_t port_rcvegr_phys;
  78         /* mmap of hdrq, must fit in 44 bits */
  79         dma_addr_t port_rcvhdrq_phys;
  80         dma_addr_t port_rcvhdrqtailaddr_phys;
  81         /*
  82          * number of opens on this instance (0 or 1; ignoring forks, dup,
  83          * etc. for now)
  84          */
  85         int port_cnt;
  86         /*
  87          * how much space to leave at start of eager TID entries for
  88          * protocol use, on each TID
  89          */
  90         /* instead of calculating it */
  91         unsigned port_port;
  92         /* chip offset of PIO buffers for this port */
  93         u32 port_piobufs;
  94         /* how many alloc_pages() chunks in port_rcvegrbuf_pages */
  95         u32 port_rcvegrbuf_chunks;
  96         /* how many egrbufs per chunk */
  97         u32 port_rcvegrbufs_perchunk;
  98         /* order for port_rcvegrbuf_pages */
  99         size_t port_rcvegrbuf_size;
 100         /* rcvhdrq size (for freeing) */
 101         size_t port_rcvhdrq_size;
 102         /* next expected TID to check when looking for free */
 103         u32 port_tidcursor;
 104         /* next expected TID to check */
 105         unsigned long port_flag;
 106         /* WAIT_RCV that timed out, no interrupt */
 107         u32 port_rcvwait_to;
 108         /* WAIT_PIO that timed out, no interrupt */
 109         u32 port_piowait_to;
 110         /* WAIT_RCV already happened, no wait */
 111         u32 port_rcvnowait;
 112         /* WAIT_PIO already happened, no wait */
 113         u32 port_pionowait;
 114         /* total number of rcvhdrqfull errors */
 115         u32 port_hdrqfull;
 116         /* pid of process using this port */
 117         pid_t port_pid;
 118         /* same size as task_struct .comm[] */
 119         char port_comm[16];
 120         /* pkeys set by this use of this port */
 121         u16 port_pkeys[4];
 122         /* so file ops can get at unit */
 123         struct ipath_devdata *port_dd;
 124 };
 125
 126 struct sk_buff;
 127
 128 /*
 129  * control information for layered drivers
 130  */
 131 struct _ipath_layer {
 132         void *l_arg;
 133 };
 134
 135 /* Verbs layer interface */
 136 struct _verbs_layer {
 137         void *l_arg;
 138         struct timer_list l_timer;
 139 };
 140
 141 struct ipath_devdata {
 142         struct list_head ipath_list;
 143
 144         struct ipath_kregs const *ipath_kregs;
 145         struct ipath_cregs const *ipath_cregs;
 146
 147         /* mem-mapped pointer to base of chip regs */
 148         u64 __iomem *ipath_kregbase;
 149         /* end of mem-mapped chip space; range checking */
 150         u64 __iomem *ipath_kregend;
 151         /* physical address of chip for io_remap, etc. */
 152         unsigned long ipath_physaddr;
 153         /* base of memory alloced for ipath_kregbase, for free */
 154         u64 *ipath_kregalloc;
 155         /*
 156          * virtual address where port0 rcvhdrqtail updated for this unit.
 157          * only written to by the chip, not the driver.
 158          */
 159         volatile __le64 *ipath_hdrqtailptr;
 160         /* ipath_cfgports pointers */
 161         struct ipath_portdata **ipath_pd;
 162         /* sk_buffs used by port 0 eager receive queue */
 163         struct sk_buff **ipath_port0_skbs;
 164         /* kvirt address of 1st 2k pio buffer */
 165         void __iomem *ipath_pio2kbase;
 166         /* kvirt address of 1st 4k pio buffer */
 167         void __iomem *ipath_pio4kbase;
 168         /*
 169          * points to area where PIOavail registers will be DMA'ed.
 170          * Has to be on a page of it's own, because the page will be
 171          * mapped into user program space.  This copy is *ONLY* ever
 172          * written by DMA, not by the driver!  Need a copy per device
 173          * when we get to multiple devices
 174          */
 175         volatile __le64 *ipath_pioavailregs_dma;
 176         /* physical address where updates occur */
 177         dma_addr_t ipath_pioavailregs_phys;
 178         struct _ipath_layer ipath_layer;
 179         /* setup intr */
 180         int (*ipath_f_intrsetup)(struct ipath_devdata *);
 181         /* setup on-chip bus config */
 182         int (*ipath_f_bus)(struct ipath_devdata *, struct pci_dev *);
 183         /* hard reset chip */
 184         int (*ipath_f_reset)(struct ipath_devdata *);
 185         int (*ipath_f_get_boardname)(struct ipath_devdata *, char *,
 186                                      size_t);
 187         void (*ipath_f_init_hwerrors)(struct ipath_devdata *);
 188         void (*ipath_f_handle_hwerrors)(struct ipath_devdata *, char *,
 189                                         size_t);
 190         void (*ipath_f_quiet_serdes)(struct ipath_devdata *);
 191         int (*ipath_f_bringup_serdes)(struct ipath_devdata *);
 192         int (*ipath_f_early_init)(struct ipath_devdata *);
 193         void (*ipath_f_clear_tids)(struct ipath_devdata *, unsigned);
 194         void (*ipath_f_put_tid)(struct ipath_devdata *, u64 __iomem*,
 195                                 u32, unsigned long);
 196         void (*ipath_f_tidtemplate)(struct ipath_devdata *);
 197         void (*ipath_f_cleanup)(struct ipath_devdata *);
 198         void (*ipath_f_setextled)(struct ipath_devdata *, u64, u64);
 199         /* fill out chip-specific fields */
 200         int (*ipath_f_get_base_info)(struct ipath_portdata *, void *);
 201         struct _verbs_layer verbs_layer;
 202         /* total dwords sent (summed from counter) */
 203         u64 ipath_sword;
 204         /* total dwords rcvd (summed from counter) */
 205         u64 ipath_rword;
 206         /* total packets sent (summed from counter) */
 207         u64 ipath_spkts;
 208         /* total packets rcvd (summed from counter) */
 209         u64 ipath_rpkts;
 210         /* ipath_statusp initially points to this. */
 211         u64 _ipath_status;
 212         /* GUID for this interface, in network order */
 213         __be64 ipath_guid;
 214         /*
 215          * aggregrate of error bits reported since last cleared, for
 216          * limiting of error reporting
 217          */
 218         ipath_err_t ipath_lasterror;
 219         /*
 220          * aggregrate of error bits reported since last cleared, for
 221          * limiting of hwerror reporting
 222          */
 223         ipath_err_t ipath_lasthwerror;
 224         /*
 225          * errors masked because they occur too fast, also includes errors
 226          * that are always ignored (ipath_ignorederrs)
 227          */
 228         ipath_err_t ipath_maskederrs;
 229         /* time in jiffies at which to re-enable maskederrs */
 230         unsigned long ipath_unmasktime;
 231         /*
 232          * errors always ignored (masked), at least for a given
 233          * chip/device, because they are wrong or not useful
 234          */
 235         ipath_err_t ipath_ignorederrs;
 236         /* count of egrfull errors, combined for all ports */
 237         u64 ipath_last_tidfull;
 238         /* for ipath_qcheck() */
 239         u64 ipath_lastport0rcv_cnt;
 240         /* template for writing TIDs  */
 241         u64 ipath_tidtemplate;
 242         /* value to write to free TIDs */
 243         u64 ipath_tidinvalid;
 244         /* PE-800 rcv interrupt setup */
 245         u64 ipath_rhdrhead_intr_off;
 246
 247         /* size of memory at ipath_kregbase */
 248         u32 ipath_kregsize;
 249         /* number of registers used for pioavail */
 250         u32 ipath_pioavregs;
 251         /* IPATH_POLL, etc. */
 252         u32 ipath_flags;
 253         /* ipath_flags sma is waiting for */
 254         u32 ipath_sma_state_wanted;
 255         /* last buffer for user use, first buf for kernel use is this
 256          * index. */
 257         u32 ipath_lastport_piobuf;
 258         /* is a stats timer active */
 259         u32 ipath_stats_timer_active;
 260         /* dwords sent read from counter */
 261         u32 ipath_lastsword;
 262         /* dwords received read from counter */
 263         u32 ipath_lastrword;
 264         /* sent packets read from counter */
 265         u32 ipath_lastspkts;
 266         /* received packets read from counter */
 267         u32 ipath_lastrpkts;
 268         /* pio bufs allocated per port */
 269         u32 ipath_pbufsport;
 270         /*
 271          * number of ports configured as max; zero is set to number chip
 272          * supports, less gives more pio bufs/port, etc.
 273          */
 274         u32 ipath_cfgports;
 275         /* port0 rcvhdrq head offset */
 276         u32 ipath_port0head;
 277         /* count of port 0 hdrqfull errors */
 278         u32 ipath_p0_hdrqfull;
 279
 280         /*
 281          * (*cfgports) used to suppress multiple instances of same
 282          * port staying stuck at same point
 283          */
 284         u32 *ipath_lastrcvhdrqtails;
 285         /*
 286          * (*cfgports) used to suppress multiple instances of same
 287          * port staying stuck at same point
 288          */
 289         u32 *ipath_lastegrheads;
 290         /*
 291          * index of last piobuffer we used.  Speeds up searching, by
 292          * starting at this point.  Doesn't matter if multiple cpu's use and
 293          * update, last updater is only write that matters.  Whenever it
 294          * wraps, we update shadow copies.  Need a copy per device when we
 295          * get to multiple devices
 296          */
 297         u32 ipath_lastpioindex;
 298         /* max length of freezemsg */
 299         u32 ipath_freezelen;
 300         /*
 301          * consecutive times we wanted a PIO buffer but were unable to
 302          * get one
 303          */
 304         u32 ipath_consec_nopiobuf;
 305         /*
 306          * hint that we should update ipath_pioavailshadow before
 307          * looking for a PIO buffer
 308          */
 309         u32 ipath_upd_pio_shadow;
 310         /* so we can rewrite it after a chip reset */
 311         u32 ipath_pcibar0;
 312         /* so we can rewrite it after a chip reset */
 313         u32 ipath_pcibar1;
 314         /* sequential tries for SMA send and no bufs */
 315         u32 ipath_nosma_bufs;
 316         /* duration (seconds) ipath_nosma_bufs set */
 317         u32 ipath_nosma_secs;
 318
 319         /* HT/PCI Vendor ID (here for NodeInfo) */
 320         u16 ipath_vendorid;
 321         /* HT/PCI Device ID (here for NodeInfo) */
 322         u16 ipath_deviceid;
 323         /* offset in HT config space of slave/primary interface block */
 324         u8 ipath_ht_slave_off;
 325         /* for write combining settings */
 326         unsigned long ipath_wc_cookie;
 327         /* ref count for each pkey */
 328         atomic_t ipath_pkeyrefs[4];
 329         /* shadow copy of all exptids physaddr; used only by funcsim */
 330         u64 *ipath_tidsimshadow;
 331         /* shadow copy of struct page *'s for exp tid pages */
 332         struct page **ipath_pageshadow;
 333         /* lock to workaround chip bug 9437 */
 334         spinlock_t ipath_tid_lock;
 335
 336         /*
 337          * IPATH_STATUS_*,
 338          * this address is mapped readonly into user processes so they can
 339          * get status cheaply, whenever they want.
 340          */
 341         u64 *ipath_statusp;
 342         /* freeze msg if hw error put chip in freeze */
 343         char *ipath_freezemsg;
 344         /* pci access data structure */
 345         struct pci_dev *pcidev;
 346         struct cdev *user_cdev;
 347         struct cdev *diag_cdev;
 348         struct class_device *user_class_dev;
 349         struct class_device *diag_class_dev;
 350         /* timer used to prevent stats overflow, error throttling, etc. */
 351         struct timer_list ipath_stats_timer;
 352         /* check for stale messages in rcv queue */
 353         /* only allow one intr at a time. */
 354         unsigned long ipath_rcv_pending;
 355         void *ipath_dummy_hdrq; /* used after port close */
 356         dma_addr_t ipath_dummy_hdrq_phys;
 357
 358         /*
 359          * Shadow copies of registers; size indicates read access size.
 360          * Most of them are readonly, but some are write-only register,
 361          * where we manipulate the bits in the shadow copy, and then write
 362          * the shadow copy to infinipath.
 363          *
 364          * We deliberately make most of these 32 bits, since they have
 365          * restricted range.  For any that we read, we won't to generate 32
 366          * bit accesses, since Opteron will generate 2 separate 32 bit HT
 367          * transactions for a 64 bit read, and we want to avoid unnecessary
 368          * HT transactions.
 369          */
 370
 371         /* This is the 64 bit group */
 372
 373         /*
 374          * shadow of pioavail, check to be sure it's large enough at
 375          * init time.
 376          */
 377         unsigned long ipath_pioavailshadow[8];
 378         /* shadow of kr_gpio_out, for rmw ops */
 379         u64 ipath_gpio_out;
 380         /* kr_revision shadow */
 381         u64 ipath_revision;
 382         /*
 383          * shadow of ibcctrl, for interrupt handling of link changes,
 384          * etc.
 385          */
 386         u64 ipath_ibcctrl;
 387         /*
 388          * last ibcstatus, to suppress "duplicate" status change messages,
 389          * mostly from 2 to 3
 390          */
 391         u64 ipath_lastibcstat;
 392         /* hwerrmask shadow */
 393         ipath_err_t ipath_hwerrmask;
 394         /* interrupt config reg shadow */
 395         u64 ipath_intconfig;
 396         /* kr_sendpiobufbase value */
 397         u64 ipath_piobufbase;
 398
 399         /* these are the "32 bit" regs */
 400
 401         /*
 402          * number of GUIDs in the flash for this interface; may need some
 403          * rethinking for setting on other ifaces
 404          */
 405         u32 ipath_nguid;
 406         /*
 407          * the following two are 32-bit bitmasks, but {test,clear,set}_bit
 408          * all expect bit fields to be "unsigned long"
 409          */
 410         /* shadow kr_rcvctrl */
 411         unsigned long ipath_rcvctrl;
 412         /* shadow kr_sendctrl */
 413         unsigned long ipath_sendctrl;
 414
 415         /* value we put in kr_rcvhdrcnt */
 416         u32 ipath_rcvhdrcnt;
 417         /* value we put in kr_rcvhdrsize */
 418         u32 ipath_rcvhdrsize;
 419         /* value we put in kr_rcvhdrentsize */
 420         u32 ipath_rcvhdrentsize;
 421         /* offset of last entry in rcvhdrq */
 422         u32 ipath_hdrqlast;
 423         /* kr_portcnt value */
 424         u32 ipath_portcnt;
 425         /* kr_pagealign value */
 426         u32 ipath_palign;
 427         /* number of "2KB" PIO buffers */
 428         u32 ipath_piobcnt2k;
 429         /* size in bytes of "2KB" PIO buffers */
 430         u32 ipath_piosize2k;
 431         /* number of "4KB" PIO buffers */
 432         u32 ipath_piobcnt4k;
 433         /* size in bytes of "4KB" PIO buffers */
 434         u32 ipath_piosize4k;
 435         /* kr_rcvegrbase value */
 436         u32 ipath_rcvegrbase;
 437         /* kr_rcvegrcnt value */
 438         u32 ipath_rcvegrcnt;
 439         /* kr_rcvtidbase value */
 440         u32 ipath_rcvtidbase;
 441         /* kr_rcvtidcnt value */
 442         u32 ipath_rcvtidcnt;
 443         /* kr_sendregbase */
 444         u32 ipath_sregbase;
 445         /* kr_userregbase */
 446         u32 ipath_uregbase;
 447         /* kr_counterregbase */
 448         u32 ipath_cregbase;
 449         /* shadow the control register contents */
 450         u32 ipath_control;
 451         /* shadow the gpio output contents */
 452         u32 ipath_extctrl;
 453         /* PCI revision register (HTC rev on FPGA) */
 454         u32 ipath_pcirev;
 455
 456         /* chip address space used by 4k pio buffers */
 457         u32 ipath_4kalign;
 458         /* The MTU programmed for this unit */
 459         u32 ipath_ibmtu;
 460         /*
 461          * The max size IB packet, included IB headers that we can send.
 462          * Starts same as ipath_piosize, but is affected when ibmtu is
 463          * changed, or by size of eager buffers
 464          */
 465         u32 ipath_ibmaxlen;
 466         /*
 467          * ibmaxlen at init time, limited by chip and by receive buffer
 468          * size.  Not changed after init.
 469          */
 470         u32 ipath_init_ibmaxlen;
 471         /* size of each rcvegrbuffer */
 472         u32 ipath_rcvegrbufsize;
 473         /* width (2,4,8,16,32) from HT config reg */
 474         u32 ipath_htwidth;
 475         /* HT speed (200,400,800,1000) from HT config */
 476         u32 ipath_htspeed;
 477         /* ports waiting for PIOavail intr */
 478         unsigned long ipath_portpiowait;
 479         /*
 480          * number of sequential ibcstatus change for polling active/quiet
 481          * (i.e., link not coming up).
 482          */
 483         u32 ipath_ibpollcnt;
 484         /* low and high portions of MSI capability/vector */
 485         u32 ipath_msi_lo;
 486         /* saved after PCIe init for restore after reset */
 487         u32 ipath_msi_hi;
 488         /* MSI data (vector) saved for restore */
 489         u16 ipath_msi_data;
 490         /* MLID programmed for this instance */
 491         u16 ipath_mlid;
 492         /* LID programmed for this instance */
 493         u16 ipath_lid;
 494         /* list of pkeys programmed; 0 if not set */
 495         u16 ipath_pkeys[4];
 496         /*
 497          * ASCII serial number, from flash, large enough for original
 498          * all digit strings, and longer QLogic serial number format
 499          */
 500         u8 ipath_serial[16];
 501         /* human readable board version */
 502         u8 ipath_boardversion[80];
 503         /* chip major rev, from ipath_revision */
 504         u8 ipath_majrev;
 505         /* chip minor rev, from ipath_revision */
 506         u8 ipath_minrev;
 507         /* board rev, from ipath_revision */
 508         u8 ipath_boardrev;
 509         /* unit # of this chip, if present */
 510         int ipath_unit;
 511         /* saved for restore after reset */
 512         u8 ipath_pci_cacheline;
 513         /* LID mask control */
 514         u8 ipath_lmc;
 515
 516         /* local link integrity counter */
 517         u32 ipath_lli_counter;
 518         /* local link integrity errors */
 519         u32 ipath_lli_errors;
 520 };
 521
 522 extern struct list_head ipath_dev_list;
 523 extern spinlock_t ipath_devs_lock;
 524 extern struct ipath_devdata *ipath_lookup(int unit);
 525
 526 extern u16 ipath_layer_rcv_opcode;
 527 extern int __ipath_layer_intr(struct ipath_devdata *, u32);
 528 extern int ipath_layer_intr(struct ipath_devdata *, u32);
 529 extern int __ipath_layer_rcv(struct ipath_devdata *, void *,
 530                              struct sk_buff *);
 531 extern int __ipath_layer_rcv_lid(struct ipath_devdata *, void *);
 532 extern int __ipath_verbs_piobufavail(struct ipath_devdata *);
 533 extern int __ipath_verbs_rcv(struct ipath_devdata *, void *, void *, u32);
 534
 535 void ipath_layer_add(struct ipath_devdata *);
 536 void ipath_layer_remove(struct ipath_devdata *);
 537
 538 int ipath_init_chip(struct ipath_devdata *, int);
 539 int ipath_enable_wc(struct ipath_devdata *dd);
 540 void ipath_disable_wc(struct ipath_devdata *dd);
 541 int ipath_count_units(int *npresentp, int *nupp, u32 *maxportsp);
 542 void ipath_shutdown_device(struct ipath_devdata *);
 543
 544 struct file_operations;
 545 int ipath_cdev_init(int minor, char *name, struct file_operations *fops,
 546                     struct cdev **cdevp, struct class_device **class_devp);
 547 void ipath_cdev_cleanup(struct cdev **cdevp,
 548                         struct class_device **class_devp);
 549
 550 int ipath_diag_add(struct ipath_devdata *);
 551 void ipath_diag_remove(struct ipath_devdata *);
 552 void ipath_diag_bringup_link(struct ipath_devdata *);
 553
 554 extern wait_queue_head_t ipath_sma_state_wait;
 555
 556 int ipath_user_add(struct ipath_devdata *dd);
 557 void ipath_user_remove(struct ipath_devdata *dd);
 558
 559 struct sk_buff *ipath_alloc_skb(struct ipath_devdata *dd, gfp_t);
 560
 561 extern int ipath_diag_inuse;
 562
 563 irqreturn_t ipath_intr(int irq, void *devid, struct pt_regs *regs);
 564 void ipath_decode_err(char *buf, size_t blen, ipath_err_t err);
 565 #if __IPATH_INFO || __IPATH_DBG
 566 extern const char *ipath_ibcstatus_str[];
 567 #endif
 568
 569 /* clean up any per-chip chip-specific stuff */
 570 void ipath_chip_cleanup(struct ipath_devdata *);
 571 /* clean up any chip type-specific stuff */
 572 void ipath_chip_done(void);
 573
 574 /* check to see if we have to force ordering for write combining */
 575 int ipath_unordered_wc(void);
 576
 577 void ipath_disarm_piobufs(struct ipath_devdata *, unsigned first,
 578                           unsigned cnt);
 579
 580 int ipath_create_rcvhdrq(struct ipath_devdata *, struct ipath_portdata *);
 581 void ipath_free_pddata(struct ipath_devdata *, struct ipath_portdata *);
 582
 583 int ipath_parse_ushort(const char *str, unsigned short *valp);
 584
 585 int ipath_wait_linkstate(struct ipath_devdata *, u32, int);
 586 void ipath_set_ib_lstate(struct ipath_devdata *, int);
 587 void ipath_kreceive(struct ipath_devdata *);
 588 int ipath_setrcvhdrsize(struct ipath_devdata *, unsigned);
 589 int ipath_reset_device(int);
 590 void ipath_get_faststats(unsigned long);
 591
 592 /* for use in system calls, where we want to know device type, etc. */
 593 #define port_fp(fp) ((struct ipath_portdata *) (fp)->private_data)
 594
 595 /*
 596  * values for ipath_flags
 597  */
 598 /* The chip is up and initted */
 599 #define IPATH_INITTED       0x2
 600                 /* set if any user code has set kr_rcvhdrsize */
 601 #define IPATH_RCVHDRSZ_SET  0x4
 602                 /* The chip is present and valid for accesses */
 603 #define IPATH_PRESENT       0x8
 604                 /* HT link0 is only 8 bits wide, ignore upper byte crc
 605                  * errors, etc. */
 606 #define IPATH_8BIT_IN_HT0   0x10
 607                 /* HT link1 is only 8 bits wide, ignore upper byte crc
 608                  * errors, etc. */
 609 #define IPATH_8BIT_IN_HT1   0x20
 610                 /* The link is down */
 611 #define IPATH_LINKDOWN      0x40
 612                 /* The link level is up (0x11) */
 613 #define IPATH_LINKINIT      0x80
 614                 /* The link is in the armed (0x21) state */
 615 #define IPATH_LINKARMED     0x100
 616                 /* The link is in the active (0x31) state */
 617 #define IPATH_LINKACTIVE    0x200
 618                 /* link current state is unknown */
 619 #define IPATH_LINKUNK       0x400
 620                 /* no IB cable, or no device on IB cable */
 621 #define IPATH_NOCABLE       0x4000
 622                 /* Supports port zero per packet receive interrupts via
 623                  * GPIO */
 624 #define IPATH_GPIO_INTR     0x8000
 625                 /* uses the coded 4byte TID, not 8 byte */
 626 #define IPATH_4BYTE_TID     0x10000
 627                 /* packet/word counters are 32 bit, else those 4 counters
 628                  * are 64bit */
 629 #define IPATH_32BITCOUNTERS 0x20000
 630                 /* can miss port0 rx interrupts */
 631 #define IPATH_POLL_RX_INTR  0x40000
 632 #define IPATH_DISABLED      0x80000 /* administratively disabled */
 633
 634 /* portdata flag bit offsets */
 635                 /* waiting for a packet to arrive */
 636 #define IPATH_PORT_WAITING_RCV   2
 637                 /* waiting for a PIO buffer to be available */
 638 #define IPATH_PORT_WAITING_PIO   3
 639
 640 /* free up any allocated data at closes */
 641 void ipath_free_data(struct ipath_portdata *dd);
 642 int ipath_waitfor_mdio_cmdready(struct ipath_devdata *);
 643 int ipath_waitfor_complete(struct ipath_devdata *, ipath_kreg, u64, u64 *);
 644 u32 __iomem *ipath_getpiobuf(struct ipath_devdata *, u32 *);
 645 /* init PE-800-specific func */
 646 void ipath_init_pe800_funcs(struct ipath_devdata *);
 647 /* init HT-400-specific func */
 648 void ipath_init_ht400_funcs(struct ipath_devdata *);
 649 void ipath_get_eeprom_info(struct ipath_devdata *);
 650 u64 ipath_snap_cntr(struct ipath_devdata *, ipath_creg);
 651
 652 /*
 653  * number of words used for protocol header if not set by ipath_userinit();
 654  */
 655 #define IPATH_DFLT_RCVHDRSIZE 9
 656
 657 #define IPATH_MDIO_CMD_WRITE   1
 658 #define IPATH_MDIO_CMD_READ    2
 659 #define IPATH_MDIO_CLD_DIV     25       /* to get 2.5 Mhz mdio clock */
 660 #define IPATH_MDIO_CMDVALID    0x40000000       /* bit 30 */
 661 #define IPATH_MDIO_DATAVALID   0x80000000       /* bit 31 */
 662 #define IPATH_MDIO_CTRL_STD    0x0
 663
 664 static inline u64 ipath_mdio_req(int cmd, int dev, int reg, int data)
 665 {
 666         return (((u64) IPATH_MDIO_CLD_DIV) << 32) |
 667                 (cmd << 26) |
 668                 (dev << 21) |
 669                 (reg << 16) |
 670                 (data & 0xFFFF);
 671 }
 672
 673                 /* signal and fifo status, in bank 31 */
 674 #define IPATH_MDIO_CTRL_XGXS_REG_8  0x8
 675                 /* controls loopback, redundancy */
 676 #define IPATH_MDIO_CTRL_8355_REG_1  0x10
 677                 /* premph, encdec, etc. */
 678 #define IPATH_MDIO_CTRL_8355_REG_2  0x11
 679                 /* Kchars, etc. */
 680 #define IPATH_MDIO_CTRL_8355_REG_6  0x15
 681 #define IPATH_MDIO_CTRL_8355_REG_9  0x18
 682 #define IPATH_MDIO_CTRL_8355_REG_10 0x1D
 683
 684 int ipath_get_user_pages(unsigned long, size_t, struct page **);
 685 int ipath_get_user_pages_nocopy(unsigned long, struct page **);
 686 void ipath_release_user_pages(struct page **, size_t);
 687 void ipath_release_user_pages_on_close(struct page **, size_t);
 688 int ipath_eeprom_read(struct ipath_devdata *, u8, void *, int);
 689 int ipath_eeprom_write(struct ipath_devdata *, u8, const void *, int);
 690
 691 /* these are used for the registers that vary with port */
 692 void ipath_write_kreg_port(const struct ipath_devdata *, ipath_kreg,
 693                            unsigned, u64);
 694 u64 ipath_read_kreg64_port(const struct ipath_devdata *, ipath_kreg,
 695                            unsigned);
 696
 697 /*
 698  * We could have a single register get/put routine, that takes a group type,
 699  * but this is somewhat clearer and cleaner.  It also gives us some error
 700  * checking.  64 bit register reads should always work, but are inefficient
 701  * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
 702  * so we use kreg32 wherever possible.  User register and counter register
 703  * reads are always 32 bit reads, so only one form of those routines.
 704  */
 705
 706 /*
 707  * At the moment, none of the s-registers are writable, so no
 708  * ipath_write_sreg(), and none of the c-registers are writable, so no
 709  * ipath_write_creg().
 710  */
 711
 712 /**
 713  * ipath_read_ureg32 - read 32-bit virtualized per-port register
 714  * @dd: device
 715  * @regno: register number
 716  * @port: port number
 717  *
 718  * Return the contents of a register that is virtualized to be per port.
 719  * Returns -1 on errors (not distinguishable from valid contents at
 720  * runtime; we may add a separate error variable at some point).
 721  */
 722 static inline u32 ipath_read_ureg32(const struct ipath_devdata *dd,
 723                                     ipath_ureg regno, int port)
 724 {
 725         if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
 726                 return 0;
 727
 728         return readl(regno + (u64 __iomem *)
 729                      (dd->ipath_uregbase +
 730                       (char __iomem *)dd->ipath_kregbase +
 731                       dd->ipath_palign * port));
 732 }
 733
 734 /**
 735  * ipath_write_ureg - write 32-bit virtualized per-port register
 736  * @dd: device
 737  * @regno: register number
 738  * @value: value
 739  * @port: port
 740  *
 741  * Write the contents of a register that is virtualized to be per port.
 742  */
 743 static inline void ipath_write_ureg(const struct ipath_devdata *dd,
 744                                     ipath_ureg regno, u64 value, int port)
 745 {
 746         u64 __iomem *ubase = (u64 __iomem *)
 747                 (dd->ipath_uregbase + (char __iomem *) dd->ipath_kregbase +
 748                  dd->ipath_palign * port);
 749         if (dd->ipath_kregbase)
 750                 writeq(value, &ubase[regno]);
 751 }
 752
 753 static inline u32 ipath_read_kreg32(const struct ipath_devdata *dd,
 754                                     ipath_kreg regno)
 755 {
 756         if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
 757                 return -1;
 758         return readl((u32 __iomem *) & dd->ipath_kregbase[regno]);
 759 }
 760
 761 static inline u64 ipath_read_kreg64(const struct ipath_devdata *dd,
 762                                     ipath_kreg regno)
 763 {
 764         if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
 765                 return -1;
 766
 767         return readq(&dd->ipath_kregbase[regno]);
 768 }
 769
 770 static inline void ipath_write_kreg(const struct ipath_devdata *dd,
 771                                     ipath_kreg regno, u64 value)
 772 {
 773         if (dd->ipath_kregbase)
 774                 writeq(value, &dd->ipath_kregbase[regno]);
 775 }
 776
 777 static inline u64 ipath_read_creg(const struct ipath_devdata *dd,
 778                                   ipath_sreg regno)
 779 {
 780         if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
 781                 return 0;
 782
 783         return readq(regno + (u64 __iomem *)
 784                      (dd->ipath_cregbase +
 785                       (char __iomem *)dd->ipath_kregbase));
 786 }
 787
 788 static inline u32 ipath_read_creg32(const struct ipath_devdata *dd,
 789                                          ipath_sreg regno)
 790 {
 791         if (!dd->ipath_kregbase || !(dd->ipath_flags & IPATH_PRESENT))
 792                 return 0;
 793         return readl(regno + (u64 __iomem *)
 794                      (dd->ipath_cregbase +
 795                       (char __iomem *)dd->ipath_kregbase));
 796 }
 797
 798 /*
 799  * sysfs interface.
 800  */
 801
 802 struct device_driver;
 803
 804 extern const char ipath_core_version[];
 805
 806 int ipath_driver_create_group(struct device_driver *);
 807 void ipath_driver_remove_group(struct device_driver *);
 808
 809 int ipath_device_create_group(struct device *, struct ipath_devdata *);
 810 void ipath_device_remove_group(struct device *, struct ipath_devdata *);
 811 int ipath_expose_reset(struct device *);
 812
 813 int ipath_init_ipathfs(void);
 814 void ipath_exit_ipathfs(void);
 815 int ipathfs_add_device(struct ipath_devdata *);
 816 int ipathfs_remove_device(struct ipath_devdata *);
 817
 818 /*
 819  * Flush write combining store buffers (if present) and perform a write
 820  * barrier.
 821  */
 822 #if defined(CONFIG_X86_64)
 823 #define ipath_flush_wc() asm volatile("sfence" ::: "memory")
 824 #else
 825 #define ipath_flush_wc() wmb()
 826 #endif
 827
 828 extern unsigned ipath_debug; /* debugging bit mask */
 829
 830 const char *ipath_get_unit_name(int unit);
 831
 832 extern struct mutex ipath_mutex;
 833
 834 #define IPATH_DRV_NAME          "ipath_core"
 835 #define IPATH_MAJOR             233
 836 #define IPATH_USER_MINOR_BASE   0
 837 #define IPATH_SMA_MINOR         128
 838 #define IPATH_DIAG_MINOR_BASE   129
 839 #define IPATH_NMINORS           255
 840
 841 #define ipath_dev_err(dd,fmt,...) \
 842         do { \
 843                 const struct ipath_devdata *__dd = (dd); \
 844                 if (__dd->pcidev) \
 845                         dev_err(&__dd->pcidev->dev, "%s: " fmt, \
 846                                 ipath_get_unit_name(__dd->ipath_unit), \
 847                                 ##__VA_ARGS__); \
 848                 else \
 849                         printk(KERN_ERR IPATH_DRV_NAME ": %s: " fmt, \
 850                                ipath_get_unit_name(__dd->ipath_unit), \
 851                                ##__VA_ARGS__); \
 852         } while (0)
 853
 854 #if _IPATH_DEBUGGING
 855
 856 # define __IPATH_DBG_WHICH(which,fmt,...) \
 857         do { \
 858                 if(unlikely(ipath_debug&(which))) \
 859                         printk(KERN_DEBUG IPATH_DRV_NAME ": %s: " fmt, \
 860                                __func__,##__VA_ARGS__); \
 861         } while(0)
 862
 863 # define ipath_dbg(fmt,...) \
 864         __IPATH_DBG_WHICH(__IPATH_DBG,fmt,##__VA_ARGS__)
 865 # define ipath_cdbg(which,fmt,...) \
 866         __IPATH_DBG_WHICH(__IPATH_##which##DBG,fmt,##__VA_ARGS__)
 867
 868 #else /* ! _IPATH_DEBUGGING */
 869
 870 # define ipath_dbg(fmt,...)
 871 # define ipath_cdbg(which,fmt,...)
 872
 873 #endif /* _IPATH_DEBUGGING */
 874
 875 #endif                          /* _IPATH_KERNEL_H */