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mlx4: In RoCE allow guests to have multiple GIDS
[deliverable/linux.git] / drivers / infiniband / hw / mlx4 / mad.c
1 /*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <rdma/ib_mad.h>
34 #include <rdma/ib_smi.h>
35 #include <rdma/ib_sa.h>
36 #include <rdma/ib_cache.h>
37
38 #include <linux/random.h>
39 #include <linux/mlx4/cmd.h>
40 #include <linux/gfp.h>
41 #include <rdma/ib_pma.h>
42
43 #include "mlx4_ib.h"
44
45 enum {
46 MLX4_IB_VENDOR_CLASS1 = 0x9,
47 MLX4_IB_VENDOR_CLASS2 = 0xa
48 };
49
50 #define MLX4_TUN_SEND_WRID_SHIFT 34
51 #define MLX4_TUN_QPN_SHIFT 32
52 #define MLX4_TUN_WRID_RECV (((u64) 1) << MLX4_TUN_SEND_WRID_SHIFT)
53 #define MLX4_TUN_SET_WRID_QPN(a) (((u64) ((a) & 0x3)) << MLX4_TUN_QPN_SHIFT)
54
55 #define MLX4_TUN_IS_RECV(a) (((a) >> MLX4_TUN_SEND_WRID_SHIFT) & 0x1)
56 #define MLX4_TUN_WRID_QPN(a) (((a) >> MLX4_TUN_QPN_SHIFT) & 0x3)
57
58 /* Port mgmt change event handling */
59
60 #define GET_BLK_PTR_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.block_ptr)
61 #define GET_MASK_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.tbl_entries_mask)
62 #define NUM_IDX_IN_PKEY_TBL_BLK 32
63 #define GUID_TBL_ENTRY_SIZE 8 /* size in bytes */
64 #define GUID_TBL_BLK_NUM_ENTRIES 8
65 #define GUID_TBL_BLK_SIZE (GUID_TBL_ENTRY_SIZE * GUID_TBL_BLK_NUM_ENTRIES)
66
67 struct mlx4_mad_rcv_buf {
68 struct ib_grh grh;
69 u8 payload[256];
70 } __packed;
71
72 struct mlx4_mad_snd_buf {
73 u8 payload[256];
74 } __packed;
75
76 struct mlx4_tunnel_mad {
77 struct ib_grh grh;
78 struct mlx4_ib_tunnel_header hdr;
79 struct ib_mad mad;
80 } __packed;
81
82 struct mlx4_rcv_tunnel_mad {
83 struct mlx4_rcv_tunnel_hdr hdr;
84 struct ib_grh grh;
85 struct ib_mad mad;
86 } __packed;
87
88 static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num);
89 static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num);
90 static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
91 int block, u32 change_bitmap);
92
93 __be64 mlx4_ib_gen_node_guid(void)
94 {
95 #define NODE_GUID_HI ((u64) (((u64)IB_OPENIB_OUI) << 40))
96 return cpu_to_be64(NODE_GUID_HI | prandom_u32());
97 }
98
99 __be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx)
100 {
101 return cpu_to_be64(atomic_inc_return(&ctx->tid)) |
102 cpu_to_be64(0xff00000000000000LL);
103 }
104
105 int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags,
106 int port, struct ib_wc *in_wc, struct ib_grh *in_grh,
107 void *in_mad, void *response_mad)
108 {
109 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
110 void *inbox;
111 int err;
112 u32 in_modifier = port;
113 u8 op_modifier = 0;
114
115 inmailbox = mlx4_alloc_cmd_mailbox(dev->dev);
116 if (IS_ERR(inmailbox))
117 return PTR_ERR(inmailbox);
118 inbox = inmailbox->buf;
119
120 outmailbox = mlx4_alloc_cmd_mailbox(dev->dev);
121 if (IS_ERR(outmailbox)) {
122 mlx4_free_cmd_mailbox(dev->dev, inmailbox);
123 return PTR_ERR(outmailbox);
124 }
125
126 memcpy(inbox, in_mad, 256);
127
128 /*
129 * Key check traps can't be generated unless we have in_wc to
130 * tell us where to send the trap.
131 */
132 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_MKEY) || !in_wc)
133 op_modifier |= 0x1;
134 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_BKEY) || !in_wc)
135 op_modifier |= 0x2;
136 if (mlx4_is_mfunc(dev->dev) &&
137 (mad_ifc_flags & MLX4_MAD_IFC_NET_VIEW || in_wc))
138 op_modifier |= 0x8;
139
140 if (in_wc) {
141 struct {
142 __be32 my_qpn;
143 u32 reserved1;
144 __be32 rqpn;
145 u8 sl;
146 u8 g_path;
147 u16 reserved2[2];
148 __be16 pkey;
149 u32 reserved3[11];
150 u8 grh[40];
151 } *ext_info;
152
153 memset(inbox + 256, 0, 256);
154 ext_info = inbox + 256;
155
156 ext_info->my_qpn = cpu_to_be32(in_wc->qp->qp_num);
157 ext_info->rqpn = cpu_to_be32(in_wc->src_qp);
158 ext_info->sl = in_wc->sl << 4;
159 ext_info->g_path = in_wc->dlid_path_bits |
160 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
161 ext_info->pkey = cpu_to_be16(in_wc->pkey_index);
162
163 if (in_grh)
164 memcpy(ext_info->grh, in_grh, 40);
165
166 op_modifier |= 0x4;
167
168 in_modifier |= in_wc->slid << 16;
169 }
170
171 err = mlx4_cmd_box(dev->dev, inmailbox->dma, outmailbox->dma, in_modifier,
172 mlx4_is_master(dev->dev) ? (op_modifier & ~0x8) : op_modifier,
173 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
174 (op_modifier & 0x8) ? MLX4_CMD_NATIVE : MLX4_CMD_WRAPPED);
175
176 if (!err)
177 memcpy(response_mad, outmailbox->buf, 256);
178
179 mlx4_free_cmd_mailbox(dev->dev, inmailbox);
180 mlx4_free_cmd_mailbox(dev->dev, outmailbox);
181
182 return err;
183 }
184
185 static void update_sm_ah(struct mlx4_ib_dev *dev, u8 port_num, u16 lid, u8 sl)
186 {
187 struct ib_ah *new_ah;
188 struct ib_ah_attr ah_attr;
189 unsigned long flags;
190
191 if (!dev->send_agent[port_num - 1][0])
192 return;
193
194 memset(&ah_attr, 0, sizeof ah_attr);
195 ah_attr.dlid = lid;
196 ah_attr.sl = sl;
197 ah_attr.port_num = port_num;
198
199 new_ah = ib_create_ah(dev->send_agent[port_num - 1][0]->qp->pd,
200 &ah_attr);
201 if (IS_ERR(new_ah))
202 return;
203
204 spin_lock_irqsave(&dev->sm_lock, flags);
205 if (dev->sm_ah[port_num - 1])
206 ib_destroy_ah(dev->sm_ah[port_num - 1]);
207 dev->sm_ah[port_num - 1] = new_ah;
208 spin_unlock_irqrestore(&dev->sm_lock, flags);
209 }
210
211 /*
212 * Snoop SM MADs for port info, GUID info, and P_Key table sets, so we can
213 * synthesize LID change, Client-Rereg, GID change, and P_Key change events.
214 */
215 static void smp_snoop(struct ib_device *ibdev, u8 port_num, struct ib_mad *mad,
216 u16 prev_lid)
217 {
218 struct ib_port_info *pinfo;
219 u16 lid;
220 __be16 *base;
221 u32 bn, pkey_change_bitmap;
222 int i;
223
224
225 struct mlx4_ib_dev *dev = to_mdev(ibdev);
226 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
227 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
228 mad->mad_hdr.method == IB_MGMT_METHOD_SET)
229 switch (mad->mad_hdr.attr_id) {
230 case IB_SMP_ATTR_PORT_INFO:
231 pinfo = (struct ib_port_info *) ((struct ib_smp *) mad)->data;
232 lid = be16_to_cpu(pinfo->lid);
233
234 update_sm_ah(dev, port_num,
235 be16_to_cpu(pinfo->sm_lid),
236 pinfo->neighbormtu_mastersmsl & 0xf);
237
238 if (pinfo->clientrereg_resv_subnetto & 0x80)
239 handle_client_rereg_event(dev, port_num);
240
241 if (prev_lid != lid)
242 handle_lid_change_event(dev, port_num);
243 break;
244
245 case IB_SMP_ATTR_PKEY_TABLE:
246 if (!mlx4_is_mfunc(dev->dev)) {
247 mlx4_ib_dispatch_event(dev, port_num,
248 IB_EVENT_PKEY_CHANGE);
249 break;
250 }
251
252 /* at this point, we are running in the master.
253 * Slaves do not receive SMPs.
254 */
255 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod) & 0xFFFF;
256 base = (__be16 *) &(((struct ib_smp *)mad)->data[0]);
257 pkey_change_bitmap = 0;
258 for (i = 0; i < 32; i++) {
259 pr_debug("PKEY[%d] = x%x\n",
260 i + bn*32, be16_to_cpu(base[i]));
261 if (be16_to_cpu(base[i]) !=
262 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32]) {
263 pkey_change_bitmap |= (1 << i);
264 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32] =
265 be16_to_cpu(base[i]);
266 }
267 }
268 pr_debug("PKEY Change event: port=%d, "
269 "block=0x%x, change_bitmap=0x%x\n",
270 port_num, bn, pkey_change_bitmap);
271
272 if (pkey_change_bitmap) {
273 mlx4_ib_dispatch_event(dev, port_num,
274 IB_EVENT_PKEY_CHANGE);
275 if (!dev->sriov.is_going_down)
276 __propagate_pkey_ev(dev, port_num, bn,
277 pkey_change_bitmap);
278 }
279 break;
280
281 case IB_SMP_ATTR_GUID_INFO:
282 /* paravirtualized master's guid is guid 0 -- does not change */
283 if (!mlx4_is_master(dev->dev))
284 mlx4_ib_dispatch_event(dev, port_num,
285 IB_EVENT_GID_CHANGE);
286 /*if master, notify relevant slaves*/
287 if (mlx4_is_master(dev->dev) &&
288 !dev->sriov.is_going_down) {
289 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod);
290 mlx4_ib_update_cache_on_guid_change(dev, bn, port_num,
291 (u8 *)(&((struct ib_smp *)mad)->data));
292 mlx4_ib_notify_slaves_on_guid_change(dev, bn, port_num,
293 (u8 *)(&((struct ib_smp *)mad)->data));
294 }
295 break;
296
297 default:
298 break;
299 }
300 }
301
302 static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
303 int block, u32 change_bitmap)
304 {
305 int i, ix, slave, err;
306 int have_event = 0;
307
308 for (slave = 0; slave < dev->dev->caps.sqp_demux; slave++) {
309 if (slave == mlx4_master_func_num(dev->dev))
310 continue;
311 if (!mlx4_is_slave_active(dev->dev, slave))
312 continue;
313
314 have_event = 0;
315 for (i = 0; i < 32; i++) {
316 if (!(change_bitmap & (1 << i)))
317 continue;
318 for (ix = 0;
319 ix < dev->dev->caps.pkey_table_len[port_num]; ix++) {
320 if (dev->pkeys.virt2phys_pkey[slave][port_num - 1]
321 [ix] == i + 32 * block) {
322 err = mlx4_gen_pkey_eqe(dev->dev, slave, port_num);
323 pr_debug("propagate_pkey_ev: slave %d,"
324 " port %d, ix %d (%d)\n",
325 slave, port_num, ix, err);
326 have_event = 1;
327 break;
328 }
329 }
330 if (have_event)
331 break;
332 }
333 }
334 }
335
336 static void node_desc_override(struct ib_device *dev,
337 struct ib_mad *mad)
338 {
339 unsigned long flags;
340
341 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
342 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
343 mad->mad_hdr.method == IB_MGMT_METHOD_GET_RESP &&
344 mad->mad_hdr.attr_id == IB_SMP_ATTR_NODE_DESC) {
345 spin_lock_irqsave(&to_mdev(dev)->sm_lock, flags);
346 memcpy(((struct ib_smp *) mad)->data, dev->node_desc, 64);
347 spin_unlock_irqrestore(&to_mdev(dev)->sm_lock, flags);
348 }
349 }
350
351 static void forward_trap(struct mlx4_ib_dev *dev, u8 port_num, struct ib_mad *mad)
352 {
353 int qpn = mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_SUBN_LID_ROUTED;
354 struct ib_mad_send_buf *send_buf;
355 struct ib_mad_agent *agent = dev->send_agent[port_num - 1][qpn];
356 int ret;
357 unsigned long flags;
358
359 if (agent) {
360 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR,
361 IB_MGMT_MAD_DATA, GFP_ATOMIC);
362 if (IS_ERR(send_buf))
363 return;
364 /*
365 * We rely here on the fact that MLX QPs don't use the
366 * address handle after the send is posted (this is
367 * wrong following the IB spec strictly, but we know
368 * it's OK for our devices).
369 */
370 spin_lock_irqsave(&dev->sm_lock, flags);
371 memcpy(send_buf->mad, mad, sizeof *mad);
372 if ((send_buf->ah = dev->sm_ah[port_num - 1]))
373 ret = ib_post_send_mad(send_buf, NULL);
374 else
375 ret = -EINVAL;
376 spin_unlock_irqrestore(&dev->sm_lock, flags);
377
378 if (ret)
379 ib_free_send_mad(send_buf);
380 }
381 }
382
383 static int mlx4_ib_demux_sa_handler(struct ib_device *ibdev, int port, int slave,
384 struct ib_sa_mad *sa_mad)
385 {
386 int ret = 0;
387
388 /* dispatch to different sa handlers */
389 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) {
390 case IB_SA_ATTR_MC_MEMBER_REC:
391 ret = mlx4_ib_mcg_demux_handler(ibdev, port, slave, sa_mad);
392 break;
393 default:
394 break;
395 }
396 return ret;
397 }
398
399 int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid)
400 {
401 struct mlx4_ib_dev *dev = to_mdev(ibdev);
402 int i;
403
404 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
405 if (dev->sriov.demux[port - 1].guid_cache[i] == guid)
406 return i;
407 }
408 return -1;
409 }
410
411
412 static int find_slave_port_pkey_ix(struct mlx4_ib_dev *dev, int slave,
413 u8 port, u16 pkey, u16 *ix)
414 {
415 int i, ret;
416 u8 unassigned_pkey_ix, pkey_ix, partial_ix = 0xFF;
417 u16 slot_pkey;
418
419 if (slave == mlx4_master_func_num(dev->dev))
420 return ib_find_cached_pkey(&dev->ib_dev, port, pkey, ix);
421
422 unassigned_pkey_ix = dev->dev->phys_caps.pkey_phys_table_len[port] - 1;
423
424 for (i = 0; i < dev->dev->caps.pkey_table_len[port]; i++) {
425 if (dev->pkeys.virt2phys_pkey[slave][port - 1][i] == unassigned_pkey_ix)
426 continue;
427
428 pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][i];
429
430 ret = ib_get_cached_pkey(&dev->ib_dev, port, pkey_ix, &slot_pkey);
431 if (ret)
432 continue;
433 if ((slot_pkey & 0x7FFF) == (pkey & 0x7FFF)) {
434 if (slot_pkey & 0x8000) {
435 *ix = (u16) pkey_ix;
436 return 0;
437 } else {
438 /* take first partial pkey index found */
439 if (partial_ix == 0xFF)
440 partial_ix = pkey_ix;
441 }
442 }
443 }
444
445 if (partial_ix < 0xFF) {
446 *ix = (u16) partial_ix;
447 return 0;
448 }
449
450 return -EINVAL;
451 }
452
453 int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port,
454 enum ib_qp_type dest_qpt, struct ib_wc *wc,
455 struct ib_grh *grh, struct ib_mad *mad)
456 {
457 struct ib_sge list;
458 struct ib_send_wr wr, *bad_wr;
459 struct mlx4_ib_demux_pv_ctx *tun_ctx;
460 struct mlx4_ib_demux_pv_qp *tun_qp;
461 struct mlx4_rcv_tunnel_mad *tun_mad;
462 struct ib_ah_attr attr;
463 struct ib_ah *ah;
464 struct ib_qp *src_qp = NULL;
465 unsigned tun_tx_ix = 0;
466 int dqpn;
467 int ret = 0;
468 u16 tun_pkey_ix;
469 u16 cached_pkey;
470 u8 is_eth = dev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
471
472 if (dest_qpt > IB_QPT_GSI)
473 return -EINVAL;
474
475 tun_ctx = dev->sriov.demux[port-1].tun[slave];
476
477 /* check if proxy qp created */
478 if (!tun_ctx || tun_ctx->state != DEMUX_PV_STATE_ACTIVE)
479 return -EAGAIN;
480
481 /* QP0 forwarding only for Dom0 */
482 if (!dest_qpt && (mlx4_master_func_num(dev->dev) != slave))
483 return -EINVAL;
484
485 if (!dest_qpt)
486 tun_qp = &tun_ctx->qp[0];
487 else
488 tun_qp = &tun_ctx->qp[1];
489
490 /* compute P_Key index to put in tunnel header for slave */
491 if (dest_qpt) {
492 u16 pkey_ix;
493 ret = ib_get_cached_pkey(&dev->ib_dev, port, wc->pkey_index, &cached_pkey);
494 if (ret)
495 return -EINVAL;
496
497 ret = find_slave_port_pkey_ix(dev, slave, port, cached_pkey, &pkey_ix);
498 if (ret)
499 return -EINVAL;
500 tun_pkey_ix = pkey_ix;
501 } else
502 tun_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0];
503
504 dqpn = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave + port + (dest_qpt * 2) - 1;
505
506 /* get tunnel tx data buf for slave */
507 src_qp = tun_qp->qp;
508
509 /* create ah. Just need an empty one with the port num for the post send.
510 * The driver will set the force loopback bit in post_send */
511 memset(&attr, 0, sizeof attr);
512 attr.port_num = port;
513 if (is_eth) {
514 memcpy(&attr.grh.dgid.raw[0], &grh->dgid.raw[0], 16);
515 attr.ah_flags = IB_AH_GRH;
516 }
517 ah = ib_create_ah(tun_ctx->pd, &attr);
518 if (IS_ERR(ah))
519 return -ENOMEM;
520
521 /* allocate tunnel tx buf after pass failure returns */
522 spin_lock(&tun_qp->tx_lock);
523 if (tun_qp->tx_ix_head - tun_qp->tx_ix_tail >=
524 (MLX4_NUM_TUNNEL_BUFS - 1))
525 ret = -EAGAIN;
526 else
527 tun_tx_ix = (++tun_qp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1);
528 spin_unlock(&tun_qp->tx_lock);
529 if (ret)
530 goto out;
531
532 tun_mad = (struct mlx4_rcv_tunnel_mad *) (tun_qp->tx_ring[tun_tx_ix].buf.addr);
533 if (tun_qp->tx_ring[tun_tx_ix].ah)
534 ib_destroy_ah(tun_qp->tx_ring[tun_tx_ix].ah);
535 tun_qp->tx_ring[tun_tx_ix].ah = ah;
536 ib_dma_sync_single_for_cpu(&dev->ib_dev,
537 tun_qp->tx_ring[tun_tx_ix].buf.map,
538 sizeof (struct mlx4_rcv_tunnel_mad),
539 DMA_TO_DEVICE);
540
541 /* copy over to tunnel buffer */
542 if (grh)
543 memcpy(&tun_mad->grh, grh, sizeof *grh);
544 memcpy(&tun_mad->mad, mad, sizeof *mad);
545
546 /* adjust tunnel data */
547 tun_mad->hdr.pkey_index = cpu_to_be16(tun_pkey_ix);
548 tun_mad->hdr.sl_vid = cpu_to_be16(((u16)(wc->sl)) << 12);
549 tun_mad->hdr.slid_mac_47_32 = cpu_to_be16(wc->slid);
550 tun_mad->hdr.flags_src_qp = cpu_to_be32(wc->src_qp & 0xFFFFFF);
551 tun_mad->hdr.g_ml_path = (grh && (wc->wc_flags & IB_WC_GRH)) ? 0x80 : 0;
552
553 ib_dma_sync_single_for_device(&dev->ib_dev,
554 tun_qp->tx_ring[tun_tx_ix].buf.map,
555 sizeof (struct mlx4_rcv_tunnel_mad),
556 DMA_TO_DEVICE);
557
558 list.addr = tun_qp->tx_ring[tun_tx_ix].buf.map;
559 list.length = sizeof (struct mlx4_rcv_tunnel_mad);
560 list.lkey = tun_ctx->mr->lkey;
561
562 wr.wr.ud.ah = ah;
563 wr.wr.ud.port_num = port;
564 wr.wr.ud.remote_qkey = IB_QP_SET_QKEY;
565 wr.wr.ud.remote_qpn = dqpn;
566 wr.next = NULL;
567 wr.wr_id = ((u64) tun_tx_ix) | MLX4_TUN_SET_WRID_QPN(dest_qpt);
568 wr.sg_list = &list;
569 wr.num_sge = 1;
570 wr.opcode = IB_WR_SEND;
571 wr.send_flags = IB_SEND_SIGNALED;
572
573 ret = ib_post_send(src_qp, &wr, &bad_wr);
574 out:
575 if (ret)
576 ib_destroy_ah(ah);
577 return ret;
578 }
579
580 static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port,
581 struct ib_wc *wc, struct ib_grh *grh,
582 struct ib_mad *mad)
583 {
584 struct mlx4_ib_dev *dev = to_mdev(ibdev);
585 int err;
586 int slave;
587 u8 *slave_id;
588 int is_eth = 0;
589
590 if (rdma_port_get_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND)
591 is_eth = 0;
592 else
593 is_eth = 1;
594
595 if (is_eth) {
596 if (!(wc->wc_flags & IB_WC_GRH)) {
597 mlx4_ib_warn(ibdev, "RoCE grh not present.\n");
598 return -EINVAL;
599 }
600 if (mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_CM) {
601 mlx4_ib_warn(ibdev, "RoCE mgmt class is not CM\n");
602 return -EINVAL;
603 }
604 if (mlx4_get_slave_from_roce_gid(dev->dev, port, grh->dgid.raw, &slave)) {
605 mlx4_ib_warn(ibdev, "failed matching grh\n");
606 return -ENOENT;
607 }
608 if (slave >= dev->dev->caps.sqp_demux) {
609 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n",
610 slave, dev->dev->caps.sqp_demux);
611 return -ENOENT;
612 }
613
614 if (mlx4_ib_demux_cm_handler(ibdev, port, NULL, mad))
615 return 0;
616
617 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad);
618 if (err)
619 pr_debug("failed sending to slave %d via tunnel qp (%d)\n",
620 slave, err);
621 return 0;
622 }
623
624 /* Initially assume that this mad is for us */
625 slave = mlx4_master_func_num(dev->dev);
626
627 /* See if the slave id is encoded in a response mad */
628 if (mad->mad_hdr.method & 0x80) {
629 slave_id = (u8 *) &mad->mad_hdr.tid;
630 slave = *slave_id;
631 if (slave != 255) /*255 indicates the dom0*/
632 *slave_id = 0; /* remap tid */
633 }
634
635 /* If a grh is present, we demux according to it */
636 if (wc->wc_flags & IB_WC_GRH) {
637 slave = mlx4_ib_find_real_gid(ibdev, port, grh->dgid.global.interface_id);
638 if (slave < 0) {
639 mlx4_ib_warn(ibdev, "failed matching grh\n");
640 return -ENOENT;
641 }
642 }
643 /* Class-specific handling */
644 switch (mad->mad_hdr.mgmt_class) {
645 case IB_MGMT_CLASS_SUBN_ADM:
646 if (mlx4_ib_demux_sa_handler(ibdev, port, slave,
647 (struct ib_sa_mad *) mad))
648 return 0;
649 break;
650 case IB_MGMT_CLASS_CM:
651 if (mlx4_ib_demux_cm_handler(ibdev, port, &slave, mad))
652 return 0;
653 break;
654 case IB_MGMT_CLASS_DEVICE_MGMT:
655 if (mad->mad_hdr.method != IB_MGMT_METHOD_GET_RESP)
656 return 0;
657 break;
658 default:
659 /* Drop unsupported classes for slaves in tunnel mode */
660 if (slave != mlx4_master_func_num(dev->dev)) {
661 pr_debug("dropping unsupported ingress mad from class:%d "
662 "for slave:%d\n", mad->mad_hdr.mgmt_class, slave);
663 return 0;
664 }
665 }
666 /*make sure that no slave==255 was not handled yet.*/
667 if (slave >= dev->dev->caps.sqp_demux) {
668 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n",
669 slave, dev->dev->caps.sqp_demux);
670 return -ENOENT;
671 }
672
673 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad);
674 if (err)
675 pr_debug("failed sending to slave %d via tunnel qp (%d)\n",
676 slave, err);
677 return 0;
678 }
679
680 static int ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
681 struct ib_wc *in_wc, struct ib_grh *in_grh,
682 struct ib_mad *in_mad, struct ib_mad *out_mad)
683 {
684 u16 slid, prev_lid = 0;
685 int err;
686 struct ib_port_attr pattr;
687
688 if (in_wc && in_wc->qp->qp_num) {
689 pr_debug("received MAD: slid:%d sqpn:%d "
690 "dlid_bits:%d dqpn:%d wc_flags:0x%x, cls %x, mtd %x, atr %x\n",
691 in_wc->slid, in_wc->src_qp,
692 in_wc->dlid_path_bits,
693 in_wc->qp->qp_num,
694 in_wc->wc_flags,
695 in_mad->mad_hdr.mgmt_class, in_mad->mad_hdr.method,
696 be16_to_cpu(in_mad->mad_hdr.attr_id));
697 if (in_wc->wc_flags & IB_WC_GRH) {
698 pr_debug("sgid_hi:0x%016llx sgid_lo:0x%016llx\n",
699 be64_to_cpu(in_grh->sgid.global.subnet_prefix),
700 be64_to_cpu(in_grh->sgid.global.interface_id));
701 pr_debug("dgid_hi:0x%016llx dgid_lo:0x%016llx\n",
702 be64_to_cpu(in_grh->dgid.global.subnet_prefix),
703 be64_to_cpu(in_grh->dgid.global.interface_id));
704 }
705 }
706
707 slid = in_wc ? in_wc->slid : be16_to_cpu(IB_LID_PERMISSIVE);
708
709 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP && slid == 0) {
710 forward_trap(to_mdev(ibdev), port_num, in_mad);
711 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
712 }
713
714 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
715 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) {
716 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
717 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET &&
718 in_mad->mad_hdr.method != IB_MGMT_METHOD_TRAP_REPRESS)
719 return IB_MAD_RESULT_SUCCESS;
720
721 /*
722 * Don't process SMInfo queries -- the SMA can't handle them.
723 */
724 if (in_mad->mad_hdr.attr_id == IB_SMP_ATTR_SM_INFO)
725 return IB_MAD_RESULT_SUCCESS;
726 } else if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT ||
727 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS1 ||
728 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS2 ||
729 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_CONG_MGMT) {
730 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
731 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET)
732 return IB_MAD_RESULT_SUCCESS;
733 } else
734 return IB_MAD_RESULT_SUCCESS;
735
736 if ((in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
737 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
738 in_mad->mad_hdr.method == IB_MGMT_METHOD_SET &&
739 in_mad->mad_hdr.attr_id == IB_SMP_ATTR_PORT_INFO &&
740 !ib_query_port(ibdev, port_num, &pattr))
741 prev_lid = pattr.lid;
742
743 err = mlx4_MAD_IFC(to_mdev(ibdev),
744 (mad_flags & IB_MAD_IGNORE_MKEY ? MLX4_MAD_IFC_IGNORE_MKEY : 0) |
745 (mad_flags & IB_MAD_IGNORE_BKEY ? MLX4_MAD_IFC_IGNORE_BKEY : 0) |
746 MLX4_MAD_IFC_NET_VIEW,
747 port_num, in_wc, in_grh, in_mad, out_mad);
748 if (err)
749 return IB_MAD_RESULT_FAILURE;
750
751 if (!out_mad->mad_hdr.status) {
752 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV))
753 smp_snoop(ibdev, port_num, in_mad, prev_lid);
754 /* slaves get node desc from FW */
755 if (!mlx4_is_slave(to_mdev(ibdev)->dev))
756 node_desc_override(ibdev, out_mad);
757 }
758
759 /* set return bit in status of directed route responses */
760 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE)
761 out_mad->mad_hdr.status |= cpu_to_be16(1 << 15);
762
763 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS)
764 /* no response for trap repress */
765 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
766
767 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
768 }
769
770 static void edit_counter(struct mlx4_counter *cnt,
771 struct ib_pma_portcounters *pma_cnt)
772 {
773 pma_cnt->port_xmit_data = cpu_to_be32((be64_to_cpu(cnt->tx_bytes)>>2));
774 pma_cnt->port_rcv_data = cpu_to_be32((be64_to_cpu(cnt->rx_bytes)>>2));
775 pma_cnt->port_xmit_packets = cpu_to_be32(be64_to_cpu(cnt->tx_frames));
776 pma_cnt->port_rcv_packets = cpu_to_be32(be64_to_cpu(cnt->rx_frames));
777 }
778
779 static int iboe_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
780 struct ib_wc *in_wc, struct ib_grh *in_grh,
781 struct ib_mad *in_mad, struct ib_mad *out_mad)
782 {
783 struct mlx4_cmd_mailbox *mailbox;
784 struct mlx4_ib_dev *dev = to_mdev(ibdev);
785 int err;
786 u32 inmod = dev->counters[port_num - 1] & 0xffff;
787 u8 mode;
788
789 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT)
790 return -EINVAL;
791
792 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
793 if (IS_ERR(mailbox))
794 return IB_MAD_RESULT_FAILURE;
795
796 err = mlx4_cmd_box(dev->dev, 0, mailbox->dma, inmod, 0,
797 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
798 MLX4_CMD_WRAPPED);
799 if (err)
800 err = IB_MAD_RESULT_FAILURE;
801 else {
802 memset(out_mad->data, 0, sizeof out_mad->data);
803 mode = ((struct mlx4_counter *)mailbox->buf)->counter_mode;
804 switch (mode & 0xf) {
805 case 0:
806 edit_counter(mailbox->buf,
807 (void *)(out_mad->data + 40));
808 err = IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
809 break;
810 default:
811 err = IB_MAD_RESULT_FAILURE;
812 }
813 }
814
815 mlx4_free_cmd_mailbox(dev->dev, mailbox);
816
817 return err;
818 }
819
820 int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
821 struct ib_wc *in_wc, struct ib_grh *in_grh,
822 struct ib_mad *in_mad, struct ib_mad *out_mad)
823 {
824 switch (rdma_port_get_link_layer(ibdev, port_num)) {
825 case IB_LINK_LAYER_INFINIBAND:
826 return ib_process_mad(ibdev, mad_flags, port_num, in_wc,
827 in_grh, in_mad, out_mad);
828 case IB_LINK_LAYER_ETHERNET:
829 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc,
830 in_grh, in_mad, out_mad);
831 default:
832 return -EINVAL;
833 }
834 }
835
836 static void send_handler(struct ib_mad_agent *agent,
837 struct ib_mad_send_wc *mad_send_wc)
838 {
839 if (mad_send_wc->send_buf->context[0])
840 ib_destroy_ah(mad_send_wc->send_buf->context[0]);
841 ib_free_send_mad(mad_send_wc->send_buf);
842 }
843
844 int mlx4_ib_mad_init(struct mlx4_ib_dev *dev)
845 {
846 struct ib_mad_agent *agent;
847 int p, q;
848 int ret;
849 enum rdma_link_layer ll;
850
851 for (p = 0; p < dev->num_ports; ++p) {
852 ll = rdma_port_get_link_layer(&dev->ib_dev, p + 1);
853 for (q = 0; q <= 1; ++q) {
854 if (ll == IB_LINK_LAYER_INFINIBAND) {
855 agent = ib_register_mad_agent(&dev->ib_dev, p + 1,
856 q ? IB_QPT_GSI : IB_QPT_SMI,
857 NULL, 0, send_handler,
858 NULL, NULL);
859 if (IS_ERR(agent)) {
860 ret = PTR_ERR(agent);
861 goto err;
862 }
863 dev->send_agent[p][q] = agent;
864 } else
865 dev->send_agent[p][q] = NULL;
866 }
867 }
868
869 return 0;
870
871 err:
872 for (p = 0; p < dev->num_ports; ++p)
873 for (q = 0; q <= 1; ++q)
874 if (dev->send_agent[p][q])
875 ib_unregister_mad_agent(dev->send_agent[p][q]);
876
877 return ret;
878 }
879
880 void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev)
881 {
882 struct ib_mad_agent *agent;
883 int p, q;
884
885 for (p = 0; p < dev->num_ports; ++p) {
886 for (q = 0; q <= 1; ++q) {
887 agent = dev->send_agent[p][q];
888 if (agent) {
889 dev->send_agent[p][q] = NULL;
890 ib_unregister_mad_agent(agent);
891 }
892 }
893
894 if (dev->sm_ah[p])
895 ib_destroy_ah(dev->sm_ah[p]);
896 }
897 }
898
899 static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num)
900 {
901 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_LID_CHANGE);
902
903 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down)
904 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num,
905 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK);
906 }
907
908 static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num)
909 {
910 /* re-configure the alias-guid and mcg's */
911 if (mlx4_is_master(dev->dev)) {
912 mlx4_ib_invalidate_all_guid_record(dev, port_num);
913
914 if (!dev->sriov.is_going_down) {
915 mlx4_ib_mcg_port_cleanup(&dev->sriov.demux[port_num - 1], 0);
916 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num,
917 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK);
918 }
919 }
920 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_CLIENT_REREGISTER);
921 }
922
923 static void propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
924 struct mlx4_eqe *eqe)
925 {
926 __propagate_pkey_ev(dev, port_num, GET_BLK_PTR_FROM_EQE(eqe),
927 GET_MASK_FROM_EQE(eqe));
928 }
929
930 static void handle_slaves_guid_change(struct mlx4_ib_dev *dev, u8 port_num,
931 u32 guid_tbl_blk_num, u32 change_bitmap)
932 {
933 struct ib_smp *in_mad = NULL;
934 struct ib_smp *out_mad = NULL;
935 u16 i;
936
937 if (!mlx4_is_mfunc(dev->dev) || !mlx4_is_master(dev->dev))
938 return;
939
940 in_mad = kmalloc(sizeof *in_mad, GFP_KERNEL);
941 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
942 if (!in_mad || !out_mad) {
943 mlx4_ib_warn(&dev->ib_dev, "failed to allocate memory for guid info mads\n");
944 goto out;
945 }
946
947 guid_tbl_blk_num *= 4;
948
949 for (i = 0; i < 4; i++) {
950 if (change_bitmap && (!((change_bitmap >> (8 * i)) & 0xff)))
951 continue;
952 memset(in_mad, 0, sizeof *in_mad);
953 memset(out_mad, 0, sizeof *out_mad);
954
955 in_mad->base_version = 1;
956 in_mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
957 in_mad->class_version = 1;
958 in_mad->method = IB_MGMT_METHOD_GET;
959 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
960 in_mad->attr_mod = cpu_to_be32(guid_tbl_blk_num + i);
961
962 if (mlx4_MAD_IFC(dev,
963 MLX4_MAD_IFC_IGNORE_KEYS | MLX4_MAD_IFC_NET_VIEW,
964 port_num, NULL, NULL, in_mad, out_mad)) {
965 mlx4_ib_warn(&dev->ib_dev, "Failed in get GUID INFO MAD_IFC\n");
966 goto out;
967 }
968
969 mlx4_ib_update_cache_on_guid_change(dev, guid_tbl_blk_num + i,
970 port_num,
971 (u8 *)(&((struct ib_smp *)out_mad)->data));
972 mlx4_ib_notify_slaves_on_guid_change(dev, guid_tbl_blk_num + i,
973 port_num,
974 (u8 *)(&((struct ib_smp *)out_mad)->data));
975 }
976
977 out:
978 kfree(in_mad);
979 kfree(out_mad);
980 return;
981 }
982
983 void handle_port_mgmt_change_event(struct work_struct *work)
984 {
985 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
986 struct mlx4_ib_dev *dev = ew->ib_dev;
987 struct mlx4_eqe *eqe = &(ew->ib_eqe);
988 u8 port = eqe->event.port_mgmt_change.port;
989 u32 changed_attr;
990 u32 tbl_block;
991 u32 change_bitmap;
992
993 switch (eqe->subtype) {
994 case MLX4_DEV_PMC_SUBTYPE_PORT_INFO:
995 changed_attr = be32_to_cpu(eqe->event.port_mgmt_change.params.port_info.changed_attr);
996
997 /* Update the SM ah - This should be done before handling
998 the other changed attributes so that MADs can be sent to the SM */
999 if (changed_attr & MSTR_SM_CHANGE_MASK) {
1000 u16 lid = be16_to_cpu(eqe->event.port_mgmt_change.params.port_info.mstr_sm_lid);
1001 u8 sl = eqe->event.port_mgmt_change.params.port_info.mstr_sm_sl & 0xf;
1002 update_sm_ah(dev, port, lid, sl);
1003 }
1004
1005 /* Check if it is a lid change event */
1006 if (changed_attr & MLX4_EQ_PORT_INFO_LID_CHANGE_MASK)
1007 handle_lid_change_event(dev, port);
1008
1009 /* Generate GUID changed event */
1010 if (changed_attr & MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK) {
1011 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE);
1012 /*if master, notify all slaves*/
1013 if (mlx4_is_master(dev->dev))
1014 mlx4_gen_slaves_port_mgt_ev(dev->dev, port,
1015 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK);
1016 }
1017
1018 if (changed_attr & MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK)
1019 handle_client_rereg_event(dev, port);
1020 break;
1021
1022 case MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE:
1023 mlx4_ib_dispatch_event(dev, port, IB_EVENT_PKEY_CHANGE);
1024 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down)
1025 propagate_pkey_ev(dev, port, eqe);
1026 break;
1027 case MLX4_DEV_PMC_SUBTYPE_GUID_INFO:
1028 /* paravirtualized master's guid is guid 0 -- does not change */
1029 if (!mlx4_is_master(dev->dev))
1030 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE);
1031 /*if master, notify relevant slaves*/
1032 else if (!dev->sriov.is_going_down) {
1033 tbl_block = GET_BLK_PTR_FROM_EQE(eqe);
1034 change_bitmap = GET_MASK_FROM_EQE(eqe);
1035 handle_slaves_guid_change(dev, port, tbl_block, change_bitmap);
1036 }
1037 break;
1038 default:
1039 pr_warn("Unsupported subtype 0x%x for "
1040 "Port Management Change event\n", eqe->subtype);
1041 }
1042
1043 kfree(ew);
1044 }
1045
1046 void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num,
1047 enum ib_event_type type)
1048 {
1049 struct ib_event event;
1050
1051 event.device = &dev->ib_dev;
1052 event.element.port_num = port_num;
1053 event.event = type;
1054
1055 ib_dispatch_event(&event);
1056 }
1057
1058 static void mlx4_ib_tunnel_comp_handler(struct ib_cq *cq, void *arg)
1059 {
1060 unsigned long flags;
1061 struct mlx4_ib_demux_pv_ctx *ctx = cq->cq_context;
1062 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
1063 spin_lock_irqsave(&dev->sriov.going_down_lock, flags);
1064 if (!dev->sriov.is_going_down && ctx->state == DEMUX_PV_STATE_ACTIVE)
1065 queue_work(ctx->wq, &ctx->work);
1066 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags);
1067 }
1068
1069 static int mlx4_ib_post_pv_qp_buf(struct mlx4_ib_demux_pv_ctx *ctx,
1070 struct mlx4_ib_demux_pv_qp *tun_qp,
1071 int index)
1072 {
1073 struct ib_sge sg_list;
1074 struct ib_recv_wr recv_wr, *bad_recv_wr;
1075 int size;
1076
1077 size = (tun_qp->qp->qp_type == IB_QPT_UD) ?
1078 sizeof (struct mlx4_tunnel_mad) : sizeof (struct mlx4_mad_rcv_buf);
1079
1080 sg_list.addr = tun_qp->ring[index].map;
1081 sg_list.length = size;
1082 sg_list.lkey = ctx->mr->lkey;
1083
1084 recv_wr.next = NULL;
1085 recv_wr.sg_list = &sg_list;
1086 recv_wr.num_sge = 1;
1087 recv_wr.wr_id = (u64) index | MLX4_TUN_WRID_RECV |
1088 MLX4_TUN_SET_WRID_QPN(tun_qp->proxy_qpt);
1089 ib_dma_sync_single_for_device(ctx->ib_dev, tun_qp->ring[index].map,
1090 size, DMA_FROM_DEVICE);
1091 return ib_post_recv(tun_qp->qp, &recv_wr, &bad_recv_wr);
1092 }
1093
1094 static int mlx4_ib_multiplex_sa_handler(struct ib_device *ibdev, int port,
1095 int slave, struct ib_sa_mad *sa_mad)
1096 {
1097 int ret = 0;
1098
1099 /* dispatch to different sa handlers */
1100 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) {
1101 case IB_SA_ATTR_MC_MEMBER_REC:
1102 ret = mlx4_ib_mcg_multiplex_handler(ibdev, port, slave, sa_mad);
1103 break;
1104 default:
1105 break;
1106 }
1107 return ret;
1108 }
1109
1110 static int is_proxy_qp0(struct mlx4_ib_dev *dev, int qpn, int slave)
1111 {
1112 int proxy_start = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave;
1113
1114 return (qpn >= proxy_start && qpn <= proxy_start + 1);
1115 }
1116
1117
1118 int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port,
1119 enum ib_qp_type dest_qpt, u16 pkey_index, u32 remote_qpn,
1120 u32 qkey, struct ib_ah_attr *attr, struct ib_mad *mad)
1121 {
1122 struct ib_sge list;
1123 struct ib_send_wr wr, *bad_wr;
1124 struct mlx4_ib_demux_pv_ctx *sqp_ctx;
1125 struct mlx4_ib_demux_pv_qp *sqp;
1126 struct mlx4_mad_snd_buf *sqp_mad;
1127 struct ib_ah *ah;
1128 struct ib_qp *send_qp = NULL;
1129 unsigned wire_tx_ix = 0;
1130 int ret = 0;
1131 u16 wire_pkey_ix;
1132 int src_qpnum;
1133 u8 sgid_index;
1134
1135
1136 sqp_ctx = dev->sriov.sqps[port-1];
1137
1138 /* check if proxy qp created */
1139 if (!sqp_ctx || sqp_ctx->state != DEMUX_PV_STATE_ACTIVE)
1140 return -EAGAIN;
1141
1142 /* QP0 forwarding only for Dom0 */
1143 if (dest_qpt == IB_QPT_SMI && (mlx4_master_func_num(dev->dev) != slave))
1144 return -EINVAL;
1145
1146 if (dest_qpt == IB_QPT_SMI) {
1147 src_qpnum = 0;
1148 sqp = &sqp_ctx->qp[0];
1149 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0];
1150 } else {
1151 src_qpnum = 1;
1152 sqp = &sqp_ctx->qp[1];
1153 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][pkey_index];
1154 }
1155
1156 send_qp = sqp->qp;
1157
1158 /* create ah */
1159 sgid_index = attr->grh.sgid_index;
1160 attr->grh.sgid_index = 0;
1161 ah = ib_create_ah(sqp_ctx->pd, attr);
1162 if (IS_ERR(ah))
1163 return -ENOMEM;
1164 attr->grh.sgid_index = sgid_index;
1165 to_mah(ah)->av.ib.gid_index = sgid_index;
1166 /* get rid of force-loopback bit */
1167 to_mah(ah)->av.ib.port_pd &= cpu_to_be32(0x7FFFFFFF);
1168 spin_lock(&sqp->tx_lock);
1169 if (sqp->tx_ix_head - sqp->tx_ix_tail >=
1170 (MLX4_NUM_TUNNEL_BUFS - 1))
1171 ret = -EAGAIN;
1172 else
1173 wire_tx_ix = (++sqp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1);
1174 spin_unlock(&sqp->tx_lock);
1175 if (ret)
1176 goto out;
1177
1178 sqp_mad = (struct mlx4_mad_snd_buf *) (sqp->tx_ring[wire_tx_ix].buf.addr);
1179 if (sqp->tx_ring[wire_tx_ix].ah)
1180 ib_destroy_ah(sqp->tx_ring[wire_tx_ix].ah);
1181 sqp->tx_ring[wire_tx_ix].ah = ah;
1182 ib_dma_sync_single_for_cpu(&dev->ib_dev,
1183 sqp->tx_ring[wire_tx_ix].buf.map,
1184 sizeof (struct mlx4_mad_snd_buf),
1185 DMA_TO_DEVICE);
1186
1187 memcpy(&sqp_mad->payload, mad, sizeof *mad);
1188
1189 ib_dma_sync_single_for_device(&dev->ib_dev,
1190 sqp->tx_ring[wire_tx_ix].buf.map,
1191 sizeof (struct mlx4_mad_snd_buf),
1192 DMA_TO_DEVICE);
1193
1194 list.addr = sqp->tx_ring[wire_tx_ix].buf.map;
1195 list.length = sizeof (struct mlx4_mad_snd_buf);
1196 list.lkey = sqp_ctx->mr->lkey;
1197
1198 wr.wr.ud.ah = ah;
1199 wr.wr.ud.port_num = port;
1200 wr.wr.ud.pkey_index = wire_pkey_ix;
1201 wr.wr.ud.remote_qkey = qkey;
1202 wr.wr.ud.remote_qpn = remote_qpn;
1203 wr.next = NULL;
1204 wr.wr_id = ((u64) wire_tx_ix) | MLX4_TUN_SET_WRID_QPN(src_qpnum);
1205 wr.sg_list = &list;
1206 wr.num_sge = 1;
1207 wr.opcode = IB_WR_SEND;
1208 wr.send_flags = IB_SEND_SIGNALED;
1209
1210 ret = ib_post_send(send_qp, &wr, &bad_wr);
1211 out:
1212 if (ret)
1213 ib_destroy_ah(ah);
1214 return ret;
1215 }
1216
1217 static int get_slave_base_gid_ix(struct mlx4_ib_dev *dev, int slave, int port)
1218 {
1219 int gids;
1220 int vfs;
1221
1222 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND)
1223 return slave;
1224
1225 gids = MLX4_ROCE_MAX_GIDS - MLX4_ROCE_PF_GIDS;
1226 vfs = dev->dev->num_vfs;
1227
1228 if (slave == 0)
1229 return 0;
1230 if (slave <= gids % vfs)
1231 return MLX4_ROCE_PF_GIDS + ((gids / vfs) + 1) * (slave - 1);
1232
1233 return MLX4_ROCE_PF_GIDS + (gids % vfs) + ((gids / vfs) * (slave - 1));
1234 }
1235
1236 static void fill_in_real_sgid_index(struct mlx4_ib_dev *dev, int slave, int port,
1237 struct ib_ah_attr *ah_attr)
1238 {
1239 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND)
1240 ah_attr->grh.sgid_index = slave;
1241 else
1242 ah_attr->grh.sgid_index += get_slave_base_gid_ix(dev, slave, port);
1243 }
1244
1245 static void mlx4_ib_multiplex_mad(struct mlx4_ib_demux_pv_ctx *ctx, struct ib_wc *wc)
1246 {
1247 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
1248 struct mlx4_ib_demux_pv_qp *tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc->wr_id)];
1249 int wr_ix = wc->wr_id & (MLX4_NUM_TUNNEL_BUFS - 1);
1250 struct mlx4_tunnel_mad *tunnel = tun_qp->ring[wr_ix].addr;
1251 struct mlx4_ib_ah ah;
1252 struct ib_ah_attr ah_attr;
1253 u8 *slave_id;
1254 int slave;
1255
1256 /* Get slave that sent this packet */
1257 if (wc->src_qp < dev->dev->phys_caps.base_proxy_sqpn ||
1258 wc->src_qp >= dev->dev->phys_caps.base_proxy_sqpn + 8 * MLX4_MFUNC_MAX ||
1259 (wc->src_qp & 0x1) != ctx->port - 1 ||
1260 wc->src_qp & 0x4) {
1261 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d\n", wc->src_qp);
1262 return;
1263 }
1264 slave = ((wc->src_qp & ~0x7) - dev->dev->phys_caps.base_proxy_sqpn) / 8;
1265 if (slave != ctx->slave) {
1266 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d: "
1267 "belongs to another slave\n", wc->src_qp);
1268 return;
1269 }
1270 if (slave != mlx4_master_func_num(dev->dev) && !(wc->src_qp & 0x2)) {
1271 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d: "
1272 "non-master trying to send QP0 packets\n", wc->src_qp);
1273 return;
1274 }
1275
1276 /* Map transaction ID */
1277 ib_dma_sync_single_for_cpu(ctx->ib_dev, tun_qp->ring[wr_ix].map,
1278 sizeof (struct mlx4_tunnel_mad),
1279 DMA_FROM_DEVICE);
1280 switch (tunnel->mad.mad_hdr.method) {
1281 case IB_MGMT_METHOD_SET:
1282 case IB_MGMT_METHOD_GET:
1283 case IB_MGMT_METHOD_REPORT:
1284 case IB_SA_METHOD_GET_TABLE:
1285 case IB_SA_METHOD_DELETE:
1286 case IB_SA_METHOD_GET_MULTI:
1287 case IB_SA_METHOD_GET_TRACE_TBL:
1288 slave_id = (u8 *) &tunnel->mad.mad_hdr.tid;
1289 if (*slave_id) {
1290 mlx4_ib_warn(ctx->ib_dev, "egress mad has non-null tid msb:%d "
1291 "class:%d slave:%d\n", *slave_id,
1292 tunnel->mad.mad_hdr.mgmt_class, slave);
1293 return;
1294 } else
1295 *slave_id = slave;
1296 default:
1297 /* nothing */;
1298 }
1299
1300 /* Class-specific handling */
1301 switch (tunnel->mad.mad_hdr.mgmt_class) {
1302 case IB_MGMT_CLASS_SUBN_ADM:
1303 if (mlx4_ib_multiplex_sa_handler(ctx->ib_dev, ctx->port, slave,
1304 (struct ib_sa_mad *) &tunnel->mad))
1305 return;
1306 break;
1307 case IB_MGMT_CLASS_CM:
1308 if (mlx4_ib_multiplex_cm_handler(ctx->ib_dev, ctx->port, slave,
1309 (struct ib_mad *) &tunnel->mad))
1310 return;
1311 break;
1312 case IB_MGMT_CLASS_DEVICE_MGMT:
1313 if (tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_GET &&
1314 tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_SET)
1315 return;
1316 break;
1317 default:
1318 /* Drop unsupported classes for slaves in tunnel mode */
1319 if (slave != mlx4_master_func_num(dev->dev)) {
1320 mlx4_ib_warn(ctx->ib_dev, "dropping unsupported egress mad from class:%d "
1321 "for slave:%d\n", tunnel->mad.mad_hdr.mgmt_class, slave);
1322 return;
1323 }
1324 }
1325
1326 /* We are using standard ib_core services to send the mad, so generate a
1327 * stadard address handle by decoding the tunnelled mlx4_ah fields */
1328 memcpy(&ah.av, &tunnel->hdr.av, sizeof (struct mlx4_av));
1329 ah.ibah.device = ctx->ib_dev;
1330 mlx4_ib_query_ah(&ah.ibah, &ah_attr);
1331 if (ah_attr.ah_flags & IB_AH_GRH)
1332 fill_in_real_sgid_index(dev, slave, ctx->port, &ah_attr);
1333
1334 mlx4_ib_send_to_wire(dev, slave, ctx->port,
1335 is_proxy_qp0(dev, wc->src_qp, slave) ?
1336 IB_QPT_SMI : IB_QPT_GSI,
1337 be16_to_cpu(tunnel->hdr.pkey_index),
1338 be32_to_cpu(tunnel->hdr.remote_qpn),
1339 be32_to_cpu(tunnel->hdr.qkey),
1340 &ah_attr, &tunnel->mad);
1341 }
1342
1343 static int mlx4_ib_alloc_pv_bufs(struct mlx4_ib_demux_pv_ctx *ctx,
1344 enum ib_qp_type qp_type, int is_tun)
1345 {
1346 int i;
1347 struct mlx4_ib_demux_pv_qp *tun_qp;
1348 int rx_buf_size, tx_buf_size;
1349
1350 if (qp_type > IB_QPT_GSI)
1351 return -EINVAL;
1352
1353 tun_qp = &ctx->qp[qp_type];
1354
1355 tun_qp->ring = kzalloc(sizeof (struct mlx4_ib_buf) * MLX4_NUM_TUNNEL_BUFS,
1356 GFP_KERNEL);
1357 if (!tun_qp->ring)
1358 return -ENOMEM;
1359
1360 tun_qp->tx_ring = kcalloc(MLX4_NUM_TUNNEL_BUFS,
1361 sizeof (struct mlx4_ib_tun_tx_buf),
1362 GFP_KERNEL);
1363 if (!tun_qp->tx_ring) {
1364 kfree(tun_qp->ring);
1365 tun_qp->ring = NULL;
1366 return -ENOMEM;
1367 }
1368
1369 if (is_tun) {
1370 rx_buf_size = sizeof (struct mlx4_tunnel_mad);
1371 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad);
1372 } else {
1373 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf);
1374 tx_buf_size = sizeof (struct mlx4_mad_snd_buf);
1375 }
1376
1377 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1378 tun_qp->ring[i].addr = kmalloc(rx_buf_size, GFP_KERNEL);
1379 if (!tun_qp->ring[i].addr)
1380 goto err;
1381 tun_qp->ring[i].map = ib_dma_map_single(ctx->ib_dev,
1382 tun_qp->ring[i].addr,
1383 rx_buf_size,
1384 DMA_FROM_DEVICE);
1385 }
1386
1387 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1388 tun_qp->tx_ring[i].buf.addr =
1389 kmalloc(tx_buf_size, GFP_KERNEL);
1390 if (!tun_qp->tx_ring[i].buf.addr)
1391 goto tx_err;
1392 tun_qp->tx_ring[i].buf.map =
1393 ib_dma_map_single(ctx->ib_dev,
1394 tun_qp->tx_ring[i].buf.addr,
1395 tx_buf_size,
1396 DMA_TO_DEVICE);
1397 tun_qp->tx_ring[i].ah = NULL;
1398 }
1399 spin_lock_init(&tun_qp->tx_lock);
1400 tun_qp->tx_ix_head = 0;
1401 tun_qp->tx_ix_tail = 0;
1402 tun_qp->proxy_qpt = qp_type;
1403
1404 return 0;
1405
1406 tx_err:
1407 while (i > 0) {
1408 --i;
1409 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map,
1410 tx_buf_size, DMA_TO_DEVICE);
1411 kfree(tun_qp->tx_ring[i].buf.addr);
1412 }
1413 kfree(tun_qp->tx_ring);
1414 tun_qp->tx_ring = NULL;
1415 i = MLX4_NUM_TUNNEL_BUFS;
1416 err:
1417 while (i > 0) {
1418 --i;
1419 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map,
1420 rx_buf_size, DMA_FROM_DEVICE);
1421 kfree(tun_qp->ring[i].addr);
1422 }
1423 kfree(tun_qp->ring);
1424 tun_qp->ring = NULL;
1425 return -ENOMEM;
1426 }
1427
1428 static void mlx4_ib_free_pv_qp_bufs(struct mlx4_ib_demux_pv_ctx *ctx,
1429 enum ib_qp_type qp_type, int is_tun)
1430 {
1431 int i;
1432 struct mlx4_ib_demux_pv_qp *tun_qp;
1433 int rx_buf_size, tx_buf_size;
1434
1435 if (qp_type > IB_QPT_GSI)
1436 return;
1437
1438 tun_qp = &ctx->qp[qp_type];
1439 if (is_tun) {
1440 rx_buf_size = sizeof (struct mlx4_tunnel_mad);
1441 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad);
1442 } else {
1443 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf);
1444 tx_buf_size = sizeof (struct mlx4_mad_snd_buf);
1445 }
1446
1447
1448 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1449 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map,
1450 rx_buf_size, DMA_FROM_DEVICE);
1451 kfree(tun_qp->ring[i].addr);
1452 }
1453
1454 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1455 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map,
1456 tx_buf_size, DMA_TO_DEVICE);
1457 kfree(tun_qp->tx_ring[i].buf.addr);
1458 if (tun_qp->tx_ring[i].ah)
1459 ib_destroy_ah(tun_qp->tx_ring[i].ah);
1460 }
1461 kfree(tun_qp->tx_ring);
1462 kfree(tun_qp->ring);
1463 }
1464
1465 static void mlx4_ib_tunnel_comp_worker(struct work_struct *work)
1466 {
1467 struct mlx4_ib_demux_pv_ctx *ctx;
1468 struct mlx4_ib_demux_pv_qp *tun_qp;
1469 struct ib_wc wc;
1470 int ret;
1471 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work);
1472 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1473
1474 while (ib_poll_cq(ctx->cq, 1, &wc) == 1) {
1475 tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)];
1476 if (wc.status == IB_WC_SUCCESS) {
1477 switch (wc.opcode) {
1478 case IB_WC_RECV:
1479 mlx4_ib_multiplex_mad(ctx, &wc);
1480 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp,
1481 wc.wr_id &
1482 (MLX4_NUM_TUNNEL_BUFS - 1));
1483 if (ret)
1484 pr_err("Failed reposting tunnel "
1485 "buf:%lld\n", wc.wr_id);
1486 break;
1487 case IB_WC_SEND:
1488 pr_debug("received tunnel send completion:"
1489 "wrid=0x%llx, status=0x%x\n",
1490 wc.wr_id, wc.status);
1491 ib_destroy_ah(tun_qp->tx_ring[wc.wr_id &
1492 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1493 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1494 = NULL;
1495 spin_lock(&tun_qp->tx_lock);
1496 tun_qp->tx_ix_tail++;
1497 spin_unlock(&tun_qp->tx_lock);
1498
1499 break;
1500 default:
1501 break;
1502 }
1503 } else {
1504 pr_debug("mlx4_ib: completion error in tunnel: %d."
1505 " status = %d, wrid = 0x%llx\n",
1506 ctx->slave, wc.status, wc.wr_id);
1507 if (!MLX4_TUN_IS_RECV(wc.wr_id)) {
1508 ib_destroy_ah(tun_qp->tx_ring[wc.wr_id &
1509 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1510 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1511 = NULL;
1512 spin_lock(&tun_qp->tx_lock);
1513 tun_qp->tx_ix_tail++;
1514 spin_unlock(&tun_qp->tx_lock);
1515 }
1516 }
1517 }
1518 }
1519
1520 static void pv_qp_event_handler(struct ib_event *event, void *qp_context)
1521 {
1522 struct mlx4_ib_demux_pv_ctx *sqp = qp_context;
1523
1524 /* It's worse than that! He's dead, Jim! */
1525 pr_err("Fatal error (%d) on a MAD QP on port %d\n",
1526 event->event, sqp->port);
1527 }
1528
1529 static int create_pv_sqp(struct mlx4_ib_demux_pv_ctx *ctx,
1530 enum ib_qp_type qp_type, int create_tun)
1531 {
1532 int i, ret;
1533 struct mlx4_ib_demux_pv_qp *tun_qp;
1534 struct mlx4_ib_qp_tunnel_init_attr qp_init_attr;
1535 struct ib_qp_attr attr;
1536 int qp_attr_mask_INIT;
1537
1538 if (qp_type > IB_QPT_GSI)
1539 return -EINVAL;
1540
1541 tun_qp = &ctx->qp[qp_type];
1542
1543 memset(&qp_init_attr, 0, sizeof qp_init_attr);
1544 qp_init_attr.init_attr.send_cq = ctx->cq;
1545 qp_init_attr.init_attr.recv_cq = ctx->cq;
1546 qp_init_attr.init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
1547 qp_init_attr.init_attr.cap.max_send_wr = MLX4_NUM_TUNNEL_BUFS;
1548 qp_init_attr.init_attr.cap.max_recv_wr = MLX4_NUM_TUNNEL_BUFS;
1549 qp_init_attr.init_attr.cap.max_send_sge = 1;
1550 qp_init_attr.init_attr.cap.max_recv_sge = 1;
1551 if (create_tun) {
1552 qp_init_attr.init_attr.qp_type = IB_QPT_UD;
1553 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_TUNNEL_QP;
1554 qp_init_attr.port = ctx->port;
1555 qp_init_attr.slave = ctx->slave;
1556 qp_init_attr.proxy_qp_type = qp_type;
1557 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX |
1558 IB_QP_QKEY | IB_QP_PORT;
1559 } else {
1560 qp_init_attr.init_attr.qp_type = qp_type;
1561 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_SQP;
1562 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_QKEY;
1563 }
1564 qp_init_attr.init_attr.port_num = ctx->port;
1565 qp_init_attr.init_attr.qp_context = ctx;
1566 qp_init_attr.init_attr.event_handler = pv_qp_event_handler;
1567 tun_qp->qp = ib_create_qp(ctx->pd, &qp_init_attr.init_attr);
1568 if (IS_ERR(tun_qp->qp)) {
1569 ret = PTR_ERR(tun_qp->qp);
1570 tun_qp->qp = NULL;
1571 pr_err("Couldn't create %s QP (%d)\n",
1572 create_tun ? "tunnel" : "special", ret);
1573 return ret;
1574 }
1575
1576 memset(&attr, 0, sizeof attr);
1577 attr.qp_state = IB_QPS_INIT;
1578 ret = 0;
1579 if (create_tun)
1580 ret = find_slave_port_pkey_ix(to_mdev(ctx->ib_dev), ctx->slave,
1581 ctx->port, IB_DEFAULT_PKEY_FULL,
1582 &attr.pkey_index);
1583 if (ret || !create_tun)
1584 attr.pkey_index =
1585 to_mdev(ctx->ib_dev)->pkeys.virt2phys_pkey[ctx->slave][ctx->port - 1][0];
1586 attr.qkey = IB_QP1_QKEY;
1587 attr.port_num = ctx->port;
1588 ret = ib_modify_qp(tun_qp->qp, &attr, qp_attr_mask_INIT);
1589 if (ret) {
1590 pr_err("Couldn't change %s qp state to INIT (%d)\n",
1591 create_tun ? "tunnel" : "special", ret);
1592 goto err_qp;
1593 }
1594 attr.qp_state = IB_QPS_RTR;
1595 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE);
1596 if (ret) {
1597 pr_err("Couldn't change %s qp state to RTR (%d)\n",
1598 create_tun ? "tunnel" : "special", ret);
1599 goto err_qp;
1600 }
1601 attr.qp_state = IB_QPS_RTS;
1602 attr.sq_psn = 0;
1603 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE | IB_QP_SQ_PSN);
1604 if (ret) {
1605 pr_err("Couldn't change %s qp state to RTS (%d)\n",
1606 create_tun ? "tunnel" : "special", ret);
1607 goto err_qp;
1608 }
1609
1610 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1611 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, i);
1612 if (ret) {
1613 pr_err(" mlx4_ib_post_pv_buf error"
1614 " (err = %d, i = %d)\n", ret, i);
1615 goto err_qp;
1616 }
1617 }
1618 return 0;
1619
1620 err_qp:
1621 ib_destroy_qp(tun_qp->qp);
1622 tun_qp->qp = NULL;
1623 return ret;
1624 }
1625
1626 /*
1627 * IB MAD completion callback for real SQPs
1628 */
1629 static void mlx4_ib_sqp_comp_worker(struct work_struct *work)
1630 {
1631 struct mlx4_ib_demux_pv_ctx *ctx;
1632 struct mlx4_ib_demux_pv_qp *sqp;
1633 struct ib_wc wc;
1634 struct ib_grh *grh;
1635 struct ib_mad *mad;
1636
1637 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work);
1638 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1639
1640 while (mlx4_ib_poll_cq(ctx->cq, 1, &wc) == 1) {
1641 sqp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)];
1642 if (wc.status == IB_WC_SUCCESS) {
1643 switch (wc.opcode) {
1644 case IB_WC_SEND:
1645 ib_destroy_ah(sqp->tx_ring[wc.wr_id &
1646 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1647 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1648 = NULL;
1649 spin_lock(&sqp->tx_lock);
1650 sqp->tx_ix_tail++;
1651 spin_unlock(&sqp->tx_lock);
1652 break;
1653 case IB_WC_RECV:
1654 mad = (struct ib_mad *) &(((struct mlx4_mad_rcv_buf *)
1655 (sqp->ring[wc.wr_id &
1656 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->payload);
1657 grh = &(((struct mlx4_mad_rcv_buf *)
1658 (sqp->ring[wc.wr_id &
1659 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->grh);
1660 mlx4_ib_demux_mad(ctx->ib_dev, ctx->port, &wc, grh, mad);
1661 if (mlx4_ib_post_pv_qp_buf(ctx, sqp, wc.wr_id &
1662 (MLX4_NUM_TUNNEL_BUFS - 1)))
1663 pr_err("Failed reposting SQP "
1664 "buf:%lld\n", wc.wr_id);
1665 break;
1666 default:
1667 BUG_ON(1);
1668 break;
1669 }
1670 } else {
1671 pr_debug("mlx4_ib: completion error in tunnel: %d."
1672 " status = %d, wrid = 0x%llx\n",
1673 ctx->slave, wc.status, wc.wr_id);
1674 if (!MLX4_TUN_IS_RECV(wc.wr_id)) {
1675 ib_destroy_ah(sqp->tx_ring[wc.wr_id &
1676 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1677 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1678 = NULL;
1679 spin_lock(&sqp->tx_lock);
1680 sqp->tx_ix_tail++;
1681 spin_unlock(&sqp->tx_lock);
1682 }
1683 }
1684 }
1685 }
1686
1687 static int alloc_pv_object(struct mlx4_ib_dev *dev, int slave, int port,
1688 struct mlx4_ib_demux_pv_ctx **ret_ctx)
1689 {
1690 struct mlx4_ib_demux_pv_ctx *ctx;
1691
1692 *ret_ctx = NULL;
1693 ctx = kzalloc(sizeof (struct mlx4_ib_demux_pv_ctx), GFP_KERNEL);
1694 if (!ctx) {
1695 pr_err("failed allocating pv resource context "
1696 "for port %d, slave %d\n", port, slave);
1697 return -ENOMEM;
1698 }
1699
1700 ctx->ib_dev = &dev->ib_dev;
1701 ctx->port = port;
1702 ctx->slave = slave;
1703 *ret_ctx = ctx;
1704 return 0;
1705 }
1706
1707 static void free_pv_object(struct mlx4_ib_dev *dev, int slave, int port)
1708 {
1709 if (dev->sriov.demux[port - 1].tun[slave]) {
1710 kfree(dev->sriov.demux[port - 1].tun[slave]);
1711 dev->sriov.demux[port - 1].tun[slave] = NULL;
1712 }
1713 }
1714
1715 static int create_pv_resources(struct ib_device *ibdev, int slave, int port,
1716 int create_tun, struct mlx4_ib_demux_pv_ctx *ctx)
1717 {
1718 int ret, cq_size;
1719
1720 if (ctx->state != DEMUX_PV_STATE_DOWN)
1721 return -EEXIST;
1722
1723 ctx->state = DEMUX_PV_STATE_STARTING;
1724 /* have QP0 only on port owner, and only if link layer is IB */
1725 if (ctx->slave == mlx4_master_func_num(to_mdev(ctx->ib_dev)->dev) &&
1726 rdma_port_get_link_layer(ibdev, ctx->port) == IB_LINK_LAYER_INFINIBAND)
1727 ctx->has_smi = 1;
1728
1729 if (ctx->has_smi) {
1730 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_SMI, create_tun);
1731 if (ret) {
1732 pr_err("Failed allocating qp0 tunnel bufs (%d)\n", ret);
1733 goto err_out;
1734 }
1735 }
1736
1737 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_GSI, create_tun);
1738 if (ret) {
1739 pr_err("Failed allocating qp1 tunnel bufs (%d)\n", ret);
1740 goto err_out_qp0;
1741 }
1742
1743 cq_size = 2 * MLX4_NUM_TUNNEL_BUFS;
1744 if (ctx->has_smi)
1745 cq_size *= 2;
1746
1747 ctx->cq = ib_create_cq(ctx->ib_dev, mlx4_ib_tunnel_comp_handler,
1748 NULL, ctx, cq_size, 0);
1749 if (IS_ERR(ctx->cq)) {
1750 ret = PTR_ERR(ctx->cq);
1751 pr_err("Couldn't create tunnel CQ (%d)\n", ret);
1752 goto err_buf;
1753 }
1754
1755 ctx->pd = ib_alloc_pd(ctx->ib_dev);
1756 if (IS_ERR(ctx->pd)) {
1757 ret = PTR_ERR(ctx->pd);
1758 pr_err("Couldn't create tunnel PD (%d)\n", ret);
1759 goto err_cq;
1760 }
1761
1762 ctx->mr = ib_get_dma_mr(ctx->pd, IB_ACCESS_LOCAL_WRITE);
1763 if (IS_ERR(ctx->mr)) {
1764 ret = PTR_ERR(ctx->mr);
1765 pr_err("Couldn't get tunnel DMA MR (%d)\n", ret);
1766 goto err_pd;
1767 }
1768
1769 if (ctx->has_smi) {
1770 ret = create_pv_sqp(ctx, IB_QPT_SMI, create_tun);
1771 if (ret) {
1772 pr_err("Couldn't create %s QP0 (%d)\n",
1773 create_tun ? "tunnel for" : "", ret);
1774 goto err_mr;
1775 }
1776 }
1777
1778 ret = create_pv_sqp(ctx, IB_QPT_GSI, create_tun);
1779 if (ret) {
1780 pr_err("Couldn't create %s QP1 (%d)\n",
1781 create_tun ? "tunnel for" : "", ret);
1782 goto err_qp0;
1783 }
1784
1785 if (create_tun)
1786 INIT_WORK(&ctx->work, mlx4_ib_tunnel_comp_worker);
1787 else
1788 INIT_WORK(&ctx->work, mlx4_ib_sqp_comp_worker);
1789
1790 ctx->wq = to_mdev(ibdev)->sriov.demux[port - 1].wq;
1791
1792 ret = ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1793 if (ret) {
1794 pr_err("Couldn't arm tunnel cq (%d)\n", ret);
1795 goto err_wq;
1796 }
1797 ctx->state = DEMUX_PV_STATE_ACTIVE;
1798 return 0;
1799
1800 err_wq:
1801 ctx->wq = NULL;
1802 ib_destroy_qp(ctx->qp[1].qp);
1803 ctx->qp[1].qp = NULL;
1804
1805
1806 err_qp0:
1807 if (ctx->has_smi)
1808 ib_destroy_qp(ctx->qp[0].qp);
1809 ctx->qp[0].qp = NULL;
1810
1811 err_mr:
1812 ib_dereg_mr(ctx->mr);
1813 ctx->mr = NULL;
1814
1815 err_pd:
1816 ib_dealloc_pd(ctx->pd);
1817 ctx->pd = NULL;
1818
1819 err_cq:
1820 ib_destroy_cq(ctx->cq);
1821 ctx->cq = NULL;
1822
1823 err_buf:
1824 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, create_tun);
1825
1826 err_out_qp0:
1827 if (ctx->has_smi)
1828 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, create_tun);
1829 err_out:
1830 ctx->state = DEMUX_PV_STATE_DOWN;
1831 return ret;
1832 }
1833
1834 static void destroy_pv_resources(struct mlx4_ib_dev *dev, int slave, int port,
1835 struct mlx4_ib_demux_pv_ctx *ctx, int flush)
1836 {
1837 if (!ctx)
1838 return;
1839 if (ctx->state > DEMUX_PV_STATE_DOWN) {
1840 ctx->state = DEMUX_PV_STATE_DOWNING;
1841 if (flush)
1842 flush_workqueue(ctx->wq);
1843 if (ctx->has_smi) {
1844 ib_destroy_qp(ctx->qp[0].qp);
1845 ctx->qp[0].qp = NULL;
1846 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, 1);
1847 }
1848 ib_destroy_qp(ctx->qp[1].qp);
1849 ctx->qp[1].qp = NULL;
1850 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, 1);
1851 ib_dereg_mr(ctx->mr);
1852 ctx->mr = NULL;
1853 ib_dealloc_pd(ctx->pd);
1854 ctx->pd = NULL;
1855 ib_destroy_cq(ctx->cq);
1856 ctx->cq = NULL;
1857 ctx->state = DEMUX_PV_STATE_DOWN;
1858 }
1859 }
1860
1861 static int mlx4_ib_tunnels_update(struct mlx4_ib_dev *dev, int slave,
1862 int port, int do_init)
1863 {
1864 int ret = 0;
1865
1866 if (!do_init) {
1867 clean_vf_mcast(&dev->sriov.demux[port - 1], slave);
1868 /* for master, destroy real sqp resources */
1869 if (slave == mlx4_master_func_num(dev->dev))
1870 destroy_pv_resources(dev, slave, port,
1871 dev->sriov.sqps[port - 1], 1);
1872 /* destroy the tunnel qp resources */
1873 destroy_pv_resources(dev, slave, port,
1874 dev->sriov.demux[port - 1].tun[slave], 1);
1875 return 0;
1876 }
1877
1878 /* create the tunnel qp resources */
1879 ret = create_pv_resources(&dev->ib_dev, slave, port, 1,
1880 dev->sriov.demux[port - 1].tun[slave]);
1881
1882 /* for master, create the real sqp resources */
1883 if (!ret && slave == mlx4_master_func_num(dev->dev))
1884 ret = create_pv_resources(&dev->ib_dev, slave, port, 0,
1885 dev->sriov.sqps[port - 1]);
1886 return ret;
1887 }
1888
1889 void mlx4_ib_tunnels_update_work(struct work_struct *work)
1890 {
1891 struct mlx4_ib_demux_work *dmxw;
1892
1893 dmxw = container_of(work, struct mlx4_ib_demux_work, work);
1894 mlx4_ib_tunnels_update(dmxw->dev, dmxw->slave, (int) dmxw->port,
1895 dmxw->do_init);
1896 kfree(dmxw);
1897 return;
1898 }
1899
1900 static int mlx4_ib_alloc_demux_ctx(struct mlx4_ib_dev *dev,
1901 struct mlx4_ib_demux_ctx *ctx,
1902 int port)
1903 {
1904 char name[12];
1905 int ret = 0;
1906 int i;
1907
1908 ctx->tun = kcalloc(dev->dev->caps.sqp_demux,
1909 sizeof (struct mlx4_ib_demux_pv_ctx *), GFP_KERNEL);
1910 if (!ctx->tun)
1911 return -ENOMEM;
1912
1913 ctx->dev = dev;
1914 ctx->port = port;
1915 ctx->ib_dev = &dev->ib_dev;
1916
1917 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
1918 ret = alloc_pv_object(dev, i, port, &ctx->tun[i]);
1919 if (ret) {
1920 ret = -ENOMEM;
1921 goto err_mcg;
1922 }
1923 }
1924
1925 ret = mlx4_ib_mcg_port_init(ctx);
1926 if (ret) {
1927 pr_err("Failed initializing mcg para-virt (%d)\n", ret);
1928 goto err_mcg;
1929 }
1930
1931 snprintf(name, sizeof name, "mlx4_ibt%d", port);
1932 ctx->wq = create_singlethread_workqueue(name);
1933 if (!ctx->wq) {
1934 pr_err("Failed to create tunnelling WQ for port %d\n", port);
1935 ret = -ENOMEM;
1936 goto err_wq;
1937 }
1938
1939 snprintf(name, sizeof name, "mlx4_ibud%d", port);
1940 ctx->ud_wq = create_singlethread_workqueue(name);
1941 if (!ctx->ud_wq) {
1942 pr_err("Failed to create up/down WQ for port %d\n", port);
1943 ret = -ENOMEM;
1944 goto err_udwq;
1945 }
1946
1947 return 0;
1948
1949 err_udwq:
1950 destroy_workqueue(ctx->wq);
1951 ctx->wq = NULL;
1952
1953 err_wq:
1954 mlx4_ib_mcg_port_cleanup(ctx, 1);
1955 err_mcg:
1956 for (i = 0; i < dev->dev->caps.sqp_demux; i++)
1957 free_pv_object(dev, i, port);
1958 kfree(ctx->tun);
1959 ctx->tun = NULL;
1960 return ret;
1961 }
1962
1963 static void mlx4_ib_free_sqp_ctx(struct mlx4_ib_demux_pv_ctx *sqp_ctx)
1964 {
1965 if (sqp_ctx->state > DEMUX_PV_STATE_DOWN) {
1966 sqp_ctx->state = DEMUX_PV_STATE_DOWNING;
1967 flush_workqueue(sqp_ctx->wq);
1968 if (sqp_ctx->has_smi) {
1969 ib_destroy_qp(sqp_ctx->qp[0].qp);
1970 sqp_ctx->qp[0].qp = NULL;
1971 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_SMI, 0);
1972 }
1973 ib_destroy_qp(sqp_ctx->qp[1].qp);
1974 sqp_ctx->qp[1].qp = NULL;
1975 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_GSI, 0);
1976 ib_dereg_mr(sqp_ctx->mr);
1977 sqp_ctx->mr = NULL;
1978 ib_dealloc_pd(sqp_ctx->pd);
1979 sqp_ctx->pd = NULL;
1980 ib_destroy_cq(sqp_ctx->cq);
1981 sqp_ctx->cq = NULL;
1982 sqp_ctx->state = DEMUX_PV_STATE_DOWN;
1983 }
1984 }
1985
1986 static void mlx4_ib_free_demux_ctx(struct mlx4_ib_demux_ctx *ctx)
1987 {
1988 int i;
1989 if (ctx) {
1990 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
1991 mlx4_ib_mcg_port_cleanup(ctx, 1);
1992 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
1993 if (!ctx->tun[i])
1994 continue;
1995 if (ctx->tun[i]->state > DEMUX_PV_STATE_DOWN)
1996 ctx->tun[i]->state = DEMUX_PV_STATE_DOWNING;
1997 }
1998 flush_workqueue(ctx->wq);
1999 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2000 destroy_pv_resources(dev, i, ctx->port, ctx->tun[i], 0);
2001 free_pv_object(dev, i, ctx->port);
2002 }
2003 kfree(ctx->tun);
2004 destroy_workqueue(ctx->ud_wq);
2005 destroy_workqueue(ctx->wq);
2006 }
2007 }
2008
2009 static void mlx4_ib_master_tunnels(struct mlx4_ib_dev *dev, int do_init)
2010 {
2011 int i;
2012
2013 if (!mlx4_is_master(dev->dev))
2014 return;
2015 /* initialize or tear down tunnel QPs for the master */
2016 for (i = 0; i < dev->dev->caps.num_ports; i++)
2017 mlx4_ib_tunnels_update(dev, mlx4_master_func_num(dev->dev), i + 1, do_init);
2018 return;
2019 }
2020
2021 int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev)
2022 {
2023 int i = 0;
2024 int err;
2025
2026 if (!mlx4_is_mfunc(dev->dev))
2027 return 0;
2028
2029 dev->sriov.is_going_down = 0;
2030 spin_lock_init(&dev->sriov.going_down_lock);
2031 mlx4_ib_cm_paravirt_init(dev);
2032
2033 mlx4_ib_warn(&dev->ib_dev, "multi-function enabled\n");
2034
2035 if (mlx4_is_slave(dev->dev)) {
2036 mlx4_ib_warn(&dev->ib_dev, "operating in qp1 tunnel mode\n");
2037 return 0;
2038 }
2039
2040 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2041 if (i == mlx4_master_func_num(dev->dev))
2042 mlx4_put_slave_node_guid(dev->dev, i, dev->ib_dev.node_guid);
2043 else
2044 mlx4_put_slave_node_guid(dev->dev, i, mlx4_ib_gen_node_guid());
2045 }
2046
2047 err = mlx4_ib_init_alias_guid_service(dev);
2048 if (err) {
2049 mlx4_ib_warn(&dev->ib_dev, "Failed init alias guid process.\n");
2050 goto paravirt_err;
2051 }
2052 err = mlx4_ib_device_register_sysfs(dev);
2053 if (err) {
2054 mlx4_ib_warn(&dev->ib_dev, "Failed to register sysfs\n");
2055 goto sysfs_err;
2056 }
2057
2058 mlx4_ib_warn(&dev->ib_dev, "initializing demux service for %d qp1 clients\n",
2059 dev->dev->caps.sqp_demux);
2060 for (i = 0; i < dev->num_ports; i++) {
2061 union ib_gid gid;
2062 err = __mlx4_ib_query_gid(&dev->ib_dev, i + 1, 0, &gid, 1);
2063 if (err)
2064 goto demux_err;
2065 dev->sriov.demux[i].guid_cache[0] = gid.global.interface_id;
2066 err = alloc_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1,
2067 &dev->sriov.sqps[i]);
2068 if (err)
2069 goto demux_err;
2070 err = mlx4_ib_alloc_demux_ctx(dev, &dev->sriov.demux[i], i + 1);
2071 if (err)
2072 goto free_pv;
2073 }
2074 mlx4_ib_master_tunnels(dev, 1);
2075 return 0;
2076
2077 free_pv:
2078 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1);
2079 demux_err:
2080 while (--i >= 0) {
2081 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1);
2082 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]);
2083 }
2084 mlx4_ib_device_unregister_sysfs(dev);
2085
2086 sysfs_err:
2087 mlx4_ib_destroy_alias_guid_service(dev);
2088
2089 paravirt_err:
2090 mlx4_ib_cm_paravirt_clean(dev, -1);
2091
2092 return err;
2093 }
2094
2095 void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev)
2096 {
2097 int i;
2098 unsigned long flags;
2099
2100 if (!mlx4_is_mfunc(dev->dev))
2101 return;
2102
2103 spin_lock_irqsave(&dev->sriov.going_down_lock, flags);
2104 dev->sriov.is_going_down = 1;
2105 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags);
2106 if (mlx4_is_master(dev->dev)) {
2107 for (i = 0; i < dev->num_ports; i++) {
2108 flush_workqueue(dev->sriov.demux[i].ud_wq);
2109 mlx4_ib_free_sqp_ctx(dev->sriov.sqps[i]);
2110 kfree(dev->sriov.sqps[i]);
2111 dev->sriov.sqps[i] = NULL;
2112 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]);
2113 }
2114
2115 mlx4_ib_cm_paravirt_clean(dev, -1);
2116 mlx4_ib_destroy_alias_guid_service(dev);
2117 mlx4_ib_device_unregister_sysfs(dev);
2118 }
2119 }
Linux kernel - Deliverables
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