2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/log2.h>
36 #include <rdma/ib_cache.h>
37 #include <rdma/ib_pack.h>
39 #include <linux/mlx4/qp.h>
45 MLX4_IB_ACK_REQ_FREQ
= 8,
49 MLX4_IB_DEFAULT_SCHED_QUEUE
= 0x83,
50 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE
= 0x3f
55 * Largest possible UD header: send with GRH and immediate data.
57 MLX4_IB_UD_HEADER_SIZE
= 72
65 struct ib_ud_header ud_header
;
66 u8 header_buf
[MLX4_IB_UD_HEADER_SIZE
];
70 MLX4_IB_MIN_SQ_STRIDE
= 6
73 static const __be32 mlx4_ib_opcode
[] = {
74 [IB_WR_SEND
] = __constant_cpu_to_be32(MLX4_OPCODE_SEND
),
75 [IB_WR_LSO
] = __constant_cpu_to_be32(MLX4_OPCODE_LSO
),
76 [IB_WR_SEND_WITH_IMM
] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_IMM
),
77 [IB_WR_RDMA_WRITE
] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE
),
78 [IB_WR_RDMA_WRITE_WITH_IMM
] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM
),
79 [IB_WR_RDMA_READ
] = __constant_cpu_to_be32(MLX4_OPCODE_RDMA_READ
),
80 [IB_WR_ATOMIC_CMP_AND_SWP
] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_CS
),
81 [IB_WR_ATOMIC_FETCH_AND_ADD
] = __constant_cpu_to_be32(MLX4_OPCODE_ATOMIC_FA
),
82 [IB_WR_SEND_WITH_INV
] = __constant_cpu_to_be32(MLX4_OPCODE_SEND_INVAL
),
83 [IB_WR_LOCAL_INV
] = __constant_cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL
),
84 [IB_WR_FAST_REG_MR
] = __constant_cpu_to_be32(MLX4_OPCODE_FMR
),
87 static struct mlx4_ib_sqp
*to_msqp(struct mlx4_ib_qp
*mqp
)
89 return container_of(mqp
, struct mlx4_ib_sqp
, qp
);
92 static int is_sqp(struct mlx4_ib_dev
*dev
, struct mlx4_ib_qp
*qp
)
94 return qp
->mqp
.qpn
>= dev
->dev
->caps
.sqp_start
&&
95 qp
->mqp
.qpn
<= dev
->dev
->caps
.sqp_start
+ 3;
98 static int is_qp0(struct mlx4_ib_dev
*dev
, struct mlx4_ib_qp
*qp
)
100 return qp
->mqp
.qpn
>= dev
->dev
->caps
.sqp_start
&&
101 qp
->mqp
.qpn
<= dev
->dev
->caps
.sqp_start
+ 1;
104 static void *get_wqe(struct mlx4_ib_qp
*qp
, int offset
)
106 return mlx4_buf_offset(&qp
->buf
, offset
);
109 static void *get_recv_wqe(struct mlx4_ib_qp
*qp
, int n
)
111 return get_wqe(qp
, qp
->rq
.offset
+ (n
<< qp
->rq
.wqe_shift
));
114 static void *get_send_wqe(struct mlx4_ib_qp
*qp
, int n
)
116 return get_wqe(qp
, qp
->sq
.offset
+ (n
<< qp
->sq
.wqe_shift
));
120 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
121 * first four bytes of every 64 byte chunk with
122 * 0x7FFFFFF | (invalid_ownership_value << 31).
124 * When the max work request size is less than or equal to the WQE
125 * basic block size, as an optimization, we can stamp all WQEs with
126 * 0xffffffff, and skip the very first chunk of each WQE.
128 static void stamp_send_wqe(struct mlx4_ib_qp
*qp
, int n
, int size
)
136 struct mlx4_wqe_ctrl_seg
*ctrl
;
138 if (qp
->sq_max_wqes_per_wr
> 1) {
139 s
= roundup(size
, 1U << qp
->sq
.wqe_shift
);
140 for (i
= 0; i
< s
; i
+= 64) {
141 ind
= (i
>> qp
->sq
.wqe_shift
) + n
;
142 stamp
= ind
& qp
->sq
.wqe_cnt
? cpu_to_be32(0x7fffffff) :
143 cpu_to_be32(0xffffffff);
144 buf
= get_send_wqe(qp
, ind
& (qp
->sq
.wqe_cnt
- 1));
145 wqe
= buf
+ (i
& ((1 << qp
->sq
.wqe_shift
) - 1));
149 ctrl
= buf
= get_send_wqe(qp
, n
& (qp
->sq
.wqe_cnt
- 1));
150 s
= (ctrl
->fence_size
& 0x3f) << 4;
151 for (i
= 64; i
< s
; i
+= 64) {
153 *wqe
= cpu_to_be32(0xffffffff);
158 static void post_nop_wqe(struct mlx4_ib_qp
*qp
, int n
, int size
)
160 struct mlx4_wqe_ctrl_seg
*ctrl
;
161 struct mlx4_wqe_inline_seg
*inl
;
165 ctrl
= wqe
= get_send_wqe(qp
, n
& (qp
->sq
.wqe_cnt
- 1));
166 s
= sizeof(struct mlx4_wqe_ctrl_seg
);
168 if (qp
->ibqp
.qp_type
== IB_QPT_UD
) {
169 struct mlx4_wqe_datagram_seg
*dgram
= wqe
+ sizeof *ctrl
;
170 struct mlx4_av
*av
= (struct mlx4_av
*)dgram
->av
;
171 memset(dgram
, 0, sizeof *dgram
);
172 av
->port_pd
= cpu_to_be32((qp
->port
<< 24) | to_mpd(qp
->ibqp
.pd
)->pdn
);
173 s
+= sizeof(struct mlx4_wqe_datagram_seg
);
176 /* Pad the remainder of the WQE with an inline data segment. */
179 inl
->byte_count
= cpu_to_be32(1 << 31 | (size
- s
- sizeof *inl
));
181 ctrl
->srcrb_flags
= 0;
182 ctrl
->fence_size
= size
/ 16;
184 * Make sure descriptor is fully written before setting ownership bit
185 * (because HW can start executing as soon as we do).
189 ctrl
->owner_opcode
= cpu_to_be32(MLX4_OPCODE_NOP
| MLX4_WQE_CTRL_NEC
) |
190 (n
& qp
->sq
.wqe_cnt
? cpu_to_be32(1 << 31) : 0);
192 stamp_send_wqe(qp
, n
+ qp
->sq_spare_wqes
, size
);
195 /* Post NOP WQE to prevent wrap-around in the middle of WR */
196 static inline unsigned pad_wraparound(struct mlx4_ib_qp
*qp
, int ind
)
198 unsigned s
= qp
->sq
.wqe_cnt
- (ind
& (qp
->sq
.wqe_cnt
- 1));
199 if (unlikely(s
< qp
->sq_max_wqes_per_wr
)) {
200 post_nop_wqe(qp
, ind
, s
<< qp
->sq
.wqe_shift
);
206 static void mlx4_ib_qp_event(struct mlx4_qp
*qp
, enum mlx4_event type
)
208 struct ib_event event
;
209 struct ib_qp
*ibqp
= &to_mibqp(qp
)->ibqp
;
211 if (type
== MLX4_EVENT_TYPE_PATH_MIG
)
212 to_mibqp(qp
)->port
= to_mibqp(qp
)->alt_port
;
214 if (ibqp
->event_handler
) {
215 event
.device
= ibqp
->device
;
216 event
.element
.qp
= ibqp
;
218 case MLX4_EVENT_TYPE_PATH_MIG
:
219 event
.event
= IB_EVENT_PATH_MIG
;
221 case MLX4_EVENT_TYPE_COMM_EST
:
222 event
.event
= IB_EVENT_COMM_EST
;
224 case MLX4_EVENT_TYPE_SQ_DRAINED
:
225 event
.event
= IB_EVENT_SQ_DRAINED
;
227 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
:
228 event
.event
= IB_EVENT_QP_LAST_WQE_REACHED
;
230 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR
:
231 event
.event
= IB_EVENT_QP_FATAL
;
233 case MLX4_EVENT_TYPE_PATH_MIG_FAILED
:
234 event
.event
= IB_EVENT_PATH_MIG_ERR
;
236 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
:
237 event
.event
= IB_EVENT_QP_REQ_ERR
;
239 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
:
240 event
.event
= IB_EVENT_QP_ACCESS_ERR
;
243 printk(KERN_WARNING
"mlx4_ib: Unexpected event type %d "
244 "on QP %06x\n", type
, qp
->qpn
);
248 ibqp
->event_handler(&event
, ibqp
->qp_context
);
252 static int send_wqe_overhead(enum ib_qp_type type
, u32 flags
)
255 * UD WQEs must have a datagram segment.
256 * RC and UC WQEs might have a remote address segment.
257 * MLX WQEs need two extra inline data segments (for the UD
258 * header and space for the ICRC).
262 return sizeof (struct mlx4_wqe_ctrl_seg
) +
263 sizeof (struct mlx4_wqe_datagram_seg
) +
264 ((flags
& MLX4_IB_QP_LSO
) ? 64 : 0);
266 return sizeof (struct mlx4_wqe_ctrl_seg
) +
267 sizeof (struct mlx4_wqe_raddr_seg
);
269 return sizeof (struct mlx4_wqe_ctrl_seg
) +
270 sizeof (struct mlx4_wqe_atomic_seg
) +
271 sizeof (struct mlx4_wqe_raddr_seg
);
274 return sizeof (struct mlx4_wqe_ctrl_seg
) +
275 ALIGN(MLX4_IB_UD_HEADER_SIZE
+
276 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE
,
278 sizeof (struct mlx4_wqe_inline_seg
),
279 sizeof (struct mlx4_wqe_data_seg
)) +
281 sizeof (struct mlx4_wqe_inline_seg
),
282 sizeof (struct mlx4_wqe_data_seg
));
284 return sizeof (struct mlx4_wqe_ctrl_seg
);
288 static int set_rq_size(struct mlx4_ib_dev
*dev
, struct ib_qp_cap
*cap
,
289 int is_user
, int has_srq
, struct mlx4_ib_qp
*qp
)
291 /* Sanity check RQ size before proceeding */
292 if (cap
->max_recv_wr
> dev
->dev
->caps
.max_wqes
||
293 cap
->max_recv_sge
> dev
->dev
->caps
.max_rq_sg
)
297 /* QPs attached to an SRQ should have no RQ */
298 if (cap
->max_recv_wr
)
301 qp
->rq
.wqe_cnt
= qp
->rq
.max_gs
= 0;
303 /* HW requires >= 1 RQ entry with >= 1 gather entry */
304 if (is_user
&& (!cap
->max_recv_wr
|| !cap
->max_recv_sge
))
307 qp
->rq
.wqe_cnt
= roundup_pow_of_two(max(1U, cap
->max_recv_wr
));
308 qp
->rq
.max_gs
= roundup_pow_of_two(max(1U, cap
->max_recv_sge
));
309 qp
->rq
.wqe_shift
= ilog2(qp
->rq
.max_gs
* sizeof (struct mlx4_wqe_data_seg
));
312 cap
->max_recv_wr
= qp
->rq
.max_post
= qp
->rq
.wqe_cnt
;
313 cap
->max_recv_sge
= qp
->rq
.max_gs
;
318 static int set_kernel_sq_size(struct mlx4_ib_dev
*dev
, struct ib_qp_cap
*cap
,
319 enum ib_qp_type type
, struct mlx4_ib_qp
*qp
)
323 /* Sanity check SQ size before proceeding */
324 if (cap
->max_send_wr
> dev
->dev
->caps
.max_wqes
||
325 cap
->max_send_sge
> dev
->dev
->caps
.max_sq_sg
||
326 cap
->max_inline_data
+ send_wqe_overhead(type
, qp
->flags
) +
327 sizeof (struct mlx4_wqe_inline_seg
) > dev
->dev
->caps
.max_sq_desc_sz
)
331 * For MLX transport we need 2 extra S/G entries:
332 * one for the header and one for the checksum at the end
334 if ((type
== IB_QPT_SMI
|| type
== IB_QPT_GSI
) &&
335 cap
->max_send_sge
+ 2 > dev
->dev
->caps
.max_sq_sg
)
338 s
= max(cap
->max_send_sge
* sizeof (struct mlx4_wqe_data_seg
),
339 cap
->max_inline_data
+ sizeof (struct mlx4_wqe_inline_seg
)) +
340 send_wqe_overhead(type
, qp
->flags
);
342 if (s
> dev
->dev
->caps
.max_sq_desc_sz
)
346 * Hermon supports shrinking WQEs, such that a single work
347 * request can include multiple units of 1 << wqe_shift. This
348 * way, work requests can differ in size, and do not have to
349 * be a power of 2 in size, saving memory and speeding up send
350 * WR posting. Unfortunately, if we do this then the
351 * wqe_index field in CQEs can't be used to look up the WR ID
352 * anymore, so we do this only if selective signaling is off.
354 * Further, on 32-bit platforms, we can't use vmap() to make
355 * the QP buffer virtually contigious. Thus we have to use
356 * constant-sized WRs to make sure a WR is always fully within
357 * a single page-sized chunk.
359 * Finally, we use NOP work requests to pad the end of the
360 * work queue, to avoid wrap-around in the middle of WR. We
361 * set NEC bit to avoid getting completions with error for
362 * these NOP WRs, but since NEC is only supported starting
363 * with firmware 2.2.232, we use constant-sized WRs for older
366 * And, since MLX QPs only support SEND, we use constant-sized
369 * We look for the smallest value of wqe_shift such that the
370 * resulting number of wqes does not exceed device
373 * We set WQE size to at least 64 bytes, this way stamping
374 * invalidates each WQE.
376 if (dev
->dev
->caps
.fw_ver
>= MLX4_FW_VER_WQE_CTRL_NEC
&&
377 qp
->sq_signal_bits
&& BITS_PER_LONG
== 64 &&
378 type
!= IB_QPT_SMI
&& type
!= IB_QPT_GSI
)
379 qp
->sq
.wqe_shift
= ilog2(64);
381 qp
->sq
.wqe_shift
= ilog2(roundup_pow_of_two(s
));
384 qp
->sq_max_wqes_per_wr
= DIV_ROUND_UP(s
, 1U << qp
->sq
.wqe_shift
);
387 * We need to leave 2 KB + 1 WR of headroom in the SQ to
388 * allow HW to prefetch.
390 qp
->sq_spare_wqes
= (2048 >> qp
->sq
.wqe_shift
) + qp
->sq_max_wqes_per_wr
;
391 qp
->sq
.wqe_cnt
= roundup_pow_of_two(cap
->max_send_wr
*
392 qp
->sq_max_wqes_per_wr
+
395 if (qp
->sq
.wqe_cnt
<= dev
->dev
->caps
.max_wqes
)
398 if (qp
->sq_max_wqes_per_wr
<= 1)
404 qp
->sq
.max_gs
= (min(dev
->dev
->caps
.max_sq_desc_sz
,
405 (qp
->sq_max_wqes_per_wr
<< qp
->sq
.wqe_shift
)) -
406 send_wqe_overhead(type
, qp
->flags
)) /
407 sizeof (struct mlx4_wqe_data_seg
);
409 qp
->buf_size
= (qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
) +
410 (qp
->sq
.wqe_cnt
<< qp
->sq
.wqe_shift
);
411 if (qp
->rq
.wqe_shift
> qp
->sq
.wqe_shift
) {
413 qp
->sq
.offset
= qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
;
415 qp
->rq
.offset
= qp
->sq
.wqe_cnt
<< qp
->sq
.wqe_shift
;
419 cap
->max_send_wr
= qp
->sq
.max_post
=
420 (qp
->sq
.wqe_cnt
- qp
->sq_spare_wqes
) / qp
->sq_max_wqes_per_wr
;
421 cap
->max_send_sge
= min(qp
->sq
.max_gs
,
422 min(dev
->dev
->caps
.max_sq_sg
,
423 dev
->dev
->caps
.max_rq_sg
));
424 /* We don't support inline sends for kernel QPs (yet) */
425 cap
->max_inline_data
= 0;
430 static int set_user_sq_size(struct mlx4_ib_dev
*dev
,
431 struct mlx4_ib_qp
*qp
,
432 struct mlx4_ib_create_qp
*ucmd
)
434 /* Sanity check SQ size before proceeding */
435 if ((1 << ucmd
->log_sq_bb_count
) > dev
->dev
->caps
.max_wqes
||
436 ucmd
->log_sq_stride
>
437 ilog2(roundup_pow_of_two(dev
->dev
->caps
.max_sq_desc_sz
)) ||
438 ucmd
->log_sq_stride
< MLX4_IB_MIN_SQ_STRIDE
)
441 qp
->sq
.wqe_cnt
= 1 << ucmd
->log_sq_bb_count
;
442 qp
->sq
.wqe_shift
= ucmd
->log_sq_stride
;
444 qp
->buf_size
= (qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
) +
445 (qp
->sq
.wqe_cnt
<< qp
->sq
.wqe_shift
);
450 static int create_qp_common(struct mlx4_ib_dev
*dev
, struct ib_pd
*pd
,
451 struct ib_qp_init_attr
*init_attr
,
452 struct ib_udata
*udata
, int sqpn
, struct mlx4_ib_qp
*qp
)
456 mutex_init(&qp
->mutex
);
457 spin_lock_init(&qp
->sq
.lock
);
458 spin_lock_init(&qp
->rq
.lock
);
460 qp
->state
= IB_QPS_RESET
;
461 if (init_attr
->sq_sig_type
== IB_SIGNAL_ALL_WR
)
462 qp
->sq_signal_bits
= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE
);
464 err
= set_rq_size(dev
, &init_attr
->cap
, !!pd
->uobject
, !!init_attr
->srq
, qp
);
469 struct mlx4_ib_create_qp ucmd
;
471 if (ib_copy_from_udata(&ucmd
, udata
, sizeof ucmd
)) {
476 qp
->sq_no_prefetch
= ucmd
.sq_no_prefetch
;
478 err
= set_user_sq_size(dev
, qp
, &ucmd
);
482 qp
->umem
= ib_umem_get(pd
->uobject
->context
, ucmd
.buf_addr
,
484 if (IS_ERR(qp
->umem
)) {
485 err
= PTR_ERR(qp
->umem
);
489 err
= mlx4_mtt_init(dev
->dev
, ib_umem_page_count(qp
->umem
),
490 ilog2(qp
->umem
->page_size
), &qp
->mtt
);
494 err
= mlx4_ib_umem_write_mtt(dev
, &qp
->mtt
, qp
->umem
);
498 if (!init_attr
->srq
) {
499 err
= mlx4_ib_db_map_user(to_mucontext(pd
->uobject
->context
),
500 ucmd
.db_addr
, &qp
->db
);
505 qp
->sq_no_prefetch
= 0;
507 if (init_attr
->create_flags
& IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
)
508 qp
->flags
|= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK
;
510 if (init_attr
->create_flags
& IB_QP_CREATE_IPOIB_UD_LSO
)
511 qp
->flags
|= MLX4_IB_QP_LSO
;
513 err
= set_kernel_sq_size(dev
, &init_attr
->cap
, init_attr
->qp_type
, qp
);
517 if (!init_attr
->srq
) {
518 err
= mlx4_db_alloc(dev
->dev
, &qp
->db
, 0);
525 if (mlx4_buf_alloc(dev
->dev
, qp
->buf_size
, PAGE_SIZE
* 2, &qp
->buf
)) {
530 err
= mlx4_mtt_init(dev
->dev
, qp
->buf
.npages
, qp
->buf
.page_shift
,
535 err
= mlx4_buf_write_mtt(dev
->dev
, &qp
->mtt
, &qp
->buf
);
539 qp
->sq
.wrid
= kmalloc(qp
->sq
.wqe_cnt
* sizeof (u64
), GFP_KERNEL
);
540 qp
->rq
.wrid
= kmalloc(qp
->rq
.wqe_cnt
* sizeof (u64
), GFP_KERNEL
);
542 if (!qp
->sq
.wrid
|| !qp
->rq
.wrid
) {
548 err
= mlx4_qp_alloc(dev
->dev
, sqpn
, &qp
->mqp
);
553 * Hardware wants QPN written in big-endian order (after
554 * shifting) for send doorbell. Precompute this value to save
555 * a little bit when posting sends.
557 qp
->doorbell_qpn
= swab32(qp
->mqp
.qpn
<< 8);
559 qp
->mqp
.event
= mlx4_ib_qp_event
;
566 mlx4_ib_db_unmap_user(to_mucontext(pd
->uobject
->context
),
574 mlx4_mtt_cleanup(dev
->dev
, &qp
->mtt
);
578 ib_umem_release(qp
->umem
);
580 mlx4_buf_free(dev
->dev
, qp
->buf_size
, &qp
->buf
);
583 if (!pd
->uobject
&& !init_attr
->srq
)
584 mlx4_db_free(dev
->dev
, &qp
->db
);
590 static enum mlx4_qp_state
to_mlx4_state(enum ib_qp_state state
)
593 case IB_QPS_RESET
: return MLX4_QP_STATE_RST
;
594 case IB_QPS_INIT
: return MLX4_QP_STATE_INIT
;
595 case IB_QPS_RTR
: return MLX4_QP_STATE_RTR
;
596 case IB_QPS_RTS
: return MLX4_QP_STATE_RTS
;
597 case IB_QPS_SQD
: return MLX4_QP_STATE_SQD
;
598 case IB_QPS_SQE
: return MLX4_QP_STATE_SQER
;
599 case IB_QPS_ERR
: return MLX4_QP_STATE_ERR
;
604 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq
*send_cq
, struct mlx4_ib_cq
*recv_cq
)
606 if (send_cq
== recv_cq
)
607 spin_lock_irq(&send_cq
->lock
);
608 else if (send_cq
->mcq
.cqn
< recv_cq
->mcq
.cqn
) {
609 spin_lock_irq(&send_cq
->lock
);
610 spin_lock_nested(&recv_cq
->lock
, SINGLE_DEPTH_NESTING
);
612 spin_lock_irq(&recv_cq
->lock
);
613 spin_lock_nested(&send_cq
->lock
, SINGLE_DEPTH_NESTING
);
617 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq
*send_cq
, struct mlx4_ib_cq
*recv_cq
)
619 if (send_cq
== recv_cq
)
620 spin_unlock_irq(&send_cq
->lock
);
621 else if (send_cq
->mcq
.cqn
< recv_cq
->mcq
.cqn
) {
622 spin_unlock(&recv_cq
->lock
);
623 spin_unlock_irq(&send_cq
->lock
);
625 spin_unlock(&send_cq
->lock
);
626 spin_unlock_irq(&recv_cq
->lock
);
630 static void destroy_qp_common(struct mlx4_ib_dev
*dev
, struct mlx4_ib_qp
*qp
,
633 struct mlx4_ib_cq
*send_cq
, *recv_cq
;
635 if (qp
->state
!= IB_QPS_RESET
)
636 if (mlx4_qp_modify(dev
->dev
, NULL
, to_mlx4_state(qp
->state
),
637 MLX4_QP_STATE_RST
, NULL
, 0, 0, &qp
->mqp
))
638 printk(KERN_WARNING
"mlx4_ib: modify QP %06x to RESET failed.\n",
641 send_cq
= to_mcq(qp
->ibqp
.send_cq
);
642 recv_cq
= to_mcq(qp
->ibqp
.recv_cq
);
644 mlx4_ib_lock_cqs(send_cq
, recv_cq
);
647 __mlx4_ib_cq_clean(recv_cq
, qp
->mqp
.qpn
,
648 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
): NULL
);
649 if (send_cq
!= recv_cq
)
650 __mlx4_ib_cq_clean(send_cq
, qp
->mqp
.qpn
, NULL
);
653 mlx4_qp_remove(dev
->dev
, &qp
->mqp
);
655 mlx4_ib_unlock_cqs(send_cq
, recv_cq
);
657 mlx4_qp_free(dev
->dev
, &qp
->mqp
);
658 mlx4_mtt_cleanup(dev
->dev
, &qp
->mtt
);
662 mlx4_ib_db_unmap_user(to_mucontext(qp
->ibqp
.uobject
->context
),
664 ib_umem_release(qp
->umem
);
668 mlx4_buf_free(dev
->dev
, qp
->buf_size
, &qp
->buf
);
670 mlx4_db_free(dev
->dev
, &qp
->db
);
674 struct ib_qp
*mlx4_ib_create_qp(struct ib_pd
*pd
,
675 struct ib_qp_init_attr
*init_attr
,
676 struct ib_udata
*udata
)
678 struct mlx4_ib_dev
*dev
= to_mdev(pd
->device
);
679 struct mlx4_ib_sqp
*sqp
;
680 struct mlx4_ib_qp
*qp
;
684 * We only support LSO and multicast loopback blocking, and
685 * only for kernel UD QPs.
687 if (init_attr
->create_flags
& ~(IB_QP_CREATE_IPOIB_UD_LSO
|
688 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
))
689 return ERR_PTR(-EINVAL
);
691 if (init_attr
->create_flags
&&
692 (pd
->uobject
|| init_attr
->qp_type
!= IB_QPT_UD
))
693 return ERR_PTR(-EINVAL
);
695 switch (init_attr
->qp_type
) {
700 qp
= kzalloc(sizeof *qp
, GFP_KERNEL
);
702 return ERR_PTR(-ENOMEM
);
704 err
= create_qp_common(dev
, pd
, init_attr
, udata
, 0, qp
);
710 qp
->ibqp
.qp_num
= qp
->mqp
.qpn
;
717 /* Userspace is not allowed to create special QPs: */
719 return ERR_PTR(-EINVAL
);
721 sqp
= kzalloc(sizeof *sqp
, GFP_KERNEL
);
723 return ERR_PTR(-ENOMEM
);
727 err
= create_qp_common(dev
, pd
, init_attr
, udata
,
728 dev
->dev
->caps
.sqp_start
+
729 (init_attr
->qp_type
== IB_QPT_SMI
? 0 : 2) +
730 init_attr
->port_num
- 1,
737 qp
->port
= init_attr
->port_num
;
738 qp
->ibqp
.qp_num
= init_attr
->qp_type
== IB_QPT_SMI
? 0 : 1;
743 /* Don't support raw QPs */
744 return ERR_PTR(-EINVAL
);
750 int mlx4_ib_destroy_qp(struct ib_qp
*qp
)
752 struct mlx4_ib_dev
*dev
= to_mdev(qp
->device
);
753 struct mlx4_ib_qp
*mqp
= to_mqp(qp
);
755 if (is_qp0(dev
, mqp
))
756 mlx4_CLOSE_PORT(dev
->dev
, mqp
->port
);
758 destroy_qp_common(dev
, mqp
, !!qp
->pd
->uobject
);
760 if (is_sqp(dev
, mqp
))
768 static int to_mlx4_st(enum ib_qp_type type
)
771 case IB_QPT_RC
: return MLX4_QP_ST_RC
;
772 case IB_QPT_UC
: return MLX4_QP_ST_UC
;
773 case IB_QPT_UD
: return MLX4_QP_ST_UD
;
775 case IB_QPT_GSI
: return MLX4_QP_ST_MLX
;
780 static __be32
to_mlx4_access_flags(struct mlx4_ib_qp
*qp
, const struct ib_qp_attr
*attr
,
785 u32 hw_access_flags
= 0;
787 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
788 dest_rd_atomic
= attr
->max_dest_rd_atomic
;
790 dest_rd_atomic
= qp
->resp_depth
;
792 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
793 access_flags
= attr
->qp_access_flags
;
795 access_flags
= qp
->atomic_rd_en
;
798 access_flags
&= IB_ACCESS_REMOTE_WRITE
;
800 if (access_flags
& IB_ACCESS_REMOTE_READ
)
801 hw_access_flags
|= MLX4_QP_BIT_RRE
;
802 if (access_flags
& IB_ACCESS_REMOTE_ATOMIC
)
803 hw_access_flags
|= MLX4_QP_BIT_RAE
;
804 if (access_flags
& IB_ACCESS_REMOTE_WRITE
)
805 hw_access_flags
|= MLX4_QP_BIT_RWE
;
807 return cpu_to_be32(hw_access_flags
);
810 static void store_sqp_attrs(struct mlx4_ib_sqp
*sqp
, const struct ib_qp_attr
*attr
,
813 if (attr_mask
& IB_QP_PKEY_INDEX
)
814 sqp
->pkey_index
= attr
->pkey_index
;
815 if (attr_mask
& IB_QP_QKEY
)
816 sqp
->qkey
= attr
->qkey
;
817 if (attr_mask
& IB_QP_SQ_PSN
)
818 sqp
->send_psn
= attr
->sq_psn
;
821 static void mlx4_set_sched(struct mlx4_qp_path
*path
, u8 port
)
823 path
->sched_queue
= (path
->sched_queue
& 0xbf) | ((port
- 1) << 6);
826 static int mlx4_set_path(struct mlx4_ib_dev
*dev
, const struct ib_ah_attr
*ah
,
827 struct mlx4_qp_path
*path
, u8 port
)
829 path
->grh_mylmc
= ah
->src_path_bits
& 0x7f;
830 path
->rlid
= cpu_to_be16(ah
->dlid
);
831 if (ah
->static_rate
) {
832 path
->static_rate
= ah
->static_rate
+ MLX4_STAT_RATE_OFFSET
;
833 while (path
->static_rate
> IB_RATE_2_5_GBPS
+ MLX4_STAT_RATE_OFFSET
&&
834 !(1 << path
->static_rate
& dev
->dev
->caps
.stat_rate_support
))
837 path
->static_rate
= 0;
838 path
->counter_index
= 0xff;
840 if (ah
->ah_flags
& IB_AH_GRH
) {
841 if (ah
->grh
.sgid_index
>= dev
->dev
->caps
.gid_table_len
[port
]) {
842 printk(KERN_ERR
"sgid_index (%u) too large. max is %d\n",
843 ah
->grh
.sgid_index
, dev
->dev
->caps
.gid_table_len
[port
] - 1);
847 path
->grh_mylmc
|= 1 << 7;
848 path
->mgid_index
= ah
->grh
.sgid_index
;
849 path
->hop_limit
= ah
->grh
.hop_limit
;
850 path
->tclass_flowlabel
=
851 cpu_to_be32((ah
->grh
.traffic_class
<< 20) |
852 (ah
->grh
.flow_label
));
853 memcpy(path
->rgid
, ah
->grh
.dgid
.raw
, 16);
856 path
->sched_queue
= MLX4_IB_DEFAULT_SCHED_QUEUE
|
857 ((port
- 1) << 6) | ((ah
->sl
& 0xf) << 2);
862 static int __mlx4_ib_modify_qp(struct ib_qp
*ibqp
,
863 const struct ib_qp_attr
*attr
, int attr_mask
,
864 enum ib_qp_state cur_state
, enum ib_qp_state new_state
)
866 struct mlx4_ib_dev
*dev
= to_mdev(ibqp
->device
);
867 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
868 struct mlx4_qp_context
*context
;
869 enum mlx4_qp_optpar optpar
= 0;
873 context
= kzalloc(sizeof *context
, GFP_KERNEL
);
877 context
->flags
= cpu_to_be32((to_mlx4_state(new_state
) << 28) |
878 (to_mlx4_st(ibqp
->qp_type
) << 16));
879 context
->flags
|= cpu_to_be32(1 << 8); /* DE? */
881 if (!(attr_mask
& IB_QP_PATH_MIG_STATE
))
882 context
->flags
|= cpu_to_be32(MLX4_QP_PM_MIGRATED
<< 11);
884 optpar
|= MLX4_QP_OPTPAR_PM_STATE
;
885 switch (attr
->path_mig_state
) {
886 case IB_MIG_MIGRATED
:
887 context
->flags
|= cpu_to_be32(MLX4_QP_PM_MIGRATED
<< 11);
890 context
->flags
|= cpu_to_be32(MLX4_QP_PM_REARM
<< 11);
893 context
->flags
|= cpu_to_be32(MLX4_QP_PM_ARMED
<< 11);
898 if (ibqp
->qp_type
== IB_QPT_GSI
|| ibqp
->qp_type
== IB_QPT_SMI
)
899 context
->mtu_msgmax
= (IB_MTU_4096
<< 5) | 11;
900 else if (ibqp
->qp_type
== IB_QPT_UD
) {
901 if (qp
->flags
& MLX4_IB_QP_LSO
)
902 context
->mtu_msgmax
= (IB_MTU_4096
<< 5) |
903 ilog2(dev
->dev
->caps
.max_gso_sz
);
905 context
->mtu_msgmax
= (IB_MTU_4096
<< 5) | 11;
906 } else if (attr_mask
& IB_QP_PATH_MTU
) {
907 if (attr
->path_mtu
< IB_MTU_256
|| attr
->path_mtu
> IB_MTU_4096
) {
908 printk(KERN_ERR
"path MTU (%u) is invalid\n",
912 context
->mtu_msgmax
= (attr
->path_mtu
<< 5) |
913 ilog2(dev
->dev
->caps
.max_msg_sz
);
917 context
->rq_size_stride
= ilog2(qp
->rq
.wqe_cnt
) << 3;
918 context
->rq_size_stride
|= qp
->rq
.wqe_shift
- 4;
921 context
->sq_size_stride
= ilog2(qp
->sq
.wqe_cnt
) << 3;
922 context
->sq_size_stride
|= qp
->sq
.wqe_shift
- 4;
924 if (cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
925 context
->sq_size_stride
|= !!qp
->sq_no_prefetch
<< 7;
927 if (qp
->ibqp
.uobject
)
928 context
->usr_page
= cpu_to_be32(to_mucontext(ibqp
->uobject
->context
)->uar
.index
);
930 context
->usr_page
= cpu_to_be32(dev
->priv_uar
.index
);
932 if (attr_mask
& IB_QP_DEST_QPN
)
933 context
->remote_qpn
= cpu_to_be32(attr
->dest_qp_num
);
935 if (attr_mask
& IB_QP_PORT
) {
936 if (cur_state
== IB_QPS_SQD
&& new_state
== IB_QPS_SQD
&&
937 !(attr_mask
& IB_QP_AV
)) {
938 mlx4_set_sched(&context
->pri_path
, attr
->port_num
);
939 optpar
|= MLX4_QP_OPTPAR_SCHED_QUEUE
;
943 if (attr_mask
& IB_QP_PKEY_INDEX
) {
944 context
->pri_path
.pkey_index
= attr
->pkey_index
;
945 optpar
|= MLX4_QP_OPTPAR_PKEY_INDEX
;
948 if (attr_mask
& IB_QP_AV
) {
949 if (mlx4_set_path(dev
, &attr
->ah_attr
, &context
->pri_path
,
950 attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
))
953 optpar
|= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH
|
954 MLX4_QP_OPTPAR_SCHED_QUEUE
);
957 if (attr_mask
& IB_QP_TIMEOUT
) {
958 context
->pri_path
.ackto
= attr
->timeout
<< 3;
959 optpar
|= MLX4_QP_OPTPAR_ACK_TIMEOUT
;
962 if (attr_mask
& IB_QP_ALT_PATH
) {
963 if (attr
->alt_port_num
== 0 ||
964 attr
->alt_port_num
> dev
->dev
->caps
.num_ports
)
967 if (attr
->alt_pkey_index
>=
968 dev
->dev
->caps
.pkey_table_len
[attr
->alt_port_num
])
971 if (mlx4_set_path(dev
, &attr
->alt_ah_attr
, &context
->alt_path
,
975 context
->alt_path
.pkey_index
= attr
->alt_pkey_index
;
976 context
->alt_path
.ackto
= attr
->alt_timeout
<< 3;
977 optpar
|= MLX4_QP_OPTPAR_ALT_ADDR_PATH
;
980 context
->pd
= cpu_to_be32(to_mpd(ibqp
->pd
)->pdn
);
981 context
->params1
= cpu_to_be32(MLX4_IB_ACK_REQ_FREQ
<< 28);
983 /* Set "fast registration enabled" for all kernel QPs */
984 if (!qp
->ibqp
.uobject
)
985 context
->params1
|= cpu_to_be32(1 << 11);
987 if (attr_mask
& IB_QP_RNR_RETRY
) {
988 context
->params1
|= cpu_to_be32(attr
->rnr_retry
<< 13);
989 optpar
|= MLX4_QP_OPTPAR_RNR_RETRY
;
992 if (attr_mask
& IB_QP_RETRY_CNT
) {
993 context
->params1
|= cpu_to_be32(attr
->retry_cnt
<< 16);
994 optpar
|= MLX4_QP_OPTPAR_RETRY_COUNT
;
997 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
998 if (attr
->max_rd_atomic
)
1000 cpu_to_be32(fls(attr
->max_rd_atomic
- 1) << 21);
1001 optpar
|= MLX4_QP_OPTPAR_SRA_MAX
;
1004 if (attr_mask
& IB_QP_SQ_PSN
)
1005 context
->next_send_psn
= cpu_to_be32(attr
->sq_psn
);
1007 context
->cqn_send
= cpu_to_be32(to_mcq(ibqp
->send_cq
)->mcq
.cqn
);
1009 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
1010 if (attr
->max_dest_rd_atomic
)
1012 cpu_to_be32(fls(attr
->max_dest_rd_atomic
- 1) << 21);
1013 optpar
|= MLX4_QP_OPTPAR_RRA_MAX
;
1016 if (attr_mask
& (IB_QP_ACCESS_FLAGS
| IB_QP_MAX_DEST_RD_ATOMIC
)) {
1017 context
->params2
|= to_mlx4_access_flags(qp
, attr
, attr_mask
);
1018 optpar
|= MLX4_QP_OPTPAR_RWE
| MLX4_QP_OPTPAR_RRE
| MLX4_QP_OPTPAR_RAE
;
1022 context
->params2
|= cpu_to_be32(MLX4_QP_BIT_RIC
);
1024 if (attr_mask
& IB_QP_MIN_RNR_TIMER
) {
1025 context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->min_rnr_timer
<< 24);
1026 optpar
|= MLX4_QP_OPTPAR_RNR_TIMEOUT
;
1028 if (attr_mask
& IB_QP_RQ_PSN
)
1029 context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->rq_psn
);
1031 context
->cqn_recv
= cpu_to_be32(to_mcq(ibqp
->recv_cq
)->mcq
.cqn
);
1033 if (attr_mask
& IB_QP_QKEY
) {
1034 context
->qkey
= cpu_to_be32(attr
->qkey
);
1035 optpar
|= MLX4_QP_OPTPAR_Q_KEY
;
1039 context
->srqn
= cpu_to_be32(1 << 24 | to_msrq(ibqp
->srq
)->msrq
.srqn
);
1041 if (!ibqp
->srq
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
1042 context
->db_rec_addr
= cpu_to_be64(qp
->db
.dma
);
1044 if (cur_state
== IB_QPS_INIT
&&
1045 new_state
== IB_QPS_RTR
&&
1046 (ibqp
->qp_type
== IB_QPT_GSI
|| ibqp
->qp_type
== IB_QPT_SMI
||
1047 ibqp
->qp_type
== IB_QPT_UD
)) {
1048 context
->pri_path
.sched_queue
= (qp
->port
- 1) << 6;
1049 if (is_qp0(dev
, qp
))
1050 context
->pri_path
.sched_queue
|= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE
;
1052 context
->pri_path
.sched_queue
|= MLX4_IB_DEFAULT_SCHED_QUEUE
;
1055 if (cur_state
== IB_QPS_RTS
&& new_state
== IB_QPS_SQD
&&
1056 attr_mask
& IB_QP_EN_SQD_ASYNC_NOTIFY
&& attr
->en_sqd_async_notify
)
1062 * Before passing a kernel QP to the HW, make sure that the
1063 * ownership bits of the send queue are set and the SQ
1064 * headroom is stamped so that the hardware doesn't start
1065 * processing stale work requests.
1067 if (!ibqp
->uobject
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
) {
1068 struct mlx4_wqe_ctrl_seg
*ctrl
;
1071 for (i
= 0; i
< qp
->sq
.wqe_cnt
; ++i
) {
1072 ctrl
= get_send_wqe(qp
, i
);
1073 ctrl
->owner_opcode
= cpu_to_be32(1 << 31);
1074 if (qp
->sq_max_wqes_per_wr
== 1)
1075 ctrl
->fence_size
= 1 << (qp
->sq
.wqe_shift
- 4);
1077 stamp_send_wqe(qp
, i
, 1 << qp
->sq
.wqe_shift
);
1081 err
= mlx4_qp_modify(dev
->dev
, &qp
->mtt
, to_mlx4_state(cur_state
),
1082 to_mlx4_state(new_state
), context
, optpar
,
1083 sqd_event
, &qp
->mqp
);
1087 qp
->state
= new_state
;
1089 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
1090 qp
->atomic_rd_en
= attr
->qp_access_flags
;
1091 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
1092 qp
->resp_depth
= attr
->max_dest_rd_atomic
;
1093 if (attr_mask
& IB_QP_PORT
)
1094 qp
->port
= attr
->port_num
;
1095 if (attr_mask
& IB_QP_ALT_PATH
)
1096 qp
->alt_port
= attr
->alt_port_num
;
1098 if (is_sqp(dev
, qp
))
1099 store_sqp_attrs(to_msqp(qp
), attr
, attr_mask
);
1102 * If we moved QP0 to RTR, bring the IB link up; if we moved
1103 * QP0 to RESET or ERROR, bring the link back down.
1105 if (is_qp0(dev
, qp
)) {
1106 if (cur_state
!= IB_QPS_RTR
&& new_state
== IB_QPS_RTR
)
1107 if (mlx4_INIT_PORT(dev
->dev
, qp
->port
))
1108 printk(KERN_WARNING
"INIT_PORT failed for port %d\n",
1111 if (cur_state
!= IB_QPS_RESET
&& cur_state
!= IB_QPS_ERR
&&
1112 (new_state
== IB_QPS_RESET
|| new_state
== IB_QPS_ERR
))
1113 mlx4_CLOSE_PORT(dev
->dev
, qp
->port
);
1117 * If we moved a kernel QP to RESET, clean up all old CQ
1118 * entries and reinitialize the QP.
1120 if (new_state
== IB_QPS_RESET
&& !ibqp
->uobject
) {
1121 mlx4_ib_cq_clean(to_mcq(ibqp
->recv_cq
), qp
->mqp
.qpn
,
1122 ibqp
->srq
? to_msrq(ibqp
->srq
): NULL
);
1123 if (ibqp
->send_cq
!= ibqp
->recv_cq
)
1124 mlx4_ib_cq_clean(to_mcq(ibqp
->send_cq
), qp
->mqp
.qpn
, NULL
);
1130 qp
->sq_next_wqe
= 0;
1140 int mlx4_ib_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
1141 int attr_mask
, struct ib_udata
*udata
)
1143 struct mlx4_ib_dev
*dev
= to_mdev(ibqp
->device
);
1144 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
1145 enum ib_qp_state cur_state
, new_state
;
1148 mutex_lock(&qp
->mutex
);
1150 cur_state
= attr_mask
& IB_QP_CUR_STATE
? attr
->cur_qp_state
: qp
->state
;
1151 new_state
= attr_mask
& IB_QP_STATE
? attr
->qp_state
: cur_state
;
1153 if (!ib_modify_qp_is_ok(cur_state
, new_state
, ibqp
->qp_type
, attr_mask
))
1156 if ((attr_mask
& IB_QP_PORT
) &&
1157 (attr
->port_num
== 0 || attr
->port_num
> dev
->dev
->caps
.num_ports
)) {
1161 if (attr_mask
& IB_QP_PKEY_INDEX
) {
1162 int p
= attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
;
1163 if (attr
->pkey_index
>= dev
->dev
->caps
.pkey_table_len
[p
])
1167 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
&&
1168 attr
->max_rd_atomic
> dev
->dev
->caps
.max_qp_init_rdma
) {
1172 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
&&
1173 attr
->max_dest_rd_atomic
> dev
->dev
->caps
.max_qp_dest_rdma
) {
1177 if (cur_state
== new_state
&& cur_state
== IB_QPS_RESET
) {
1182 err
= __mlx4_ib_modify_qp(ibqp
, attr
, attr_mask
, cur_state
, new_state
);
1185 mutex_unlock(&qp
->mutex
);
1189 static int build_mlx_header(struct mlx4_ib_sqp
*sqp
, struct ib_send_wr
*wr
,
1190 void *wqe
, unsigned *mlx_seg_len
)
1192 struct ib_device
*ib_dev
= &to_mdev(sqp
->qp
.ibqp
.device
)->ib_dev
;
1193 struct mlx4_wqe_mlx_seg
*mlx
= wqe
;
1194 struct mlx4_wqe_inline_seg
*inl
= wqe
+ sizeof *mlx
;
1195 struct mlx4_ib_ah
*ah
= to_mah(wr
->wr
.ud
.ah
);
1203 for (i
= 0; i
< wr
->num_sge
; ++i
)
1204 send_size
+= wr
->sg_list
[i
].length
;
1206 ib_ud_header_init(send_size
, mlx4_ib_ah_grh_present(ah
), &sqp
->ud_header
);
1208 sqp
->ud_header
.lrh
.service_level
=
1209 be32_to_cpu(ah
->av
.sl_tclass_flowlabel
) >> 28;
1210 sqp
->ud_header
.lrh
.destination_lid
= ah
->av
.dlid
;
1211 sqp
->ud_header
.lrh
.source_lid
= cpu_to_be16(ah
->av
.g_slid
& 0x7f);
1212 if (mlx4_ib_ah_grh_present(ah
)) {
1213 sqp
->ud_header
.grh
.traffic_class
=
1214 (be32_to_cpu(ah
->av
.sl_tclass_flowlabel
) >> 20) & 0xff;
1215 sqp
->ud_header
.grh
.flow_label
=
1216 ah
->av
.sl_tclass_flowlabel
& cpu_to_be32(0xfffff);
1217 sqp
->ud_header
.grh
.hop_limit
= ah
->av
.hop_limit
;
1218 ib_get_cached_gid(ib_dev
, be32_to_cpu(ah
->av
.port_pd
) >> 24,
1219 ah
->av
.gid_index
, &sqp
->ud_header
.grh
.source_gid
);
1220 memcpy(sqp
->ud_header
.grh
.destination_gid
.raw
,
1224 mlx
->flags
&= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE
);
1225 mlx
->flags
|= cpu_to_be32((!sqp
->qp
.ibqp
.qp_num
? MLX4_WQE_MLX_VL15
: 0) |
1226 (sqp
->ud_header
.lrh
.destination_lid
==
1227 IB_LID_PERMISSIVE
? MLX4_WQE_MLX_SLR
: 0) |
1228 (sqp
->ud_header
.lrh
.service_level
<< 8));
1229 mlx
->rlid
= sqp
->ud_header
.lrh
.destination_lid
;
1231 switch (wr
->opcode
) {
1233 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY
;
1234 sqp
->ud_header
.immediate_present
= 0;
1236 case IB_WR_SEND_WITH_IMM
:
1237 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE
;
1238 sqp
->ud_header
.immediate_present
= 1;
1239 sqp
->ud_header
.immediate_data
= wr
->ex
.imm_data
;
1245 sqp
->ud_header
.lrh
.virtual_lane
= !sqp
->qp
.ibqp
.qp_num
? 15 : 0;
1246 if (sqp
->ud_header
.lrh
.destination_lid
== IB_LID_PERMISSIVE
)
1247 sqp
->ud_header
.lrh
.source_lid
= IB_LID_PERMISSIVE
;
1248 sqp
->ud_header
.bth
.solicited_event
= !!(wr
->send_flags
& IB_SEND_SOLICITED
);
1249 if (!sqp
->qp
.ibqp
.qp_num
)
1250 ib_get_cached_pkey(ib_dev
, sqp
->qp
.port
, sqp
->pkey_index
, &pkey
);
1252 ib_get_cached_pkey(ib_dev
, sqp
->qp
.port
, wr
->wr
.ud
.pkey_index
, &pkey
);
1253 sqp
->ud_header
.bth
.pkey
= cpu_to_be16(pkey
);
1254 sqp
->ud_header
.bth
.destination_qpn
= cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1255 sqp
->ud_header
.bth
.psn
= cpu_to_be32((sqp
->send_psn
++) & ((1 << 24) - 1));
1256 sqp
->ud_header
.deth
.qkey
= cpu_to_be32(wr
->wr
.ud
.remote_qkey
& 0x80000000 ?
1257 sqp
->qkey
: wr
->wr
.ud
.remote_qkey
);
1258 sqp
->ud_header
.deth
.source_qpn
= cpu_to_be32(sqp
->qp
.ibqp
.qp_num
);
1260 header_size
= ib_ud_header_pack(&sqp
->ud_header
, sqp
->header_buf
);
1263 printk(KERN_ERR
"built UD header of size %d:\n", header_size
);
1264 for (i
= 0; i
< header_size
/ 4; ++i
) {
1266 printk(" [%02x] ", i
* 4);
1268 be32_to_cpu(((__be32
*) sqp
->header_buf
)[i
]));
1269 if ((i
+ 1) % 8 == 0)
1276 * Inline data segments may not cross a 64 byte boundary. If
1277 * our UD header is bigger than the space available up to the
1278 * next 64 byte boundary in the WQE, use two inline data
1279 * segments to hold the UD header.
1281 spc
= MLX4_INLINE_ALIGN
-
1282 ((unsigned long) (inl
+ 1) & (MLX4_INLINE_ALIGN
- 1));
1283 if (header_size
<= spc
) {
1284 inl
->byte_count
= cpu_to_be32(1 << 31 | header_size
);
1285 memcpy(inl
+ 1, sqp
->header_buf
, header_size
);
1288 inl
->byte_count
= cpu_to_be32(1 << 31 | spc
);
1289 memcpy(inl
+ 1, sqp
->header_buf
, spc
);
1291 inl
= (void *) (inl
+ 1) + spc
;
1292 memcpy(inl
+ 1, sqp
->header_buf
+ spc
, header_size
- spc
);
1294 * Need a barrier here to make sure all the data is
1295 * visible before the byte_count field is set.
1296 * Otherwise the HCA prefetcher could grab the 64-byte
1297 * chunk with this inline segment and get a valid (!=
1298 * 0xffffffff) byte count but stale data, and end up
1299 * generating a packet with bad headers.
1301 * The first inline segment's byte_count field doesn't
1302 * need a barrier, because it comes after a
1303 * control/MLX segment and therefore is at an offset
1307 inl
->byte_count
= cpu_to_be32(1 << 31 | (header_size
- spc
));
1312 ALIGN(i
* sizeof (struct mlx4_wqe_inline_seg
) + header_size
, 16);
1316 static int mlx4_wq_overflow(struct mlx4_ib_wq
*wq
, int nreq
, struct ib_cq
*ib_cq
)
1319 struct mlx4_ib_cq
*cq
;
1321 cur
= wq
->head
- wq
->tail
;
1322 if (likely(cur
+ nreq
< wq
->max_post
))
1326 spin_lock(&cq
->lock
);
1327 cur
= wq
->head
- wq
->tail
;
1328 spin_unlock(&cq
->lock
);
1330 return cur
+ nreq
>= wq
->max_post
;
1333 static __be32
convert_access(int acc
)
1335 return (acc
& IB_ACCESS_REMOTE_ATOMIC
? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC
) : 0) |
1336 (acc
& IB_ACCESS_REMOTE_WRITE
? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE
) : 0) |
1337 (acc
& IB_ACCESS_REMOTE_READ
? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ
) : 0) |
1338 (acc
& IB_ACCESS_LOCAL_WRITE
? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE
) : 0) |
1339 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ
);
1342 static void set_fmr_seg(struct mlx4_wqe_fmr_seg
*fseg
, struct ib_send_wr
*wr
)
1344 struct mlx4_ib_fast_reg_page_list
*mfrpl
= to_mfrpl(wr
->wr
.fast_reg
.page_list
);
1346 fseg
->flags
= convert_access(wr
->wr
.fast_reg
.access_flags
);
1347 fseg
->mem_key
= cpu_to_be32(wr
->wr
.fast_reg
.rkey
);
1348 fseg
->buf_list
= cpu_to_be64(mfrpl
->map
);
1349 fseg
->start_addr
= cpu_to_be64(wr
->wr
.fast_reg
.iova_start
);
1350 fseg
->reg_len
= cpu_to_be64(wr
->wr
.fast_reg
.length
);
1351 fseg
->offset
= 0; /* XXX -- is this just for ZBVA? */
1352 fseg
->page_size
= cpu_to_be32(wr
->wr
.fast_reg
.page_shift
);
1353 fseg
->reserved
[0] = 0;
1354 fseg
->reserved
[1] = 0;
1357 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg
*iseg
, u32 rkey
)
1360 iseg
->mem_key
= cpu_to_be32(rkey
);
1365 static __always_inline
void set_raddr_seg(struct mlx4_wqe_raddr_seg
*rseg
,
1366 u64 remote_addr
, u32 rkey
)
1368 rseg
->raddr
= cpu_to_be64(remote_addr
);
1369 rseg
->rkey
= cpu_to_be32(rkey
);
1373 static void set_atomic_seg(struct mlx4_wqe_atomic_seg
*aseg
, struct ib_send_wr
*wr
)
1375 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1376 aseg
->swap_add
= cpu_to_be64(wr
->wr
.atomic
.swap
);
1377 aseg
->compare
= cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1379 aseg
->swap_add
= cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1385 static void set_datagram_seg(struct mlx4_wqe_datagram_seg
*dseg
,
1386 struct ib_send_wr
*wr
)
1388 memcpy(dseg
->av
, &to_mah(wr
->wr
.ud
.ah
)->av
, sizeof (struct mlx4_av
));
1389 dseg
->dqpn
= cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1390 dseg
->qkey
= cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1393 static void set_mlx_icrc_seg(void *dseg
)
1396 struct mlx4_wqe_inline_seg
*iseg
= dseg
;
1401 * Need a barrier here before writing the byte_count field to
1402 * make sure that all the data is visible before the
1403 * byte_count field is set. Otherwise, if the segment begins
1404 * a new cacheline, the HCA prefetcher could grab the 64-byte
1405 * chunk and get a valid (!= * 0xffffffff) byte count but
1406 * stale data, and end up sending the wrong data.
1410 iseg
->byte_count
= cpu_to_be32((1 << 31) | 4);
1413 static void set_data_seg(struct mlx4_wqe_data_seg
*dseg
, struct ib_sge
*sg
)
1415 dseg
->lkey
= cpu_to_be32(sg
->lkey
);
1416 dseg
->addr
= cpu_to_be64(sg
->addr
);
1419 * Need a barrier here before writing the byte_count field to
1420 * make sure that all the data is visible before the
1421 * byte_count field is set. Otherwise, if the segment begins
1422 * a new cacheline, the HCA prefetcher could grab the 64-byte
1423 * chunk and get a valid (!= * 0xffffffff) byte count but
1424 * stale data, and end up sending the wrong data.
1428 dseg
->byte_count
= cpu_to_be32(sg
->length
);
1431 static void __set_data_seg(struct mlx4_wqe_data_seg
*dseg
, struct ib_sge
*sg
)
1433 dseg
->byte_count
= cpu_to_be32(sg
->length
);
1434 dseg
->lkey
= cpu_to_be32(sg
->lkey
);
1435 dseg
->addr
= cpu_to_be64(sg
->addr
);
1438 static int build_lso_seg(struct mlx4_wqe_lso_seg
*wqe
, struct ib_send_wr
*wr
,
1439 struct mlx4_ib_qp
*qp
, unsigned *lso_seg_len
)
1441 unsigned halign
= ALIGN(sizeof *wqe
+ wr
->wr
.ud
.hlen
, 16);
1444 * This is a temporary limitation and will be removed in
1445 * a forthcoming FW release:
1447 if (unlikely(halign
> 64))
1450 if (unlikely(!(qp
->flags
& MLX4_IB_QP_LSO
) &&
1451 wr
->num_sge
> qp
->sq
.max_gs
- (halign
>> 4)))
1454 memcpy(wqe
->header
, wr
->wr
.ud
.header
, wr
->wr
.ud
.hlen
);
1456 /* make sure LSO header is written before overwriting stamping */
1459 wqe
->mss_hdr_size
= cpu_to_be32((wr
->wr
.ud
.mss
- wr
->wr
.ud
.hlen
) << 16 |
1462 *lso_seg_len
= halign
;
1466 static __be32
send_ieth(struct ib_send_wr
*wr
)
1468 switch (wr
->opcode
) {
1469 case IB_WR_SEND_WITH_IMM
:
1470 case IB_WR_RDMA_WRITE_WITH_IMM
:
1471 return wr
->ex
.imm_data
;
1473 case IB_WR_SEND_WITH_INV
:
1474 return cpu_to_be32(wr
->ex
.invalidate_rkey
);
1481 int mlx4_ib_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1482 struct ib_send_wr
**bad_wr
)
1484 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
1486 struct mlx4_wqe_ctrl_seg
*ctrl
;
1487 struct mlx4_wqe_data_seg
*dseg
;
1488 unsigned long flags
;
1492 int uninitialized_var(stamp
);
1493 int uninitialized_var(size
);
1494 unsigned uninitialized_var(seglen
);
1497 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1499 ind
= qp
->sq_next_wqe
;
1501 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1502 if (mlx4_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1508 if (unlikely(wr
->num_sge
> qp
->sq
.max_gs
)) {
1514 ctrl
= wqe
= get_send_wqe(qp
, ind
& (qp
->sq
.wqe_cnt
- 1));
1515 qp
->sq
.wrid
[(qp
->sq
.head
+ nreq
) & (qp
->sq
.wqe_cnt
- 1)] = wr
->wr_id
;
1518 (wr
->send_flags
& IB_SEND_SIGNALED
?
1519 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE
) : 0) |
1520 (wr
->send_flags
& IB_SEND_SOLICITED
?
1521 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED
) : 0) |
1522 ((wr
->send_flags
& IB_SEND_IP_CSUM
) ?
1523 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM
|
1524 MLX4_WQE_CTRL_TCP_UDP_CSUM
) : 0) |
1527 ctrl
->imm
= send_ieth(wr
);
1529 wqe
+= sizeof *ctrl
;
1530 size
= sizeof *ctrl
/ 16;
1532 switch (ibqp
->qp_type
) {
1535 switch (wr
->opcode
) {
1536 case IB_WR_ATOMIC_CMP_AND_SWP
:
1537 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1538 set_raddr_seg(wqe
, wr
->wr
.atomic
.remote_addr
,
1539 wr
->wr
.atomic
.rkey
);
1540 wqe
+= sizeof (struct mlx4_wqe_raddr_seg
);
1542 set_atomic_seg(wqe
, wr
);
1543 wqe
+= sizeof (struct mlx4_wqe_atomic_seg
);
1545 size
+= (sizeof (struct mlx4_wqe_raddr_seg
) +
1546 sizeof (struct mlx4_wqe_atomic_seg
)) / 16;
1550 case IB_WR_RDMA_READ
:
1551 case IB_WR_RDMA_WRITE
:
1552 case IB_WR_RDMA_WRITE_WITH_IMM
:
1553 set_raddr_seg(wqe
, wr
->wr
.rdma
.remote_addr
,
1555 wqe
+= sizeof (struct mlx4_wqe_raddr_seg
);
1556 size
+= sizeof (struct mlx4_wqe_raddr_seg
) / 16;
1559 case IB_WR_LOCAL_INV
:
1560 set_local_inv_seg(wqe
, wr
->ex
.invalidate_rkey
);
1561 wqe
+= sizeof (struct mlx4_wqe_local_inval_seg
);
1562 size
+= sizeof (struct mlx4_wqe_local_inval_seg
) / 16;
1565 case IB_WR_FAST_REG_MR
:
1566 set_fmr_seg(wqe
, wr
);
1567 wqe
+= sizeof (struct mlx4_wqe_fmr_seg
);
1568 size
+= sizeof (struct mlx4_wqe_fmr_seg
) / 16;
1572 /* No extra segments required for sends */
1578 set_datagram_seg(wqe
, wr
);
1579 wqe
+= sizeof (struct mlx4_wqe_datagram_seg
);
1580 size
+= sizeof (struct mlx4_wqe_datagram_seg
) / 16;
1582 if (wr
->opcode
== IB_WR_LSO
) {
1583 err
= build_lso_seg(wqe
, wr
, qp
, &seglen
);
1584 if (unlikely(err
)) {
1589 size
+= seglen
/ 16;
1595 err
= build_mlx_header(to_msqp(qp
), wr
, ctrl
, &seglen
);
1596 if (unlikely(err
)) {
1601 size
+= seglen
/ 16;
1609 * Write data segments in reverse order, so as to
1610 * overwrite cacheline stamp last within each
1611 * cacheline. This avoids issues with WQE
1616 dseg
+= wr
->num_sge
- 1;
1617 size
+= wr
->num_sge
* (sizeof (struct mlx4_wqe_data_seg
) / 16);
1619 /* Add one more inline data segment for ICRC for MLX sends */
1620 if (unlikely(qp
->ibqp
.qp_type
== IB_QPT_SMI
||
1621 qp
->ibqp
.qp_type
== IB_QPT_GSI
)) {
1622 set_mlx_icrc_seg(dseg
+ 1);
1623 size
+= sizeof (struct mlx4_wqe_data_seg
) / 16;
1626 for (i
= wr
->num_sge
- 1; i
>= 0; --i
, --dseg
)
1627 set_data_seg(dseg
, wr
->sg_list
+ i
);
1629 ctrl
->fence_size
= (wr
->send_flags
& IB_SEND_FENCE
?
1630 MLX4_WQE_CTRL_FENCE
: 0) | size
;
1633 * Make sure descriptor is fully written before
1634 * setting ownership bit (because HW can start
1635 * executing as soon as we do).
1639 if (wr
->opcode
< 0 || wr
->opcode
>= ARRAY_SIZE(mlx4_ib_opcode
)) {
1644 ctrl
->owner_opcode
= mlx4_ib_opcode
[wr
->opcode
] |
1645 (ind
& qp
->sq
.wqe_cnt
? cpu_to_be32(1 << 31) : 0);
1647 stamp
= ind
+ qp
->sq_spare_wqes
;
1648 ind
+= DIV_ROUND_UP(size
* 16, 1U << qp
->sq
.wqe_shift
);
1651 * We can improve latency by not stamping the last
1652 * send queue WQE until after ringing the doorbell, so
1653 * only stamp here if there are still more WQEs to post.
1655 * Same optimization applies to padding with NOP wqe
1656 * in case of WQE shrinking (used to prevent wrap-around
1657 * in the middle of WR).
1660 stamp_send_wqe(qp
, stamp
, size
* 16);
1661 ind
= pad_wraparound(qp
, ind
);
1668 qp
->sq
.head
+= nreq
;
1671 * Make sure that descriptors are written before
1676 writel(qp
->doorbell_qpn
,
1677 to_mdev(ibqp
->device
)->uar_map
+ MLX4_SEND_DOORBELL
);
1680 * Make sure doorbells don't leak out of SQ spinlock
1681 * and reach the HCA out of order.
1685 stamp_send_wqe(qp
, stamp
, size
* 16);
1687 ind
= pad_wraparound(qp
, ind
);
1688 qp
->sq_next_wqe
= ind
;
1691 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
1696 int mlx4_ib_post_recv(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
1697 struct ib_recv_wr
**bad_wr
)
1699 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
1700 struct mlx4_wqe_data_seg
*scat
;
1701 unsigned long flags
;
1707 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
1709 ind
= qp
->rq
.head
& (qp
->rq
.wqe_cnt
- 1);
1711 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1712 if (mlx4_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.send_cq
)) {
1718 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
1724 scat
= get_recv_wqe(qp
, ind
);
1726 for (i
= 0; i
< wr
->num_sge
; ++i
)
1727 __set_data_seg(scat
+ i
, wr
->sg_list
+ i
);
1729 if (i
< qp
->rq
.max_gs
) {
1730 scat
[i
].byte_count
= 0;
1731 scat
[i
].lkey
= cpu_to_be32(MLX4_INVALID_LKEY
);
1735 qp
->rq
.wrid
[ind
] = wr
->wr_id
;
1737 ind
= (ind
+ 1) & (qp
->rq
.wqe_cnt
- 1);
1742 qp
->rq
.head
+= nreq
;
1745 * Make sure that descriptors are written before
1750 *qp
->db
.db
= cpu_to_be32(qp
->rq
.head
& 0xffff);
1753 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
1758 static inline enum ib_qp_state
to_ib_qp_state(enum mlx4_qp_state mlx4_state
)
1760 switch (mlx4_state
) {
1761 case MLX4_QP_STATE_RST
: return IB_QPS_RESET
;
1762 case MLX4_QP_STATE_INIT
: return IB_QPS_INIT
;
1763 case MLX4_QP_STATE_RTR
: return IB_QPS_RTR
;
1764 case MLX4_QP_STATE_RTS
: return IB_QPS_RTS
;
1765 case MLX4_QP_STATE_SQ_DRAINING
:
1766 case MLX4_QP_STATE_SQD
: return IB_QPS_SQD
;
1767 case MLX4_QP_STATE_SQER
: return IB_QPS_SQE
;
1768 case MLX4_QP_STATE_ERR
: return IB_QPS_ERR
;
1773 static inline enum ib_mig_state
to_ib_mig_state(int mlx4_mig_state
)
1775 switch (mlx4_mig_state
) {
1776 case MLX4_QP_PM_ARMED
: return IB_MIG_ARMED
;
1777 case MLX4_QP_PM_REARM
: return IB_MIG_REARM
;
1778 case MLX4_QP_PM_MIGRATED
: return IB_MIG_MIGRATED
;
1783 static int to_ib_qp_access_flags(int mlx4_flags
)
1787 if (mlx4_flags
& MLX4_QP_BIT_RRE
)
1788 ib_flags
|= IB_ACCESS_REMOTE_READ
;
1789 if (mlx4_flags
& MLX4_QP_BIT_RWE
)
1790 ib_flags
|= IB_ACCESS_REMOTE_WRITE
;
1791 if (mlx4_flags
& MLX4_QP_BIT_RAE
)
1792 ib_flags
|= IB_ACCESS_REMOTE_ATOMIC
;
1797 static void to_ib_ah_attr(struct mlx4_dev
*dev
, struct ib_ah_attr
*ib_ah_attr
,
1798 struct mlx4_qp_path
*path
)
1800 memset(ib_ah_attr
, 0, sizeof *ib_ah_attr
);
1801 ib_ah_attr
->port_num
= path
->sched_queue
& 0x40 ? 2 : 1;
1803 if (ib_ah_attr
->port_num
== 0 || ib_ah_attr
->port_num
> dev
->caps
.num_ports
)
1806 ib_ah_attr
->dlid
= be16_to_cpu(path
->rlid
);
1807 ib_ah_attr
->sl
= (path
->sched_queue
>> 2) & 0xf;
1808 ib_ah_attr
->src_path_bits
= path
->grh_mylmc
& 0x7f;
1809 ib_ah_attr
->static_rate
= path
->static_rate
? path
->static_rate
- 5 : 0;
1810 ib_ah_attr
->ah_flags
= (path
->grh_mylmc
& (1 << 7)) ? IB_AH_GRH
: 0;
1811 if (ib_ah_attr
->ah_flags
) {
1812 ib_ah_attr
->grh
.sgid_index
= path
->mgid_index
;
1813 ib_ah_attr
->grh
.hop_limit
= path
->hop_limit
;
1814 ib_ah_attr
->grh
.traffic_class
=
1815 (be32_to_cpu(path
->tclass_flowlabel
) >> 20) & 0xff;
1816 ib_ah_attr
->grh
.flow_label
=
1817 be32_to_cpu(path
->tclass_flowlabel
) & 0xfffff;
1818 memcpy(ib_ah_attr
->grh
.dgid
.raw
,
1819 path
->rgid
, sizeof ib_ah_attr
->grh
.dgid
.raw
);
1823 int mlx4_ib_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*qp_attr
, int qp_attr_mask
,
1824 struct ib_qp_init_attr
*qp_init_attr
)
1826 struct mlx4_ib_dev
*dev
= to_mdev(ibqp
->device
);
1827 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
1828 struct mlx4_qp_context context
;
1832 mutex_lock(&qp
->mutex
);
1834 if (qp
->state
== IB_QPS_RESET
) {
1835 qp_attr
->qp_state
= IB_QPS_RESET
;
1839 err
= mlx4_qp_query(dev
->dev
, &qp
->mqp
, &context
);
1845 mlx4_state
= be32_to_cpu(context
.flags
) >> 28;
1847 qp
->state
= to_ib_qp_state(mlx4_state
);
1848 qp_attr
->qp_state
= qp
->state
;
1849 qp_attr
->path_mtu
= context
.mtu_msgmax
>> 5;
1850 qp_attr
->path_mig_state
=
1851 to_ib_mig_state((be32_to_cpu(context
.flags
) >> 11) & 0x3);
1852 qp_attr
->qkey
= be32_to_cpu(context
.qkey
);
1853 qp_attr
->rq_psn
= be32_to_cpu(context
.rnr_nextrecvpsn
) & 0xffffff;
1854 qp_attr
->sq_psn
= be32_to_cpu(context
.next_send_psn
) & 0xffffff;
1855 qp_attr
->dest_qp_num
= be32_to_cpu(context
.remote_qpn
) & 0xffffff;
1856 qp_attr
->qp_access_flags
=
1857 to_ib_qp_access_flags(be32_to_cpu(context
.params2
));
1859 if (qp
->ibqp
.qp_type
== IB_QPT_RC
|| qp
->ibqp
.qp_type
== IB_QPT_UC
) {
1860 to_ib_ah_attr(dev
->dev
, &qp_attr
->ah_attr
, &context
.pri_path
);
1861 to_ib_ah_attr(dev
->dev
, &qp_attr
->alt_ah_attr
, &context
.alt_path
);
1862 qp_attr
->alt_pkey_index
= context
.alt_path
.pkey_index
& 0x7f;
1863 qp_attr
->alt_port_num
= qp_attr
->alt_ah_attr
.port_num
;
1866 qp_attr
->pkey_index
= context
.pri_path
.pkey_index
& 0x7f;
1867 if (qp_attr
->qp_state
== IB_QPS_INIT
)
1868 qp_attr
->port_num
= qp
->port
;
1870 qp_attr
->port_num
= context
.pri_path
.sched_queue
& 0x40 ? 2 : 1;
1872 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1873 qp_attr
->sq_draining
= mlx4_state
== MLX4_QP_STATE_SQ_DRAINING
;
1875 qp_attr
->max_rd_atomic
= 1 << ((be32_to_cpu(context
.params1
) >> 21) & 0x7);
1877 qp_attr
->max_dest_rd_atomic
=
1878 1 << ((be32_to_cpu(context
.params2
) >> 21) & 0x7);
1879 qp_attr
->min_rnr_timer
=
1880 (be32_to_cpu(context
.rnr_nextrecvpsn
) >> 24) & 0x1f;
1881 qp_attr
->timeout
= context
.pri_path
.ackto
>> 3;
1882 qp_attr
->retry_cnt
= (be32_to_cpu(context
.params1
) >> 16) & 0x7;
1883 qp_attr
->rnr_retry
= (be32_to_cpu(context
.params1
) >> 13) & 0x7;
1884 qp_attr
->alt_timeout
= context
.alt_path
.ackto
>> 3;
1887 qp_attr
->cur_qp_state
= qp_attr
->qp_state
;
1888 qp_attr
->cap
.max_recv_wr
= qp
->rq
.wqe_cnt
;
1889 qp_attr
->cap
.max_recv_sge
= qp
->rq
.max_gs
;
1891 if (!ibqp
->uobject
) {
1892 qp_attr
->cap
.max_send_wr
= qp
->sq
.wqe_cnt
;
1893 qp_attr
->cap
.max_send_sge
= qp
->sq
.max_gs
;
1895 qp_attr
->cap
.max_send_wr
= 0;
1896 qp_attr
->cap
.max_send_sge
= 0;
1900 * We don't support inline sends for kernel QPs (yet), and we
1901 * don't know what userspace's value should be.
1903 qp_attr
->cap
.max_inline_data
= 0;
1905 qp_init_attr
->cap
= qp_attr
->cap
;
1907 qp_init_attr
->create_flags
= 0;
1908 if (qp
->flags
& MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK
)
1909 qp_init_attr
->create_flags
|= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
;
1911 if (qp
->flags
& MLX4_IB_QP_LSO
)
1912 qp_init_attr
->create_flags
|= IB_QP_CREATE_IPOIB_UD_LSO
;
1915 mutex_unlock(&qp
->mutex
);